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Article

RiscADA: RISC-V Extension for Optimized Control of External D/A and A/D Converters

by
Cosmin-Andrei Popovici
,
Andrei Stan
*,
Nicolae-Alexandru Botezatu
and
Vasile-Ion Manta
Department of Computer Engineering, Faculty of Automatic Control and Computer Engineering, “Gheorghe Asachi” Technical University of Iași, 700050 Iași, Romania
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(15), 3152; https://doi.org/10.3390/electronics14153152 (registering DOI)
Submission received: 5 July 2025 / Revised: 4 August 2025 / Accepted: 6 August 2025 / Published: 7 August 2025
(This article belongs to the Section Computer Science & Engineering)

Abstract

The increasing interest shared by academia and industry in the development of RISC-V cores, extensions and accelerators becomes fructified by collaborative efforts, like the EU’s ChipsJU, which leverages the design of building blocks, IPs and cores based on RISC-V architecture. A domain capable of benefiting from the RISC-V extensibility is the control of external DACs and ADCs. The proposed solution is an open-source RISC-V extension for optimized control of external DACs and ADCs called RiscADA. The extension supports a parametrizable number of DACs and ADCs, is integrated as a coprocessor beside CVA6 in a SoC by using the CV-X-IF interface, deployed on a Kintex UltraScale+ FPGA and implements ISA extension instructions. After benchmarks with commercial solutions, the results show that CVA6 using RiscADA extension configures external DACs 38.6 × and 10.9× times faster than MicroBlaze V and simple CVA6, both using AXI SPI peripherals. The proposed extension achieves 5.35× and 3.05× times higher sample rates of external ADCs than the two configurations mentioned above. RiscADA extension performs digital signal conditioning 4.52× and 3.1× times faster than the MicroBlaze V and CVA6, both using AXI SPI peripherals. It computes statistics for external ADC readings (minimum, maximum, simple-moving average and over-threshold duration).
Keywords: RISC-V extension; CVA6; FPGA; DAC; ADC RISC-V extension; CVA6; FPGA; DAC; ADC

Share and Cite

MDPI and ACS Style

Popovici, C.-A.; Stan, A.; Botezatu, N.-A.; Manta, V.-I. RiscADA: RISC-V Extension for Optimized Control of External D/A and A/D Converters. Electronics 2025, 14, 3152. https://doi.org/10.3390/electronics14153152

AMA Style

Popovici C-A, Stan A, Botezatu N-A, Manta V-I. RiscADA: RISC-V Extension for Optimized Control of External D/A and A/D Converters. Electronics. 2025; 14(15):3152. https://doi.org/10.3390/electronics14153152

Chicago/Turabian Style

Popovici, Cosmin-Andrei, Andrei Stan, Nicolae-Alexandru Botezatu, and Vasile-Ion Manta. 2025. "RiscADA: RISC-V Extension for Optimized Control of External D/A and A/D Converters" Electronics 14, no. 15: 3152. https://doi.org/10.3390/electronics14153152

APA Style

Popovici, C.-A., Stan, A., Botezatu, N.-A., & Manta, V.-I. (2025). RiscADA: RISC-V Extension for Optimized Control of External D/A and A/D Converters. Electronics, 14(15), 3152. https://doi.org/10.3390/electronics14153152

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