# A New Symmetrical Source-Based DC/AC Converter with Experimental Verification

^{1}

^{2}

^{3}

^{4}

^{5}

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## Abstract

**:**

## 1. Introduction

## 2. Proposed Reduced-Switch Topology

#### 2.1. Circuit Operation of the Proposed Circuit−I

#### 2.2. Circuit Operation of the Proposed Circuit-II

_{1}, S

_{2}, S

_{3}, S

_{4}, S

_{1a}, S

_{4a}) are unidirectional, and three (S

_{2a}, S

_{3a}, S

_{5}) are bi-directional, with four capacitors (V

_{1a}, V

_{2a}, V

_{1}, V

_{2}). It consists of an H-bridge employing the switches S

_{1}, S

_{2}, S

_{3}, S

_{4}that are generally used for polarity generation. As depicted in Figure 2b, cell-a, cell-b, etc., up to cell-n are enhanced as per the desired voltage levels to obtain the generalized configuration of circuit−II. There are two unidirectional and two bi-directional switches, along with two capacitors, in each cell unit, and these cells are cascaded to achieve higher levels, as depicted in Figure 2b. Thus, for generating the n

^{th}voltage level, a cascading of cells till the nth cell is required, which contains two bi-directional switches (S

_{2n}, S

_{3n}), two unidirectional switches (S

_{1n}, S

_{4n}), and two capacitors (V

_{1n}, V

_{2n}). Five switches (S

_{1}, S

_{2}, S

_{3}, S

_{4}, S

_{5}) and two capacitors (V

_{1}, V

_{2}) remain the same throughout the generalized proposed circuit−II.

_{n}is the n

^{th}voltage required to generate the n

^{th}output voltage levels.

- One DC supply with DC/DC converters is employed for the required capacitors.
- One AC supply is fed to the transformer primary side, with isolated multi-windings on the secondary side, then connected to a bridge rectifier, and fed to the required capacitors.
- Every photovoltaic module is connected with DC/DC converters for the required capacitors.
- Photovoltaic modules connected in series with DC/DC converters are employed for the required capacitors.

## 3. Modes of Operation

_{dc,}+3V

_{dc,}+2V

_{dc,}and +V

_{dc}, respectively, whereas four negative cycles, i.e., Mode-6 (−V

_{dc}), Mode-7 (−2V

_{dc}), Mode-8 (−3V

_{dc}), and Mode-9 (−4V

_{dc}), produce four negative voltage output and are shown in Figure 5; the exception is Mode-5, with zero cycles.

## 4. Comparison with other MLI Topologies

_{L}.

## 5. Simulation and Experimental Verification

_{1}, S

_{2}, and S

_{3}are 60 V, 55 V, and 27.5 V, respectively, as shown in Figure 10a. Similarly, in Figure 10b, the blocking voltage of S

_{4}, S

_{5}, and S

_{6}are depicted as 32 V, 110 V, and 110 V, respectively. As shown in Figure 10c, the values of the blocking voltage of S

_{7}, S

_{8}, and S

_{9}are 110 V, 110 V, and −80 V, respectively.

_{1}, V

_{2}, V

_{3}, V

_{4}= 27.5 V, R = 200 Ω, and L = 150 mH at a fundamental frequency of 50 Hz, a prototype is shown. A switching frequency of 6 kHz resulted in an output voltage of 110 V and a load current of 0.71 A. A single DC source was used along with the DC/DC converter to provide equal values of DC magnitude, as shown in Figure 4a. The driver circuit utilized for each power switch is depicted in Figure 11, with the TLP250 serving as an opto-isolator.

_{1}, S

_{2}, S

_{3}); (S

_{4}, S

_{5}, S

_{6}); (S

_{7}, S

_{8}, S

_{9}), were grouped for 10 msec and are depicted in Figure 13a, Figure 13b, and Figure 13c, respectively. The switching pulse patterns of the switches present in circuit−II were similar to those in circuit−I, as shown in Figure 6.

_{1}= V

_{2}= V

_{3}= V

_{4}= V

_{5}= V

_{dc}= 30 V with load values R = 200 Ω and L = 150 mH, the output voltage (peak) and output current are recorded as 145 V and 1.2 A respectively. The value of THD and the simulation output voltage are depicted in Figure 15a and corresponded to 145 V and 11.14%. For 13-level the simulation and the experimentation are performed using the proposed circuit-II topology. The simulation result for the output voltage and THD for 13-level of proposed circuit-II topology for V

_{1}= V

_{2}= V

_{3}= V

_{4}= V

_{5}= V

_{6}= V

_{dc}= 21 V with load values R = 200 Ω and L = 100 mH have been shown in Figure 15b and corresponded to 125.7 V and 9.37% respectively.

## 6. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## Correction Statement

## References

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**Figure 1.**Proposed topology: (

**a**) proposed circuit−I topology; (

**b**) generalized proposed circuit−I topology.

**Figure 2.**Proposed topology: (

**a**) proposed circuit−II topology; (

**b**) generalized proposed circuit−II topology.

**Figure 3.**Different types of configurations of bi-directional switches (

**a**) Common Emitter; IGBT (

**b**) Diode Bridge with one Power Switch (

**c**) Common Collector IGBT.

**Figure 6.**Generated pulse pattern for the proposed inverter (circuit−I and circuit−II) for 9-level output voltage.

**Figure 10.**Blocking voltages across the switches: (

**a**) S

_{1}, S

_{2}, and S

_{3}; (

**b**) S

_{4}, S

_{5}, and S

_{6}; (

**c**) S

_{7}, S

_{8}, and S

_{9}.

**Figure 12.**Simulation results for the 9-level inverter: (

**a**) output voltage and current; (

**b**) %THD of output phase voltage.

**Figure 13.**Switching pulses fed to the power switches of the proposed circuit−I topology: (

**a**) S

_{1}, S

_{2}and S

_{3}; (

**b**) S

_{3}, S

_{4}, and S

_{5}; (

**c**) S

_{6}, S

_{7}, and S

_{8}.

**Figure 15.**Total harmonic distortion of the output voltage of the proposed inverters: (

**a**) 11−level inverter; (

**b**) 13−level inverter.

**Figure 16.**Load voltage and current for the 11-level inverter; (

**a**) 2.5 cycles; (

**b**) different modulation indices.

**Figure 17.**Load voltage and current for the 13-level inverter: (

**a**) 2.5 cycles; (

**b**) different modulation indices.

Modes | Switching States1 = ON; 0 = OFF | Circuit−IVoltages | Circuit−IIVoltages | Stepped Output VoltageGeneration | ||||||||

Circuit−I | ${S}_{1}$ | ${S}_{2}$ | ${S}_{3}$ | ${S}_{4}$ | ${S}_{5}$ | ${S}_{6}$ | ${S}_{7}$ | ${S}_{8}$ | ${S}_{9}$ | ${V}_{1}={V}_{2}={V}_{dc}$ ${V}_{3}={V}_{4}={V}_{dc}$ | ${V}_{1a}={V}_{2a}={V}_{dc}$ ${V}_{1}={V}_{2}={V}_{dc}$ | |

Circuit−II | ${S}_{1a}$ | ${S}_{2a}$ | ${S}_{3a}$ | ${S}_{4a}$ | ${S}_{1}$ | ${S}_{4}$ | ${S}_{3}$ | ${S}_{2}$ | ${S}_{5}$ | |||

Mode-1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | ${V}_{1}+{V}_{2}+{V}_{3}+{V}_{4}$ | ${V}_{1a}+{V}_{2a}+{V}_{1}+{V}_{2}$ | $+4{V}_{dc}$ |

Mode-2 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | ${V}_{1}+{V}_{3}+{V}_{4}$ | ${V}_{1a}+{V}_{1}+{V}_{2}$ | $+3{V}_{dc}$ |

Mode-3 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | ${V}_{3}+{V}_{4}$ | ${V}_{1}+{V}_{2}$ | $+2{V}_{dc}$ |

Mode-4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | ${V}_{4}$ | ${V}_{2}$ | $+{V}_{dc}$ |

Mode-5 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | --- | --- | $+0{V}_{dc}$ |

0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | --- | --- | $+0{V}_{dc}$ | |

Mode-6 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | ${V}_{3}$ | ${V}_{1}$ | $-{V}_{dc}$ |

Mode-7 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | ${V}_{3}+{V}_{4}$ | ${V}_{1}+{V}_{2}$ | $-2{V}_{dc}$ |

Mode-8 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | ${V}_{1}+{V}_{2}+{V}_{3}$ | ${V}_{1a}+{V}_{2a}+{V}_{1}$ | $-3{V}_{dc}$ |

Mode-9 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | ${V}_{1}+{V}_{2}+{V}_{3}+{V}_{4}$ | ${V}_{1a}+{V}_{2a}+{V}_{1}+{V}_{2}$ | $-4{V}_{dc}$ |

MLI Compared with the Proposed Topology | Total Switches (M) | Gate Driver Circuit (N) | Capacitors/Isolated DC Sources (O) | Main Diodes (P) | Switches | |
---|---|---|---|---|---|---|

Unidirectional Switches (Q) | Bi-Directional Switches (R) | |||||

[24] | $2({N}_{L}-1)$ | $2({N}_{L}-1)$ | $\frac{({N}_{L}-1)}{2}$ | $2({N}_{L}-1)$ | $2({N}_{L}-1)$ | --- |

[25] | $\frac{3({N}_{L}-1)}{2}$ | $\frac{3({N}_{L}-1)}{2}$ | $\frac{({N}_{L}-1)}{2}$ | $\frac{3({N}_{L}-1)}{2}$ | $\frac{3({N}_{L}-1)}{2}$ | --- |

[26] | $2({N}_{L}-1)$ | $2({N}_{L}-1)$ | $\frac{({N}_{L}-1)}{2}$ | $2({N}_{L}-1)$ | $2({N}_{L}-1)$ | --- |

[27] | $({N}_{L}+3)$ | $({N}_{L}+3)$ | $\frac{({N}_{L}-1)}{2}$ | $({N}_{L}+3)$ | $({N}_{L}+3)$ | --- |

[28] | $7({N}_{L}-1)/8$ | $7({N}_{L}-1)/8$ | $\frac{({N}_{L}-1)}{2}$ | $\frac{({N}_{L}-1)}{8}$ | $\frac{({N}_{L}-1)}{8}$ | $3\frac{({N}_{L}-1)}{4}$ |

[29] | ${N}_{L}+1$ | ${N}_{L}+1$ | $\frac{({N}_{L}-1)}{2}$ | ${N}_{L}+1$ | ${N}_{L}+1$ | --- |

[30] | $({N}_{L}+5)/2$ | $({N}_{L}+5)/2$ | $\frac{({N}_{L}-1)}{2}$ | 4 | 4 | $({N}_{L}-3)/2$ |

Proposed Circuit−I Topology | $\frac{({N}_{L}+9)}{2}$ | $\frac{({N}_{L}+9)}{2}$ | $\frac{({N}_{L}-1)}{2}$ | $({N}_{L}+3)$ | 6 | $\frac{({N}_{L}-3)}{2}$ |

Proposed Circuit−II Topology | ${N}_{L}$ | ${N}_{L}$ | $\frac{({N}_{L}-1)}{2}$ | $\frac{3({N}_{L}-1)}{2}$ | $\frac{({N}_{L}+3)}{2}$ | $\frac{({N}_{L}-3)}{2}$ |

Cited Papers | Voltage Levels ${\mathit{N}}_{\mathit{L}}$ | Total Switches (M) | Capacitors/Isolated DC Sources (O) | PIV (Peak Inverse Voltage) | TSV (Total Standing Voltage) |
---|---|---|---|---|---|

[24] | 9 | 16 | 4 | 4 V_{dc} | 24 V_{dc} |

[25] | 9 | 12 | 4 | V_{dc} | 12 V_{dc} |

[26] | 9 | 16 | 4 | 3 V_{dc} | 24 V_{dc} |

[27] | 9 | 12 | 4 | V_{dc} | 12 V_{dc} |

[28] | 9 | 7 | 4 | 2 V_{dc} | 13 V_{dc} |

[29] | 9 | 10 | 4 | 4 V_{dc} | 16 V_{dc} |

[30] | 9 | 7 | 4 | 3 V_{dc} | 20 V_{dc} |

Circuit−I and Circuit−II Topology | 9 | 9 | 4 | 4 V_{dc} | 24 V_{dc} |

**Table 4.**Circuit parameters in the simulation and experimental tests and outputs at different levels.

Parameters | Name and Value or Type | |
---|---|---|

Switching parameters IGBT | CT-60AM-18F: 900 V, 60 A V _{on, IGBT} = 1.3 V, V_{on, Dio} = 1.5 V, R_{Dio} = 0.01Ω, R_{IGBT} = 0.11Ω, β = 3 | |

Types of switching devices and their controlling elements | Diode driver Controller, switching frequency | MUR1560G: 600 V, 15 A TLP250: 10–35, ±1.5 A DS1103, 6 kHz |

Common parameters of simulation and experimental tests | 9-level inverter (same for circuit−I topology and circuit−II topologies) (V _{1} = V_{2} = V_{3} = V_{4} = V_{dc} = 27.5 V)R = 200 Ω, L = 150 mH, V _{pk} = 110.3 V, I_{pk} = 0.71 A. | |

11-level inverter, (Circuit−I Topology) (V _{1} = V_{2} = V_{3} = V_{4} = V_{5} = V_{dc} = 30 V)R = 200 Ω, L = 100 mH, V _{pk} = 145 V, I_{pk} = 1.2 A. | ||

13-level inverter, (circuit−II topology) (V _{1} = V_{2} = V_{3} = V_{4} = V_{5} = V_{6} = V_{dc} = 21 V)R = 200 Ω, L = 100 mH, V _{pk} = 125.7 V, I_{pk} = 1.2 A. |

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## Share and Cite

**MDPI and ACS Style**

Mahto, K.K.; Mahato, B.; Chandan, B.; Das, D.; Das, P.; Fotis, G.; Vita, V.; Mann, M.
A New Symmetrical Source-Based DC/AC Converter with Experimental Verification. *Electronics* **2024**, *13*, 1975.
https://doi.org/10.3390/electronics13101975

**AMA Style**

Mahto KK, Mahato B, Chandan B, Das D, Das P, Fotis G, Vita V, Mann M.
A New Symmetrical Source-Based DC/AC Converter with Experimental Verification. *Electronics*. 2024; 13(10):1975.
https://doi.org/10.3390/electronics13101975

**Chicago/Turabian Style**

Mahto, Kailash Kumar, Bidyut Mahato, Bikramaditya Chandan, Durbanjali Das, Priyanath Das, Georgios Fotis, Vasiliki Vita, and Michael Mann.
2024. "A New Symmetrical Source-Based DC/AC Converter with Experimental Verification" *Electronics* 13, no. 10: 1975.
https://doi.org/10.3390/electronics13101975