# Cross-Mesh Clock Network Synthesis

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Related Works

#### 2.1. Clock Tree

#### 2.2. Clock Mesh

#### 2.3. Hybrid Network

## 3. Motivation Example

_{mesh_wire}is the wire’s capacitance from the driving buffer to the gate that is the beginning of a register cluster, Cap

_{gate}is the capacitance of a cluster gate, Cap

_{subtree_wire}is the wire capacitance in a cluster, and Cap

_{reg}is the capacitance of a register. Because we use a clock gate to control a register cluster, it needs a parameter, α, to represent the activity ratio of a cluster. If $\alpha =0.5$, it means this cluster will activate half of the time during the working process. To simplify the problem, we assume that the α of every gate is 0.5 in this example. Note that parameters of power are similar to those of capacitance, while for the other parameters, we assume that the capacitance and power of the 1X gate is 6 pf and 6 pw, and those of 4X gate is 14 pf and 14 pw. Similarly, we assume that the capacitance and power of a register is 5 pf and 5 pw.

_{mesh_wire}= 5 pf and Pwr

_{mesh}

_{_wire}= 5 pw, and Cap

_{subtree_wire}= 5 pf and Pwr

_{subtree}

_{_wire}= 5 pw. Therefore, ${Cap}_{tot}=5+0.5\left(6+5+5\times 2\right)=15.5\mathrm{p}\mathrm{f}$ and ${Pwr}_{tot}=15.5\mathrm{p}\mathrm{w}$. For cluster 2, we assume that Cap

_{mesh_wire}= 10 pf and Pwr

_{mesh}

_{_wire}= 10 pw, and Cap

_{subtree_wire}= 30 pf and Pwr

_{subtree}

_{_wire}= 30 pw. Therefore, ${Cap}_{tot}=10+0.5\left(14+30+5\times 8\right)=52\mathrm{p}\mathrm{f}$ and ${Pwr}_{tot}=52\mathrm{p}\mathrm{w}$. In cluster 2, there are eight registers in the tree topology; thus, it needs to use a 4X gated cell to drive the clock tree. At last, the average capacitance is 33.75 pf and total power consumption is 62.5 pw. Incidentally, Pwr

_{mesh}

_{_wire1}is public in clusters 1 and 2, and we only need to calculate it one time for total power consumption.

_{mesh_wire}and Pwr

_{mesh}

_{_wire}values of clusters 1, 2, and 3 are 5 pf, 13 pf, and 4 pf, and 5 pw, 13 pw, and 4 pw; the Cap

_{subtree_wire}and Pwr

_{subtree}

_{_wire}values are 5 pf, 13 pf, and 14 pf, and 5 pw, 13 pw, and 14 pw. Using Equations (1) and (2), we can obtain the Cap

_{tot}values of clusters 1, 2, and 3, which are 15.5 pf, 32.5 pf, and 24 pf, and the Pwr

_{tot}values of clusters 1, 2, and 3 are 15.5 pw, 32.5 pw, and 24 pw. The average capacitance of this mesh tree is 24 pf and the total power consumption is 63 pw. This optimization method significantly reduces the average capacitance of the driving gate but only has 0.5 pw of extra total power.

_{mesh_wire}and Pwr

_{mesh}

_{_wire}values of clusters 1, 2, and 3 are 5 pf, 13 pf, and 8 pf, and 5 pw, 13 pw, and 8 pw; the Cap

_{subtree_wire}and Pwr

_{subtree}

_{_wire}values are 5 pf, 13 pf, and 14 pf, and 5 pw, 13 pw, and 14 pw. Using Equations (1) and (2), we obtain the Cap

_{tot}values of clusters 1, 2, and 3, which are 15.5 pf, 32.5 pf, and 28 pf, and the Pwr

_{tot}values of clusters 1, 2, and 3 are 15.5 pw, 32.5 pw, and 28 pw. The average capacitance of this mesh tree is 25.3 pf and the total power consumption is 71 pw. Compared to the mesh tree in Figure 2b, it has a little increase in both average capacitance and total power consumption. However, if we only focus on the horizontal mesh wire, it has better average capacitance and total power consumption values which are 24 pf and 43 pw due to cluster 3 being connected to the vertical mesh wire.

_{mesh_wire}and Pwr

_{mesh}

_{_wire}values of clusters 1, 2, and 3 are 4 pf, 5 pf, and 3 pf, and 4 pw, 5 pw, and 3 pw; the Cap

_{subtree_wire}and Pwr

_{subtree}

_{_wire}values are 5 pf, 13 pf, and 14 pf, and 5 pfw 13 pw, and 14 pw; the Pwr

_{mesh}

_{_wire}values of buffer

_{12}and buffer

_{3}are 8 pw and 5 pw. Using the equations, we obtain the Cap

_{tot}values of of clusters 1, 2, and 3, which are 14.5 pf, 24.5 pf, and 23 pf and the Pwr

_{tot}values of clusters 1, 2, and 3 are 14.5 pw, 24.5 pw, and 23 pw. Because there are two driving buffers in the circuit, we analyze the average capacitance and total power consumption for each buffer. For buffer

_{12}, the average capacitance is 19.5 pf and total power consumption is 47 pw. On the other hand, the average capacitance and total power consumption values are 23 pf and 28 pw for buffer

_{3}. This result shows that our cross-mesh architecture can further reduce the capacitance load of each cluster. We cannot compare power consumption between the conventional mesh tree and the proposed cross-mesh tree here directly due to their different structures. Instead, we will discuss it in next paragraph the power consumption of the whole mesh tree.

_{avg}in the subtree denotes the average capacitance of every cluster, while Cap

_{avg}in the whole circuit is the average output capacitance to each driving buffer, and Pwr

_{tot}is the total power consumption of the whole circuit. In this table, we can see that cross-mesh structure has much better results than the three others do.

## 4. Design Flow and Methodology

#### 4.1. Overview

#### 4.2. Cross-Mesh Planning Algorithm

_{x}and Cross-Mesh

_{y}are coordinates of the cross-mesh. After completing mesh wire construction, we start to insert drive buffers in the mesh structure. For the example in Figure 4a, there are four directions of the wire in the tree (red line). At first, we put drive buffers on the center of each piece of mesh wire (orange triangle) as shown in Figure 4b. The mesh tree will use these four buffers to drive cells. Because the complexity of IC design grows drastically, it is insufficient to drive the cross-mesh using only four drive buffers. We divide the original triangular drive area in half using mesh wire as in Figure 4c, adding two additional drive buffers (white triangle) to make up the drive strength. The design with a completed mesh structure is as shown in Figure 4d.

#### 4.3. Register Clustering Algorithm

#### 4.4. Mesh Network-Connecting Algorithm

#### 4.5. Load Balancing Algorithm

_{dummy}, where C

_{target}is the target capacitance, C

_{before}represents the clock gate load capacitance that does not have dummy cells inserted into it, and C

_{dummy}is the capacitance value of the dummy cell. The additional capacitance value, C

_{extra}, is calculated using Equation (7), and the load capacitance of the clock gate subtree is updated using Equation (8). We repeat these steps until all the clock subtree load capacitances are balanced.

## 5. Experiment Results and Discussion

#### 5.1. Analysis of Cross-Mesh Clock Network

#### 5.2. Comparison of Clock Mesh Structures

## 6. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 2.**Motivation example (

**a**) mesh tree (

**b**) clock gating on mesh tree (

**c**) load balancing on mesh tree (

**d**) cross-mesh with clock gating and load balancing.

**Figure 4.**Example of establishing cross-mesh (

**a**) mesh wire (

**b**) drive buffer on the center of mesh wire (

**c**) additional drive buffers to make up the drive strength (

**d**) completed mesh structure.

**Figure 5.**Example of allocating driving buffer (

**a**) four free registers to be classified (

**b**) compare distance to mesh wires (

**c**) connect to drive buffer with less distance (

**d**) connect to drive buffer that has less registers connected to it (

**e**) select drive buffer randomly on equal condition (

**f**) completed allocation.

**Figure 7.**Example of register clustering algorithm (

**a**) each register is a cluster (

**b**) two registers near to each other are chosen (

**c**) merge chosen registers into a cluster and continue to merge other registers (

**d**) completed register clustering.

**Figure 8.**Example of mesh network-connecting algorithm (

**a**) original network (

**b**) divide a group into half and insert drive buffers (

**c**) check load capacitance and connect drive buffers (

**d**) completed mesh network.

**Figure 10.**Example of load balancing algorithm (

**a**) original subtrees (

**b**) the left subtree needs to add dummy cells (

**c**) followed by the right subtree to add dummy cells (

**d**) completed subtrees with load balanced.

Mesh Tree | Subtree | Whole Circuit | ||
---|---|---|---|---|

Cap_{avg} (pf) | Cap_{avg} (pf) | Pwr_{tot} (pw) | ||

Conventional mesh tree | A | 33.75 | 30 | 128.5 |

B | 24 | 31 | 126 | |

C | 25.3 | 39 | 126 | |

Cross-mesh tree | D | 21.2 | 15 | 107 |

Cluster Constraint | Circuit | |||
---|---|---|---|---|

S9234 | S13207 | S38584 | S35932 | |

#Clock Gates | ||||

60% | 11 | 27 | 69 | 80 |

70% | 9 | 23 | 54 | 66 |

80% | 8 | 21 | 46 | 55 |

90% | 8 | 20 | 39 | 46 |

Circuit | Voltage: 1.0 V, Temperature: 25 °C, Cluster Constraint 90% | ||||
---|---|---|---|---|---|

#Gate | Capacitance (pF) | ||||

Non-Cluster | Cluster | Non-Cluster | Cluster | Cap. Reduction | |

s9234 | 211 | 8 | 0.867 | 0.338 | 61.0% |

s13207 | 638 | 20 | 3.408 | 0.906 | 73.4% |

s38584 | 1426 | 39 | 11.746 | 2.086 | 82.2% |

s35932 | 1728 | 46 | 13.556 | 2.425 | 82.1% |

Avg. Capacitance Reduction | 74.7% |

Circuit | Voltage: 1.1 V, Temperature: −40 °C, Cluster Constraint 90% | ||||
---|---|---|---|---|---|

#Gate | Capacitance (pF) | ||||

Non-Cluster | Cluster | Non-Cluster | Cluster | Cap. Reduction | |

s9234 | 211 | 8 | 0.879 | 0.345 | 61.8% |

s13207 | 638 | 20 | 3.444 | 0.924 | 73.2% |

s38584 | 1426 | 41 | 11.824 | 2.155 | 81.8% |

s35932 | 1728 | 47 | 13.651 | 2.484 | 81.8% |

Avg. Capacitance Reduction | 74.4% |

Circuit | Voltage: 0.9 V, Temperature: 125 °C, Cluster Constraint 90% | ||||
---|---|---|---|---|---|

#Gate | Capacitance (pF) | ||||

Non-Cluster | Cluster | Non-Cluster | Cluster | Cap. Reduction | |

s9234 | 211 | 8 | 0.857 | 0.333 | 61.2% |

s13207 | 638 | 9 | 3.377 | 0.879 | 74.0% |

s38584 | 1426 | 40 | 11.676 | 2.064 | 82.3% |

s35932 | 1728 | 47 | 13.471 | 2.393 | 82.2% |

Avg. Capacitance Reduction | 74.9% |

Circuit | Voltage: 1.0 V, Temperature: 25 °C | |||||
---|---|---|---|---|---|---|

Capacitance (pF) | Skew (ps) | |||||

Pre-Opt. | Post-Opt. | Cap. Ratio | Pre-Opt. | Post-Opt. | Skew Reduction | |

s9234 | 0.338 | 0.487 | 1.44× | 100.25 | 10.15 | 89.9% |

s13207 | 0.906 | 1.613 | 1.78× | 402.25 | 9.02 | 97.8% |

s38584 | 2.086 | 2.582 | 1.24× | 323.51 | 12.43 | 96.2% |

s35932 | 2.425 | 2.974 | 1.22× | 318.75 | 10.55 | 96.7% |

Avg. Capacitance Increasing | 1.42× | Avg. Skew Reduction | 95.1% |

Circuit | Voltage: 1.1 V, Temperature: −40 °C | |||||
---|---|---|---|---|---|---|

Capacitance (pF) | Skew (ps) | |||||

Pre-Opt. | Post-Opt. | Cap. Ratio | Pre-Opt. | Post-Opt. | Skew Reduction | |

s9234 | 0.345 | 0.493 | 1.43× | 71.89 | 7.27 | 89.9% |

s13207 | 0.924 | 1.589 | 1.72× | 273.94 | 6.69 | 97.6% |

s38584 | 2.155 | 2.870 | 1.33× | 317.69 | 6.83 | 97.8% |

s35932 | 2.484 | 2.983 | 1.20× | 251.65 | 7.08 | 97.2% |

Avg. Capacitance Increasing | 1.42× | Avg. Skew Reduction | 95.6% |

Circuit | Voltage: 0.9 V, Temperature: 125 °C | |||||
---|---|---|---|---|---|---|

Capacitance (pF) | Skew (ps) | |||||

Pre-Opt. | Post-Opt. | Cap. Ratio | Pre-Opt. | Post-Opt. | Skew Reduction | |

s9234 | 0.333 | 0.477 | 1.43× | 140.86 | 14.39 | 89.8% |

s13207 | 0.879 | 1.479 | 1.68× | 542.28 | 24.66 | 95.4% |

s38584 | 2.064 | 2.766 | 1.34× | 579.97 | 13.21 | 97.7% |

s35932 | 2.393 | 3.160 | 1.32× | 574.61 | 16.76 | 97.1% |

Avg. Capacitance Increasing | 1.44× | Avg. Skew Reduction | 95.0% |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s9234 | 3 × 3 | 88.442 | 1 | 0.656 | 1 |

4 × 4 | 50.391 | 0.57 | 0.637 | 0.97 | |

5 × 5 | 67.982 | 0.77 | 0.641 | 0.98 | |

6 × 6 | 35.962 | 0.41 | 0.666 | 1.02 | |

Cross-Mesh | 10.148 | 0.11 | 0.487 | 0.74 |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s13207 | 5 × 5 | 110.536 | 1 | 1.842 | 1 |

6 × 6 | 111.81 | 1.01 | 1.868 | 1.01 | |

7 × 7 | 94.66 | 0.86 | 1.820 | 0.99 | |

8 × 8 | 87.816 | 0.79 | 1.792 | 0.97 | |

Cross-Mesh | 9.017 | 0.08 | 1.613 | 0.88 |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s38584 | 10 × 10 | 100.044 | 1 | 3.913 | 1 |

11 × 11 | 82.381 | 0.82 | 4.032 | 1.03 | |

12 × 12 | 65.774 | 0.66 | 4.276 | 1.09 | |

13 × 13 | 57.641 | 0.58 | 4.409 | 1.13 | |

Cross-Mesh | 12.426 | 0.12 | 2.583 | 0.66 |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s35932 | 12 × 12 | 80.257 | 1 | 4.526 | 1 |

13 × 13 | 67.558 | 0.84 | 4.500 | 0.99 | |

14 × 14 | 70.897 | 0.88 | 4.720 | 1.04 | |

15 × 15 | 57.558 | 0.72 | 4.774 | 1.05 | |

Cross-Mesh | 10.548 | 0.13 | 2.974 | 0.66 |

Circuit | Capacitance (pF) | ||
---|---|---|---|

Cross-Mesh (Our Proposed) | Uniform Mesh ([21]) | Capacitance Reduction | |

s9234 | 0.487 | 0.666 | 26.7% |

s13207 | 1.613 | 1.792 | 9.9% |

s38584 | 2.582 | 4.409 | 41.4% |

s35932 | 2.974 | 4.774 | 37.7% |

Avg. Capacitance Reduction | 28.9% |

Circuit | Skew (ps) | ||
---|---|---|---|

Cross-Mesh (Our Proposed) | Uniform Mesh ([21]) | Skew Reduction | |

s9234 | 10.148 | 35.962 | 71.7% |

s13207 | 9.017 | 87.816 | 89.7% |

s38584 | 12.426 | 57.641 | 78.4% |

s35932 | 10.548 | 57.558 | 81.6% |

Avg. Skew Reduction | 80.4% |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s9234 | 3 × 3 | 65.378 | 1 | 0.503 | 1 |

4 × 4 | 46.984 | 0.72 | 0.554 | 1.10 | |

5 × 5 | 28.428 | 0.43 | 0.601 | 1.20 | |

6 × 6 | 46.298 | 0.71 | 0.645 | 1.28 | |

Cross-Mesh | 10.148 | 0.16 | 0.487 | 0.97 |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s13207 | 5 × 5 | 126.881 | 1 | 1.360 | 1 |

6 × 6 | 67.638 | 0.53 | 1.512 | 1.11 | |

7 × 7 | 59.068 | 0.47 | 1.591 | 1.17 | |

8 × 8 | 62.39 | 0.49 | 1.616 | 1.19 | |

Cross-Mesh | 9.017 | 0.07 | 1.613 | 1.19 |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s38584 | 10 × 10 | 82.198 | 1 | 3.715 | 1 |

11 × 11 | 60.983 | 0.74 | 3.925 | 1.06 | |

12 × 12 | 55.541 | 0.68 | 4.135 | 1.11 | |

13 × 13 | 55.09 | 0.67 | 4.074 | 1.10 | |

Cross-Mesh | 12.426 | 0.15 | 2.582 | 0.70 |

Circuit | Mesh Size | Skew (ps) | Skew Normalization | Capacitance (pF) | Capacitance Normalization |
---|---|---|---|---|---|

s35932 | 12 × 12 | 64.243 | 1 | 4.207 | 1 |

13 × 13 | 61.974 | 0.96 | 4.271 | 1.02 | |

14 × 14 | 55.178 | 0.86 | 4.485 | 1.07 | |

15 × 15 | 53.917 | 0.84 | 4.629 | 1.10 | |

Cross-Mesh | 10.548 | 0.16 | 2.974 | 0.71 |

Circuit | Capacitance (pF) | ||
---|---|---|---|

Cross-Mesh (Our Proposed) | Non-Uniform ([29]) | Capacitance Reduction | |

s9234 | 0.487 | 0.601 | 18.8% |

s13207 | 1.613 | 1.591 | −1.4% |

s38584 | 2.582 | 4.074 | 36.6% |

s35932 | 2.974 | 4.629 | 35.7% |

Avg. Capacitance Reduction | 22.4% |

Circuit | Skew (ps) | ||
---|---|---|---|

Cross-Mesh (Our Proposed) | Non-Uniform ([29]) | Skew Reduction | |

s9234 | 10.148 | 28.428 | 64.3% |

s13207 | 9.017 | 59.068 | 84.7% |

s38584 | 12.426 | 55.090 | 77.4% |

s35932 | 10.548 | 53.917 | 80.4% |

Avg. Skew Reduction | 76.7% |

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## Share and Cite

**MDPI and ACS Style**

Cheng, W.-K.; Yeh, Z.-M.; Kao, H.-Y.; Huang, S.-H.
Cross-Mesh Clock Network Synthesis. *Electronics* **2023**, *12*, 3410.
https://doi.org/10.3390/electronics12163410

**AMA Style**

Cheng W-K, Yeh Z-M, Kao H-Y, Huang S-H.
Cross-Mesh Clock Network Synthesis. *Electronics*. 2023; 12(16):3410.
https://doi.org/10.3390/electronics12163410

**Chicago/Turabian Style**

Cheng, Wei-Kai, Zih-Ming Yeh, Hsu-Yu Kao, and Shih-Hsu Huang.
2023. "Cross-Mesh Clock Network Synthesis" *Electronics* 12, no. 16: 3410.
https://doi.org/10.3390/electronics12163410