# Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Proposed Design Workflow

- It must be compatible with existing automatic workflows;
- It must not change the initial mathematical model;
- It must not require knowledge of hardware description languages by the power engineer;
- Any modifications to the algorithm design must be understandable to the power engineer;
- It must not require knowledge of the inner structure of the target device;
- It must not require knowledge of HDL design and optimization processes;
- It must be simple enough to make it worth using so that the performance improvement in the final model is obtained at the price of a small additional effort;
- It must be compatible with different numerical methods;
- It must be compatible with complex architectures, such as pipelined operation;
- It must achieve similar occupation figures in the target device compared to manual design;
- It must achieve a similar speed to that achieved by manual design.

## 3. Characterization in a Buck Converter

- Mode 1: S1 is closed and S2 open or S1 and S2 are open (dead time), and the inductor current (${i}_{L}$) is negative (D1 in the conduction state).
- Mode 2: S1 is open and S2 closed and during a dead time in which ${i}_{L}>0$ (D2 in the conduction state).
- Mode 3: if the inductor becomes discharged during a dead time, there is no current flow through the inductor.

Algorithm 1 Calculation of the following value of ${v}_{C}$ and ${i}_{L}$ with the Euler method using a simple ${i}_{L}$ saturation method. | ||

1: | Constant declaration | |

2: | $dtC\leftarrow dt/C$ | |

3: | $dtL\leftarrow dt/L$ | |

4: | $invR\leftarrow 1/R$ | |

5: | function calculateStep($iL,vC,dtC,dtL,invR,S1,S2,{v}_{in}$) | |

6: | if $S1=closed$ OR $(S1=open$ AND $S2=open$ AND $iL<0)$ then | ▹ Mode 1 |

7: | $\Delta vC\leftarrow (iL-vC\times invR)\times dtC$ | |

8: | $\Delta iL\leftarrow ({v}_{in}-vC)\times dtL$ | |

9: | else if $S2=closed$ OR $(S1=open$ AND $S2=open$ AND $iL>0)$ then | ▹ Mode 2 |

10: | $\Delta vC\leftarrow (iL-vC\times invR)\times dtC$ | |

11: | $\Delta iL\leftarrow -vC\times dtL$ | |

12: | else if $iL=0$ then | ▹ Mode 3: $iL=0$ during a dead time |

13: | $\Delta vC\leftarrow -vC\times invR\times dtC$ | |

14: | $\Delta iL\leftarrow 0$ | |

15: | end if | |

16: | $v{C}_{next}\leftarrow vC+\Delta {v}_{C}$ | |

17: | $i{L}_{next}\leftarrow iL+\Delta {i}_{L}$ | |

18: | if $sign\left(i{L}_{next}\right)\ne sign\left(iL\right)$ AND $S1=open$ AND $S2=open$ then | ▹ iL crosses zero during a dead time |

19: | $i{L}_{next}\leftarrow 0$ | |

20: | end if | |

21: | end function |

#### 3.1. HDL Model Design Workflows

#### 3.1.1. Conversion of MATLAB Code into VHDL

**if–then–else**block calculating $\Delta {v}_{C}$ and $\Delta {i}_{L}$, detecting if ${i}_{L}$ crosses zero during a dead time and setting it to zero if so, then storing variables for the next calculation cycle.

#### 3.1.2. Model-Based Design with Simulink

#### 3.1.3. Reference Implementation in VHDL

#### 3.2. Implementation

#### 3.2.1. Generation of VHDL Code from MATLAB

#### 3.2.2. Generation of VHDL Code from Simulink

#### 3.2.3. Initial Comparison

#### 3.2.4. Revised Algorithmic Model

**if–then–else**block to only assignments, with the circuit operation mode (1, 2, or 3) as the output. Intermediate variables are then used to store values that depend on the operating mode, and the algebraic operations that calculate $\Delta {i}_{L}$ and $\Delta {v}_{C}$ should appear only once. Algorithm 2 illustrates this optimized approach.

**if–then–else**block resembles the mode selector block, whose output drives the switching of signals, which in turn are used to calculate $\Delta {i}_{L}$ and $\Delta {v}_{C}$.

Algorithm 2 Optimized version of Algorithm 1, taking the multiplications out of the if–then blocks. Changes in red. | ||

1: | Constant declaration | |

2: | $dtC\leftarrow dt/C$ | |

3: | $dtL\leftarrow dt/L$ | |

4: | $invR\leftarrow 1/R$ | |

5: | function calculateStep($iL,vC,dtC,dtL,invR,S1,S2,{v}_{in}$) | |

6: | $i{C}_{temp}\leftarrow vC\times invR$ | |

7: | if $S1=closed$ OR $(S1=open$ AND $S2=open$ AND $iL<0)$ then | |

8: | $mode\leftarrow 1$ | |

9: | else if $S2=closed$ OR $(S1=open$ AND $S2=open$ AND $iL>0)$ then | |

10: | $mode\leftarrow 2$ | |

11: | else if $iL=0$ then | |

12: | $mode\leftarrow 3$ | |

13: | end if | |

14: | if $mode=1$ OR $mode=2$ then | |

15: | $i{L}_{temp}\leftarrow iL$ | |

16: | else | |

17: | $i{L}_{temp}\leftarrow 0$ | |

18: | end if | |

19: | $\Delta vC\leftarrow (i{L}_{temp}-i{C}_{temp})\times dtC$ | |

20: | if $mode=1$ then | |

21: | $v{2}_{temp}\leftarrow {v}_{in}-vC$ | |

22: | else if $mode=2$ then | |

23: | $v{2}_{temp}\leftarrow -vC$ | |

24: | else | |

25: | $v{2}_{temp}\leftarrow 0$ | |

26: | end if | |

27: | $\Delta iL\leftarrow v{2}_{temp}\times dtL$ | |

28: | $v{C}_{next}\leftarrow vC+\Delta {v}_{C}$ | |

29: | $i{L}_{next}\leftarrow iL+\Delta {i}_{L}$ | |

30: | if $sign\left(i{L}_{next}\right)\ne sign\left(iL\right)$ AND $S1=open$ AND $S2=open$ then | ▹ iL crosses zero during a dead time |

31: | $i{L}_{next}\leftarrow 0$ | |

32: | end if | |

33: | end function |

#### 3.2.5. Reference Implementation in VHDL

#### 3.3. Code Metrics and Resource Usage

## 4. Validation in a More Complex Circuit

#### 4.1. Full-Bridge Converter Equations

#### 4.2. Second-Order Runge–Kutta Model with K-Calculator

#### 4.3. Full-Bridge MATLAB Model

- State 0: Calculates ${M}_{1}$ and ${M}_{3}$.
- State 1: The K-calculator computes ${K}_{1C}$ and ${K}_{1L}$ (13) and (14). In parallel, ${v}_{O}$ is calculated based on the stored values of ${v}_{C}$ and ${i}_{L}$.
- State 2: The K-calculator computes ${K}_{2C}$ and ${K}_{2L}$ (15) and (16).
- State 3: The new values of ${i}_{L}$ and ${v}_{C}$ are calculated.

#### 4.4. Full-Bridge Simulink Model

#### 4.5. Full-Bridge Native VHDL Model

#### 4.6. Summary of the Full-Bridge Model Results

## 5. Experimental Results

## 6. Discussion

## 7. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 8.**Overview of the Simulink model of the full-bridge rectifier with losses. Enabling ports of unit delays are controlled by the state counter (not shown).

**Table 1.**Resource utilization and speed with floating-point models generated from manual VHDL and translation from MATLAB code, both from Table 7 in [17] and from Simscape.

Circuit | Modeling Approach | LUTs | FFs | DSPs | Speed (ns) |
---|---|---|---|---|---|

Buck | VHDL | 2003 | 126 | 9 | 51 |

wo/ losses | MATLAB | 2575 | 64 | 2 | 72 |

Simscape | 10,244 | 397 | 32 | 100 | |

Full-bridge | VHDL | 3646 | 158 | 15 | 70 |

w/ losses | MATLAB code | 16,301 | 100 | 7 | 159 |

Simscape | 17,144 | 360 | 32 | 155 |

Mode 1 | Mode 2 | Mode 3 |
---|---|---|

$\begin{array}{ccc}\hfill \frac{d{v}_{C}}{dt}& =& \frac{{i}_{L}}{C}-\frac{{v}_{C}}{R\times C}\hfill \\ \hfill \frac{d{i}_{L}}{dt}& =& \frac{{v}_{in}}{L}-\frac{{v}_{C}}{L}\hfill \end{array}$ | $\begin{array}{ccc}\hfill \frac{d{v}_{C}}{dt}& =& \frac{{i}_{L}}{C}-\frac{{v}_{C}}{R\times C}\hfill \\ \hfill \frac{d{i}_{L}}{dt}& =& -\frac{{v}_{C}}{L}\hfill \end{array}$ | $\begin{array}{ccc}\hfill \frac{d{v}_{C}}{dt}& =& -\frac{{v}_{C}}{R\times C}\hfill \\ \hfill \frac{d{i}_{L}}{dt}& =& 0\hfill \end{array}$ |

${\mathit{V}}_{\mathit{in}}$ | ${\mathit{V}}_{\mathit{out}}$ | C | L | P | ${\mathit{f}}_{\mathit{sw}}$ | $\mathit{dt}$ |
---|---|---|---|---|---|---|

25 V | 10 V | 35 $\mathsf{\mu}$F | 850 $\mathsf{\mu}$H | 3.5 W | 10 kHz | 1 $\mathsf{\mu}$s |

Variable or Constant | Sign | Integer Bits | Fractional Bits | Total Bits |
---|---|---|---|---|

${i}_{L}$ | yes | 7 | 24 | 32 |

$iLnext$ | yes | 7 | 24 | 32 |

${v}_{C}$ | yes | 10 | 21 | 32 |

$\Delta {i}_{L}$ | yes | −5 | 36 | 32 |

$\Delta {v}_{C}$ | yes | −3 | 33 | 32 |

$invR$ | no | −4 | 36 | 32 |

$dtC$ | no | −5 | 37 | 32 |

$dtL$ | no | −9 | 41 | 32 |

$Vin$ | no | 5 | 27 | 32 |

Code Type | LUTs | FFs | DSPs | Speed (ns) |
---|---|---|---|---|

VHDL from MATLAB | 521 | 68 | 20 | 24 |

VHDL from Simulink | 363 | 64 | 12 | 23 |

**Table 6.**Operations in the MATLAB and Simulink models and their VHDL code, before optimization of the MATLAB code.

Code Type | Additions and Subtractions | Multiplications |
---|---|---|

MATLAB code | 5 | 6 |

VHDL from MATLAB | 5 | 6 |

Simulink schematic | 4 | 3 |

VHDL from Simulink | 4 | 3 |

Code Type | LUTs | FFs | DSPs | Speed (ns) |
---|---|---|---|---|

VHDL from MATLAB | 521 | 68 | 20 | 24 |

VHDL from Simulink | 363 | 64 | 12 | 23 |

VHDL from revised MATLAB | 400 | 67 | 12 | 23 |

Manual VHDL | 287 | 64 | 9 | 25 |

Characteristic | MATLAB | MATLAB | Simulink | Manual |
---|---|---|---|---|

(Initial) | (Optimized) | VHDL | ||

Lines of code | 306 | 284 | 1007 | 107 |

Add/subtract | 5 | 4 | 4 | 4 |

Multiplications | 6 | 3 | 3 | 3 |

If–then–else blocks | 13 | 13 | 14 | 5 |

Signals and variables | 102 | 89 | 95 | 13 |

Processes | 6 | 6 | 7 | 2 |

**Table 9.**Parameters $KR$, $K{V}_{1}$, and $K{V}_{2}$ according to switches’ states and inductor current sign.

${\mathit{Q}}_{1},{\mathit{Q}}_{2},{\mathit{Q}}_{3},{\mathit{Q}}_{4}$ | ${\mathit{i}}_{\mathit{L}}$ | KR | ${\mathit{KV}}_{1}$ | ${\mathit{KV}}_{2}$ |
---|---|---|---|---|

ON, OFF, ON, OFF | any | ${V}_{in}$ | 0 | $2{R}_{DSON}+{R}_{L}$ |

OFF, ON, OFF, ON | any | $-{V}_{in}$ | 0 | $2{R}_{DSON}+{R}_{L}$ |

OFF, OFF, OFF, OFF | >0 | $-{V}_{in}$ | $2{V}_{D}$ | $2{R}_{D}+{R}_{L}$ |

OFF, OFF, OFF, OFF | >0 | ${V}_{in}$ | $-2{V}_{D}$ | $2{R}_{D}+{R}_{L}$ |

ON, OFF, OFF, OFF | >0 | 0 | ${V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

OFF, OFF, ON, OFF | >0 | 0 | ${V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

ON, OFF, OFF, OFF | >0 | ${V}_{in}$ | $-{V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

OFF, OFF, ON, OFF | >0 | ${V}_{in}$ | $-{V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

OFF, ON, OFF, OFF | >0 | ${V}_{in}$ | ${V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

OFF, OFF, OFF, ON | >0 | ${V}_{in}$ | ${V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

OFF, ON, OFF, OFF | >0 | 0 | $-{V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

OFF, OFF, OFF, ON | >0 | 0 | $-{V}_{D}$ | ${R}_{DSON}+{R}_{D}+{R}_{L}$ |

**Table 10.**Resource usage and maximum speed for the full-bridge model (Rows 1 to 3) and comparison with the method proposed in [17] (Rows 4 and 5).

Code Type | LUTs | FFs | DSPs | Speed (ns) | Numerical Method |
---|---|---|---|---|---|

VHDL from MATLAB | 603 | 299 | 12 | 21.2 | Second-order Runge–Kutta |

VHDL from Simulink | 602 | 513 | 12 | 19.0 | Second-order Runge–Kutta |

Manual VHDL | 397 | 326 | 12 | 21.0 | Second-order Runge–Kutta |

VHDL from MATLAB | 837 | 97 | 10 | 19.8 | Forward Euler |

Manual VHDL | 759 | 77 | 7 | 19.3 | Forward Euler |

Characteristic | MATLAB | Simulink | Manual VHDL |
---|---|---|---|

Lines of code | 928 | 1288 | 147 |

Add/subtract | 13 | 13 | 14 |

Multiplications | 12 | 12 | 14 |

If–then–else blocks | 22 | 59 | 5 |

Signals and variables | 338 | 230 | 16 |

Processes | 12 | 29 | 2 |

${\mathit{V}}_{\mathit{in}}$ | C | L | R | ${\mathit{R}}_{\mathit{ESR}}$ | ${\mathit{R}}_{\mathit{D}}$ | ${\mathit{R}}_{\mathit{DSON}}$ | ${\mathit{R}}_{\mathit{L}}$ | ${\mathit{V}}_{\mathit{D}}$ | ${\mathit{f}}_{\mathit{sw}}$ | $\mathbf{dt}$ |
---|---|---|---|---|---|---|---|---|---|---|

200 V | 100 $\mathsf{\mu}$F | 900 $\mathsf{\mu}$H | 200 $\mathsf{\Omega}$ | 360 m$\mathsf{\Omega}$ | 800 m$\mathsf{\Omega}$ | 100 m$\mathsf{\Omega}$ | 5 m$\mathsf{\Omega}$ | 0.7 V | 200 kHz | 116 ns |

Code Type | LUTs | FFs | DSPs | Speed (ns) |
---|---|---|---|---|

Bare model | 602 | 513 | 12 | 19 |

Model with AXI and microprocessor | 1567 | 1773 | 12 | 22 |

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## Share and Cite

**MDPI and ACS Style**

Saralegui, R.; Sanchez, A.; de Castro, A.
Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink. *Electronics* **2023**, *12*, 2786.
https://doi.org/10.3390/electronics12132786

**AMA Style**

Saralegui R, Sanchez A, de Castro A.
Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink. *Electronics*. 2023; 12(13):2786.
https://doi.org/10.3390/electronics12132786

**Chicago/Turabian Style**

Saralegui, Roberto, Alberto Sanchez, and Angel de Castro.
2023. "Efficient Hardware-in-the-Loop Models Using Automatic Code Generation with MATLAB/Simulink" *Electronics* 12, no. 13: 2786.
https://doi.org/10.3390/electronics12132786