# A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation

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## Abstract

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## 1. Introduction

- Neural networks (NNs) of different complexities (shallow and deep) using both supervised [10,11,12,13,14,15,16,17,18] and reinforcement [19,20,21] learning techniques have been proposed in the past six years. These methods have been boosted by the progress in the development of high-performance computing hardware and are gaining attention in the scientific community thanks to their ability to model complex nonlinear problems [22];
- Multi-objective optimization with several heuristic- and stochastic-assisted strategies to explore the search space efficiently: Bayesian [23,24], particle swarm [25], the Gaussian process [26], simulated annealing [27], and genetic algorithms [28,29,30]. These are simulation-based optimizations that rely on a circuit simulator to find a solution. Although global optimization is not an ML technique in the strict sense of the word, it remains a powerful mathematical tool for the automation of circuit design. In contrast, older equation-based techniques as in [31] are no longer considered;

## 2. NN-Based IC Design Automation Methods

#### 2.1. Supervised Learning

- Dataset generation technique;
- Feature selection;
- NN complexity;
- IC fabrication process used;
- Types of circuits targeted;
- Result validation method.

#### 2.1.1. Dataset Generation Technique

#### 2.1.2. Feature Selection

#### 2.1.3. NN Complexity

#### 2.1.4. IC Fabrication Process

#### 2.1.5. Target Circuits

#### 2.1.6. Result Validation Method

#### 2.2. Reinforcement Learning

## 3. Hybrid IC Design Automation Methods

## 4. Discussion and Analysis

#### 4.1. Analysis of the Previous Learning Approaches

#### 4.2. Analysis of Circuit Features

#### 4.3. Transistor Biasing Considerations

## 5. Open Challenges in the Field

## 6. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 3.**Description of the training-dataset-generation approach used in [13].

**Figure 6.**Conceptual bloc diagram of the hybrid technique used in [33].

**Figure 7.**Schematic of the cascode low-noise amplifier circuit used in [32].

**Figure 8.**Bloc diagram of the hybrid approach adopted by [34].

**Figure 10.**Exploration and generalization capabilities of all the studied techniques in the prior state-of-the-art.

${\mathit{W}}_{1}$ | ${\mathit{L}}_{1}$ | ${\mathit{W}}_{2}$ | ${\mathit{L}}_{2}$ | ${\mathit{W}}_{3}$ | ${\mathit{L}}_{3}$ | ${\mathit{W}}_{4}$ | ${\mathit{A}}_{\mathit{d}}$ | ${\mathit{I}}_{\mathit{c}}$ | |
---|---|---|---|---|---|---|---|---|---|

1 | 5.2 | 0.13 | 10 | 0.2 | 2.4 | 0.3 | 0.24 | 56 | 2.3 |

2 | 4.1 | 0.18 | 11 | 0.6 | 2.1 | 0.35 | 0.4 | 112 | 4 |

… | … | … | … | … | … | … | … | … | … |

Starting Point | Generation Technique | Dataset Size | |
---|---|---|---|

[12] | 1 random point | linear sweeps | 1600 |

[13] | 1 expert design | random variation $\pm 30\%$ | 20,000 |

[14] | 1 expert design | random variation $\pm 5\%$ | 9000 |

[15] | existing database | – | 16,600 |

[16] | – | MaxFit software | 10,000 |

[17] | 1 expert design | normal random distribution | 40,000 |

**Table 3.**Complexities in terms of number of neurons for the different NN structures used in prior state-of-the-art.

References | Inputs | Hidden Layers | Output Layer |
---|---|---|---|

[12] | 3 | 24 + 200 | 1 |

[13] | 12 | Missing | 7 |

[14] | 5 | 15 × 1024 | 6 |

[15] | 4 (expanded: 14) | 120, 240, 60 | 8 |

[16] | 6 | 1 × 9 | 12 |

[17] | 5 | 1 × 50 | 9 |

**Table 4.**Prediction error statistics in % per specification in prior state-of-the-art calculated using Equation (1).

[13] | [14] | [15] | [16] | |
---|---|---|---|---|

Power consumption | 14.5 | – | 9.8 | 3.7 |

Gain | 1.1 | 7.2 | 18.2 | 3.7 |

Gain-BW product | 18.1 | 0.1 | 1.3 | 5.9 |

Phase margin | 5.8 | 5.8 | 1.6 | 3.5 |

Common-mode rej. ratio | 3.7 | 1.6 | – | – |

Power-supply rej. ratio | 2.8 | 7.5 | – | – |

Slew rate | 19.1 | – | – | 2.1 |

Average—Std. Dev. | 9.3–7.7 | 4.4–3.4 | 7.7–8 | 3.8–2.5 |

**Table 5.**Comparative summary of supervised and reinforcement learning techniques in the prior state-of-the-art.

[12] | [13] | [14] | [15] | [16] | [17] | [19] | [20] | [21] | |
---|---|---|---|---|---|---|---|---|---|

MLMethod | superv. | superv. | superv. | superv. | superv. | superv. | reinforc. | reinforc. | reinforc. |

Circuit | bandgap reference | 2-stage opamp | 2-stage opamp | volt. combi. diff. opamp | 2-stage opamp | 2-stage opamp | 3-stage opamp | 2-stage opamp-gm | fold.-casc. opamp |

Fabricationtechnology | CMOS missing | CMOS $<1$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $<1$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $0.13$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $0.18$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $0.18$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $0.18$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS 45 $\mathrm{n}$$\mathrm{m}$ | CMOS 65 $\mathrm{n}$$\mathrm{m}$ |

Perform.features | 3 | 12 | 5 | 4 (exp. 14) | 6 | 5 | 6 | 4 | 4 |

Designparameters | 1 | 7 | 6 | 8 | 12 | 9 | 17 | 11 | 16 |

NNcomplexity | 24 + 200 + 1 | 100 + 200 + 7 | $15\phantom{\rule{3.33333pt}{0ex}}\times \phantom{\rule{3.33333pt}{0ex}}1024$ + 6 | 120 + 240 + 60 + 8 | $1\phantom{\rule{3.33333pt}{0ex}}\times \phantom{\rule{3.33333pt}{0ex}}9$ + 12 | 50 + 9 | missing | $3\phantom{\rule{3.33333pt}{0ex}}\times \phantom{\rule{3.33333pt}{0ex}}50$ + 11 | 3 hidden layers |

Averageerror (%) | 0.25 | 7.8 | 4.4 | 7.7 | 3.7 | <10 | missing | 3.7 | missing |

Datasetsize | ∼1600 | 20,000 | 9000 | 16,600 | 10,000 | 40,000 | N/A | N/A | N/A |

Generationtime | missing | 28 h | missing | 0 (existing) | 3.6 h | 16 h | N/A | N/A | N/A |

Trainingtime | missing | 19 min | 18 min | 1 h | 1 h | 30 min | 30 h | 1.6 h | missing |

[32] | [33] | [34] | [35] | [36] | [37] | |
---|---|---|---|---|---|---|

Circuit | cascode LNA induc. deg. | fold.-casc. opamp Vth-bias | 2-stage opamp-gm | fold.-casc. opamp Vth-bias | charge-pump and fold.-casc. opamp | rail-to-rail opamp 5th-ord. filter |

Fabricationtechnology | CMOS $0.18$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $0.13$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS 45 $\mathrm{n}$$\mathrm{m}$ | CMOS $0.13$ $\mathsf{\mu}$$\mathrm{m}$ | CMOS $40/55$ $\mathrm{n}$$\mathrm{m}$ | CMOS $0.18/0.13$ $\mathsf{\mu}$$\mathrm{m}$ |

Perform.features | 6 | 5 (expanded 20) | 3 | 4 | 6/3 | 4/3 |

Designparameters | 10 | 19 | 11 | 19 | 16/13 | 9/8 |

NNcomplexity | 17 + 10 | $1\phantom{\rule{3.33333pt}{0ex}}\times \phantom{\rule{3.33333pt}{0ex}}100$ + 19 | $5\phantom{\rule{3.33333pt}{0ex}}\times \phantom{\rule{3.33333pt}{0ex}}20\phantom{\rule{3.33333pt}{0ex}}+\phantom{\rule{3.33333pt}{0ex}}3$ | missing | (25 + 10 + 13)/(10 + 13) | (8 + 9)/(16 + 3) |

Averageerror (%) | 6.6 | ∼1 | missing | 0.4 | missing | 0.5/0.8 |

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**MDPI and ACS Style**

Mina, R.; Jabbour, C.; Sakr, G.E.
A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation. *Electronics* **2022**, *11*, 435.
https://doi.org/10.3390/electronics11030435

**AMA Style**

Mina R, Jabbour C, Sakr GE.
A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation. *Electronics*. 2022; 11(3):435.
https://doi.org/10.3390/electronics11030435

**Chicago/Turabian Style**

Mina, Rayan, Chadi Jabbour, and George E. Sakr.
2022. "A Review of Machine Learning Techniques in Analog Integrated Circuit Design Automation" *Electronics* 11, no. 3: 435.
https://doi.org/10.3390/electronics11030435