Reliability Analysis and Fault-Tolerant Operation in a Multilevel Inverter for Industrial Application

Abstract

The extensive employment of power semiconductor devices in multilevel inverters (MLIs) has the consequence of increased failure probabilities. With numerous applications demanding highly reliable inverters, several fault-tolerant schemes have been devised to address switch open-circuit faults. This paper analyzes a multilevel inverter topology for IGBT modules undergoing open-circuit faults, a major impediment to reliable operation within a power converter. Reconfiguration of modulation is performed post-fault. A modulation scheme is implemented across failure modes as a hybrid of nearest level control and selective harmonic elimination. Reliability assessment of the topology is performed, including a comparison with previous literature in terms of component requirements and reliability. Simulation results validate the proposed solutions.

1. Introduction

The changing global paradigm about the electrical power sector with large scale renewable generation [1], high-voltage DC (HVDC) transmission systems, rapid electrification in automobiles [2], onboard power systems for aviation and marine applications [3,4], and introduction of the smart grid vision has enlarged the role of power electronic converters more than ever. The dc–ac conversion has extensive applications with MLIs (multilevel inverters) being the primary asset. The superiority of MLIs is vindicated by their excellent harmonic profile, lower switching losses and heat generation, and higher efficiency, a requirement of lower size filters with additional benefits of fault tolerance over the earlier established two-level inverters [5,6,7].

Nevertheless, an increased number of power semiconductors and circuit components like dc sources and capacitors cumulatively increase the probability of fault occurrence thus creating reliability issues [8,9]. Many applications in harsh environments and long operation hours demand highly reliable converters, e.g., power networks in rural areas, critical medical equipment power supplies, aircraft, and naval power systems from a safety viewpoint, satellite systems with unfeasible maintenance, or a wind farm or solar farm with extensive and widely distributed parts [10,11,12,13]. In field systems, it is observed that the power electronic converters are generally the least reliable assemblies and create significant maintenance costs [14]. Demonstrably, a survey concludes that inverters are the source for 37% of unexpected maintenance and 59% of maintenance costs during the 5-year life cycle of a 3.5 MW PV system. This validates that reliability performance must be addressed in the design phase with the traditional efficiency and power density issues.

To address these drawbacks, several topologies have been proposed with either the goal of reducing switch count hence decreasing fault probability or incorporating fault tolerance in the topology. The topology proposed in [15] demonstrates only partial fault-tolerance capabilities with reconfiguration possible for a fault on particular selected switches. Moreover, the topology uses more components while producing lesser voltage levels than the proposed topology. The combination of Cascaded H-Bridge (CHB) and neutral point clamped (NPC) for a fault-tolerant MLI is observed in [15] with complete fault tolerance on every switch, but with the added requirements of relays and transformers for post-fault operation. Extensive use of redundancy is carried out in [16] for fault tolerance of the topology. This, however, leads to an unusually large device count as well as capacitor voltage balancing issues after the fault. Likewise, the proposed topology uses redundant states in [17] for fault management. This, however, leads to twice the number of components as well as a rise in cost and reduced efficiency of the overall circuit. Topologies proposed in [18,19] circumvent the faulty cells by applying reconfiguration control mechanisms. The limitation is the unutilized dc sources belonging to the faulty cells. The MLI topology proposed in [20] is unable to tolerate fault on a bidirectional switch present between load and capacitor. The modified neutral point clamped (NPC) MLI topology proposed in [21,22,23] exhibits fault tolerance while adding the fourth leg of FC (flying capacitor) topology for redundancy. This solution does not provide fault tolerance to switches present in the inner leg, hence only is partial fault-tolerant. Additionally, the component count is significantly increased. Relays are employed to make the classical CHB topology fault-tolerant in [24,25]. However, many DC sources and conducting switches used during both pre-fault and post-fault operations have a negative impact on their reliability.

The topologies mentioned above show various drawbacks like high-power electronic device or capacitor count, capacitor voltage balancing issues, or partial fault tolerance. This paper investigates the fault-tolerant operation of a reduced device counts asymmetrical multilevel inverter topology. The topology [26] investigated in this paper exhibits fault tolerance with a lack of redundant unutilized switches or capacitors as well as the development of an open-circuit fault and mitigation method, which are verified through simulation results. Reliability analysis of the topology and a comparative analysis of the performance of the topology is also presented to demonstrate the feasibility of the fault-tolerance mechanism.

2. Analysis of the Topology

The schematic structure of the topology is illustrated in Figure 1. The components used comprise 10 unidirectional switches (bidirectional current flow and unidirectional blocking of voltage) and 1 bidirectional switch (consisting of two switches in common emitter configuration) with two pairs of dc voltage sources each of V_dc and 3 V_dc. Healthy topology operation produces 15 levels 0 to ± 7 V_dc of output load voltage. Diodes D₁, D₂, D₃, D₄, D₅, and D₆ are present to tackle the flyback effect at the instant of fault occurrence. The switching states with all the redundancies are displayed in Table 1.

Figure 1. Structure of multilevel inverter topology.

Table 1. Fault management for each switch.

S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11	Vout
1	0	1	1	0	0	0	0	0	0	1	Zero
0 0	1 1	1 0	1 0	0 0	0 1	0 1	0 0	0 0	0 0	1 1	Vdc
0	0	1	0	1	0	0	1	0	1	0	2 Vdc
1 0	0 0	1 1	0 0	1 1	0 0	0 0	0 0	0 1	0 1	1 0	3 Vdc
0	1	1	0	1	0	0	0	0	0	1	4 Vdc
0	0	1	0	0	1	0	1	0	1	0	5 Vdc
0	0	1	0	0	1	0	0	1	1	0	6 Vdc
1 0	0 1	1 1	0 0	0 0	1 1	0 0	0 0	0 0	0 0	1 1	7 Vdc
0	0	0	0	0	1	1	0	1	1	0	Zero
0 0	0 0	0 1	0 1	0 0	1 0	1 0	1 1	0 0	1 1	0 0	−Vdc
0	1	0	0	1	0	1	0	0	0	1	−2 Vdc
0 1	0 0	0 0	0 0	1 1	0 0	1 1	0 0	1 0	1 0	0 1	−3 Vdc
0	0	0	0	1	0	1	1	0	1	0	−4 Vdc
0	1	0	1	0	0	1	0	0	0	1	−5 Vdc
0	0	0	1	0	0	1	0	1	1	0	−6 Vdc
1 0	0 0	0 0	1 1	0 0	0 0	1 1	0 1	0 0	0 1	1 0	−7 Vdc

3. Fault-Tolerance Approach

Contrary to topologies developed in [15], the investigated topology does not employ any external relays or redundant switches for fault resilience. The outcome is decreased efficiency and increased cost as the redundant components stand unutilized during healthy operation. Comparatively, all switches of the proposed topology are utilized pre-fault resulting in 100% utilization. A fault is tolerated on all switches leading to complete fault tolerance. The following section deals with fault conditions and fault mitigation.

3.1. Fault Conditions

Open-circuit faults on switches cause unavailability of particular voltage levels. The conditions arising from switch failures are listed in Table 2. Unattended faults lead to poor harmonic profiles but also a dc offset which is unacceptable for any load. For eliminating the dc offset the post-fault output voltage must be symmetric.

Table 2. Fault management for each switch.

Faulty Switch	Voltage Levels Lost	Levels Regained Post Reconfiguration
S1 or S9	±3 Vdc, ±6 Vdc	All
S2 or S8	±Vdc, ±2 Vdc, ±4 Vdc, ±5 Vdc, ±7 Vdc	±3 Vdc, ± 6Vdc
S3 or S7	±2 Vdc to ±7 Vdc	±Vdc
S4 or S6	±5 Vdc, ±6 Vdc, ±7 Vdc	±Vdc, ±2 Vdc, ±3 Vdc, ±4 Vdc
S5	±2 Vdc, ± 3 Vdc, ±4 Vdc	±Vdc, ±5 Vdc, ±6 Vdc, ±7 Vdc
S10 or S11	±Vdc, ±2 Vdc, ±4 Vdc, ±5 Vdc, 7 Vdc	±3 Vdc, ±6 Vdc

3.2. Fault Correction

Post occurrence of a fault, the waveform distortion is minimized using reconfiguration of the modulation strategy. Unequal voltage levels remain post-fault as in a fault in S4/S6 or S5.

The switching angles obtained after Selective Harmonic Elemination (SHE) are rounded off to the nearest angle for compatibility with Nearest Level Modulation-Pulse Width Modulation (NLM-PWM) scheme. The modulation thus implemented is a combination of Nearest Level Modulation (NLM) and SHE methods.

4. Simulation Results

The performance of the proposed topology was verified in MATLAB-Simulink™ R2016b and PLECS™ version 4.0.8 environment using Intel^® Core™ i5-3210M 2.50 GHz simulation. The associated parameters are listed in Table 3. The modulation scheme executed was nearest level control (NLC) PWM for load voltage control. The NLC causes switching transitions at a low switching frequency, thus minimizing the switching losses and enhancing the inverter reliability. Model parameters are listed in Table 3. The results under healthy operation and faulty conditions are presented.

Table 3. Simulation parameters.

Parameter	Value
Voltage sources	100 V
	300 V
Load impedance	50 Ω, 100 mH
Modulating frequency	50 Hz

4.1. Healthy Operation

Following the simulation, the output voltage produced exhibits 15 levels with each level of 100 V and a peak of 700 V. Figure 2 and Figure 3 depict the conduction diagram for various states in positive half cycle of operation.The harmonic profile of the waveform conforms to the IEEE 519-2014 standard of generating a total harmonic distortion (THD) below 5% [27]. Figure 4 depicts the resultant output waveforms.

Figure 2. Positive conduction states (part 1). (a) State 0 (b) State 1 (c) State 2 (d) State 3.

Figure 3. Positive conduction states (part 2). (a) State 4 (b) State 5 (c) State 6 (d) State 7.

Figure 4. Simulation results of the proposed structure during healthy operation comprising (a) load voltage, (b) magnified view of load voltage, (c) load current, (d) magnified view of load current, (e) voltage harmonic characteristics acquired from Fourier analysis, and (f) current harmonic characteristics.

4.2. Fault-Tolerance

Three situations can ensue from an open-circuit malfunction on an individual switch. However, due to inbuilt fault-tolerant operation, reduced voltage levels and diminished output power continue to be supplied at the load terminals.

The first situation involves preserving every voltage level and consequently the output power rating post-detection and mitigation of fault. This is observed in the case of S1 or S9 fault, where redundant states are employed through modulation reconfiguration following fault detection. As for the second situation, in cases of open-circuited S2, S3, S4, S6, S7, S8, S10, or S11, the peak level 7 V_dc is lost additionally, which expedites to decrement in output power rating as well. In case of a fault in S5, level 7 V_dc is not lost, thus the output power rating is conserved.

4.3. S₉ or S₁ Fault

Following an open-circuit fault situation in S₉ or S₁, the loss of levels ±3 V_dc and ±6 V_dc is mitigated by reconfiguring using redundant states, leading to all seven levels being produced post-fault and the load voltage being unaffected. Figure 5 illustrates the waveforms concerned with the S₉ fault which can also represent S₁ fault conditions.

Figure 5. Simulation results for S₉ fault for (a) load voltage, (b) load current, (c) fault detection signal, and (d) voltage harmonics profile.

4.4. S₂, S_8, S_10, and S₁₁ Fault

When an open-circuit fault occurs in S₂ or S₈, the levels ±V_dc, ±2 V_dc, ±4 V_dc, ±5 V_dc, and ±7 V_dc are lost, and levels ±3 V_dc and ±6 V_dc can only be regenerated through reconfiguration. Furthermore, for obtaining the ideal switching angles, SHE is executed with the resulting angles being rounded off to the nearest NLC values for a better harmonic profile. The resulting waveforms are illustrated in Figure 6.

Figure 6. Simulation results for S8 fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, (e) diode current, and (f) current harmonics profile.

4.5. S₃ or S₇ Fault

Open-circuit failure on S3 or S7 leads to loss of all levels except ± Vdc levels. SHE is implemented for the reduction of harmonics post-fault. Minimum power is obtained post-fault in this scenario with the THD being the highest among other cases. Although the reduced power is still more useful for a critical load than no power at all. Figure 7 shows the results.

Figure 7. Simulation results for S₃ fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, (e) diode current, and (f) current harmonics profile.

4.6. S₄ or S₆ Fault

Open-circuit failure in S₄ or S₆ leads to loss of levels ±5 V_dc, ±6 V_dc, ±7 V_dc with levels ±V_dc, ±2 V_dc, ±3 V_dc, ±4 V_dc prevailing through modulation reconfiguration. The execution of SHE is done post-fault for refining the harmonic profile. The resulting waveforms are displayed in Figure 8 and Figure 9.

Figure 8. Simulation results for S₆ fault for (a) load voltage, (b) load current, (c) fault detection signal, and (d) voltage harmonics profile.

Figure 9. Simulation results for S₆ fault for (a) diode current and (b) current harmonic profile.

4.7. S₅ Fault

An open-circuit fault in S₅ leads to loss of levels ±2 V_dc, V_dc, V_dc with levels ±V_dc, ±5 V_dc, ±6 V_dc, ±7 V_dc being generated by the application of modulation reconfiguration. The dc component remains zero during fault; therefore, the root mean square (RMS) value of load voltage is also required for fault detection. SHE is applied for obtaining the optimum waveform to minimize the lower-order harmonics. The resulting waveforms are discussed in Figure 10.

Figure 10. Simulation results for S₅ fault for (a) load voltage, (b) load current, (c) fault detection signal, (d) voltage harmonics profile, and (e) current harmonics profile.

5. Reliability Analysis

Semiconductor devices are majorly prone to faults in an MLI. Nonetheless, the inherent fault-tolerant capabilities of the MLI amplify its reliability due to the provision of continued operation after the fault.

5.1. Component Failure Rate Evaluation

The failure rate of the various components depends on multiple factors derived from MIL-HDBK-217F [28], like voltage rating, application, thermal characteristics, etc. The failure rate of a semiconductor switch is derived as:

$${\mathsf{\lambda }}_{\mathrm{s}}{=\mathsf{\lambda }}_{\mathrm{b}}{ \times \mathsf{\pi }}_{\mathrm{T}}{ \times \mathsf{\pi }}_{\mathrm{A}}{ \times \mathsf{\pi }}_{\mathrm{R}}{ \times \mathsf{\pi }}_{\mathrm{S} }{\times \mathsf{\pi }}_{\mathrm{Q} }{\times \mathsf{\pi }}_{\mathrm{E}}$$

(1)

where λ_b is the base failure rate being equal to 0.00074.

${\mathsf{\pi }}_{\mathrm{T}}$ is the junction temperature factor and ${\mathsf{\pi }}_{\mathrm{R}}$ is the power rating factor and are both dependent on switch power loss values. The application factor ${\mathsf{\pi }}_{\mathrm{A}}$ corresponds to switching. The quality factor is taken for JANTX quality, and the analysis is done for a benign ground environment.

5.2. Power Loss Analysis

Switching losses and conduction losses are the two parts of the device losses. Conduction losses in an IGBT can be evaluated using (2) and a diode using (3). The fundamental period observes a total conduction loss of magnitude equal to (4). The various constants are determined by the datasheet of the device.

$$P_{ }{}_{c_{sw}}=V_{sw}i\left(t\right)+R_s{i}^{\beta }\left(t\right),$$

(2)

$$P_{ }{}_{c_D}=V_{D}i\left(t\right)+R_D{i}^2\left(t\right),$$

(3)

$${\mathrm{P}}_{\mathrm{c} }={\displaystyle \sum }_{k=1}^{N_{sw}}\frac{1}{2\pi }{{\displaystyle \int }}_0^{2\pi }\left(V_{sw}i\left(t\right)+R_s{i}^{\beta }\left(t\right)\right)dt+{\displaystyle \sum }_{k=1}^{N_D}\frac{1}{2\pi }{{\displaystyle \int }}_0^{2\pi }(V_{D}i\left(t\right)+R_D{i}^2\left(t\right))dt.$$

(4)

Above, V_sw represents the voltage drop across the switch when it is ON and V_D represents voltage drop across a diode. Non-ideal switching transitions give rise to switching losses in the circuit. With a linear assumption of current and voltage variation during switching, we arrive at the following relation for switching loss

$${\mathrm{P}}_{\mathrm{s} }=\left[{\displaystyle \sum }_{k=1}^{Ns}\left( N_{O{N}_k}{E}_{O{N}_k}+N_{OF{F}_k}{E}_{OF{F}_k}\right) \right]\times f,$$

(5)

The number of switching transitions to ON and OFF states of the switches respectively is stood for by $N_{O{N}_k}$ and $N_{OF{F}_k}$ with $E_{O{N}_k}$ and $E_{OF{F}_k}$ correspondingly equal to the associated energy losses for the kth device, f is the fundamental frequency. The sum total loss is:

$$P_{\mathrm{loss} }=P_c+P_s$$

(6)

With the power loss of every device known beforehand, the steady-state junction temperature of every switch can be determined. Thermal modeling analysis was implemented in PLECS software with the load as 50 + 50j Ω. IGBT with diode IKW40N65ES5 data was used for thermal modeling. The thermal description of the joule losses for the IGBT and Diode is given in Figure 11 and Figure 12. Respectively. The calculated values of π_R, π_T, and π_S are given in Table 4.

Figure 11. IGBT thermal description corresponding to (a) Turn ON losses, (b) Turn OFF losses, and (c) conduction losses.

Figure 12. Diode thermal description corresponding to (a) Turn OFF losses and (b) conduction losses.

Table 4. Comparative features.

Features	NPC	FC	CHB	[15]	[16]	[20]	[24]	[25]	[29]	Proposed
Number of DC voltage sources	1	1	4	2	1	2	4	4	3	4
Required number of capacitors	0	28	0	0	7	2	0	0	0	0
Number of Diodes required	56	0	0	2	0	0	0	0	0	6
Number of IGBTs required	16	16	16	8	22	12	16	20	12	12
Number of gate drivers required	16	16	16	7	22	9	16	20	9	11
Number of Relays	0	0	0	2	0	0	0	0	0	0
Number of Transformers	0	0	0	1	0	0	0	0	0	0
Number of voltage levels generated	9	9	9	5	9	9	9	9	7	15
Fault-tolerant operation	NO	NO	YES	YES	YES	YES	YES	YES	YES	YES
Redundant switches required	-	-	YES	NO	YES	NO	YES	YES	YES	NO

5.3. Derivation of the Reliability Function

The reliability function for a device, according to [28] is defined as

$$R\left(t\right)=1-{{\displaystyle \int }}_0^{1}f\left(t\right)dt=1-{{\displaystyle \int }}_0^1\begin{array}{c}\left(\lambda e^{-\lambda t}\right)dt=1-e^{-\lambda t},\\ \end{array}$$

(7)

$$f\left(t\right)=\lambda e^{-\lambda t }$$

(8)

where $f\left(t\right)$ is the probability of failure of a device in a given period. The reliability function of the topology is derived using Equations (7) and (8) and is represented by Equation (9). The first term of the equation reflects the healthy mode of operation with the succeeding terms added for various cases of fault tolerance through modulation reconfiguration for fault in any one switch.

$$\begin{array}{c}R\left(t\right)={(e^{-\lambda 1t})}^2{(e^{-\lambda 2t})}^2{(e^{-\lambda 3t})}^2{(e^{-\lambda 4t})}^2{(e^{-\lambda 5t})}^2{(e^{-\lambda 10t})}^2+\\ 2\left(1-e^{-\lambda 1t}\right){(e^{-\lambda 2t})}^2{(e^{-\lambda 3t})}^2{(e^{-\lambda 4t})}^2{(e^{-\lambda 5t})}^2{(e^{-\lambda 10t})}^2+2\left(-e^{-\lambda 2t}\right) {(e^{-\lambda 1t})}^2{(e^{-\lambda 3t})}^2{(e^{-\lambda 4t})}^2{(e^{-\lambda 5t})}^2{(e^{-\lambda 10t})}^2\\ +2\left(1-e^{-\lambda 3t}\right) {(e^{-\lambda 1t})}^2{(e^{-\lambda 2t})}^2{(e^{-\lambda 4t})}^2{(e^{-\lambda 5t})}^2{(e^{-\lambda 10t})}^2+2\left(1-e^{-\lambda 4t}\right) {(e^{-\lambda 1t})}^2{(e^{-\lambda 2t})}^2{(e^{-\lambda 3t})}^2{(e^{-\lambda 5t})}^2{(e^{-\lambda 10t})}^2\\ +2\left(1-e^{-\lambda 5t}\right){(e^{-\lambda 1t})}^2{(e^{-\lambda 3t})}^2{(e^{-\lambda 4t})}^2{(e^{-\lambda 2t})}^2+\\ 2\left(1-e^{-\lambda 10t}\right){(e^{-\lambda 1t})}^2{(e^{-\lambda 3t})}^2{(e^{-\lambda 4t})}^2{(e^{-\lambda 2t})}^2{(e^{-\lambda 5t})}^2\end{array}$$

(9)

The fault in S₁/S₉ is represented by the second term. The equation’s third term reflects fault in S₂/S₈. The fourth term of the above equation reflects fault in S₃/S₇. Similarly, sixth seventh, and eighth terms represent a fault in S₄/S₆, S₅, and S₁₀/S₁₁ respectively. The reliability curve and its comparison with previous topologies are depicted in Figure 13 for 20 years. It is recognizable that the proposed topology has higher reliability than topologies introduced in [15,16,20,24,25,29].

Figure 13. Reliability comparison with previous literature.

5.4. Reliability Comparison with Recent Literature

The reliability equation of the topology is compared with some recent works as exhibited below. The proposed topology in [30] has the following reliability function:

$$R\left(t\right)={(e^{-\lambda bt})}^5{(e^{-\lambda dt})}^4+5\left(1-e^{-\lambda bt}\right){(e^{-\lambda bt})}^3{(e^{-\lambda dt})}^{4 }+4\left(1-e^{-\lambda bt}\right){(e^{-\lambda bt})}^5{(e^{-\lambda dt})}^3$$

(10)

The topology in [31] has the following reliability function:

$$R\left(t\right)={(e^{-\lambda bt})}^5{(e^{-\lambda dt})}^3+3\left(1-e^{-\lambda bt}\right){(e^{-\lambda bt})}^4{(e^{-\lambda dt})}^{3}2\left(1-e^{-\lambda dt}\right){(e^{-\lambda bt})}^5{(e^{-\lambda dt})}^2$$

(11)

The topology in [25] possesses the following reliability function:

$$R\left(t\right)={(e^{-\lambda ct})}^{12}{(e^{-\lambda dt})}^4+12\left(1-e^{-\lambda ct}\right){(e^{-\lambda ct})}^6{(e^{-\lambda dt})}^6$$

(12)

The reliability function of topology introduced in [32] is given as:

$$\begin{array}{c}R\left(t\right)={(e^{-\lambda bt})}^2{(e^{-\lambda ct})}^4{(e^{-\lambda dt})}^8+8\left(1-e^{-\lambda dt}\right){(e^{-\lambda bt})}^2{(e^{-\lambda ct})}^4{(e^{-\lambda dt})}^8+2\left(1-e^{-\lambda bt}\right){(e^{-\lambda ct})}^4{(e^{-\lambda dt})}^8\\ +4\left(1-e^{-\lambda ct}\right){(e^{-\lambda bt})}^2{(e^{-\lambda ct})}^2\end{array}$$

(13)

The topology mentioned in [33] has the reliability function:

$$R\left(t\right)={(e^{-\lambda bt})}^5{(e^{-\lambda dt})}^3+3\left(1-e^{-\lambda bt}\right){(e^{-\lambda bt})}^4{(e^{-\lambda dt})}^{2 }$$

(14)

where in the preceding equations, ${\lambda }_b=0.0011, {\lambda }_c=0.0016, {\lambda }_d=0.002$.

6. Comparative Analysis

The performance parameters of the topologies such as NPC, CHB, and FC topologies as well as topologies proposed in [15,16,20,24,25,29] are demonstrated in Table 4. Compared with the number of levels generated, the proposed topology requires a significantly competitive amount of dc sources. The requirement of any capacitors, transformers, or relays is also absent in the proposed topology. Moreover, the ratio of levels generated/IGBTs required is substantially higher than other topologies except [15], but [15] also requires relays and a center-tapped transformer for fault-tolerant operation. Furthermore, no redundant switch is required, which implies no switch remains unutilized during healthy operation implying full utilization of all switches.

7. Conclusions

This paper assesses a reduced device count 15-level asymmetrical multilevel inverter topology for fault-tolerant capabilities. Redundant states are employed to mitigate post-fault output distortion. The topology’s operational performance, including load power and output harmonic distortion, are examined under various failure modes through simulation results to demonstrate the fault-tolerant operation. Reliability function derivation and thermal analysis are performed and reliability curve and failure rate values are established according to predefined standards to indicate the improvement in reliability with fault-tolerance capability. A comparison with previously established fault-tolerance works has been presented to evaluate the performance of the topology for reliability-critical applications.