SEE Sensitivity Evaluation for Commercial 16 nm SRAM-FPGA

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser’s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.


Introduction
Given its high processing power and configuration flexibility, static random-access memory (SRAM)-based field-programmable gate array (FPGA) has become one of the most fascinating devices in astrionics [1][2][3]. However, particle-induced single event effects (SEE) in SRAM-FPGA have shown diversity and complexity in previous studies. This was because the basic SRAM architectures were sensitive to single event upset (SEU), single event latch-up (SEL), and single event functional interrupt (SEFI). The corruption of logic values like SEU, disturbance of the functionalities like SEFI, and the thermal damage of circuits like SEL have different effects on the FPGA [1][2][3]. Though SEU is not so destructive as SEL, the occurrence of upset errors in FPGA configure RAMs (CRAMs) may change the internal states of the circuits. This may propagate to the primary outputs of circuits and produce bit errors, or even cause system failures [3][4][5][6][7]. Thus, some typical radiation-hardened FPGAs have been designed and widely employed in space missions [3,[6][7][8]. However, the rapid advances The Xilinx KCU116 evaluation platform with Kintex UltraScale + FPGA (xcku5p-ffvb676-2-e) was used as the DUT to characterize the SEE sensitivities in FinFET ultra large-scale integrated circuits (ULSI). The Verilog hardware description languages were employed to achieve the memory test and functional test. During each trial, all the CRAM in the xcku5p FPGA were measured, and the I/O currents, SEU, and SEFI signals were detected timely.
In case the SEL induced failures, the input/output (I/O) currents were detected by a real-time monitoring software (MaximDigitalPower) matched to the Xilinx Ultrascale + evaluation board (as shown in Figure 1). Since the SEL may induce destructive thermal damages in DUT, more than triple of the initial current values were regarded as the SEL phenomenon. The SEL can be detected using the software, and then the power will be cut-off automatically in case the current surges. Owing to the power-off procedure, the SEL could also result in the removal of the configured bitstream in the DUT, rendering the SEU and SEFI tests invalid.
Electronics 2020, 9, x FOR PEER REVIEW 3 of 12 employed to realize an effective evaluation by checking the read and write function of the implemented IPs in the FPGA. This test was a representative example to evaluate the SEFI rate and its influence on the FinFET FPGA. As shown in Table 1, though the BRAM, LUT, I/O resources utilized are below 40%, a lot of logic and clock resources are included in the functional test. The currents and power consumption for the functional test were not very low due to the embedded Microblaze IP. Higher resource occupation may lead to over-temperature, low efficiency of the JTAG interface, and resulting difficulty in fault analysis, which is not easy for the SEE evaluation.   The memory test is mainly aimed to examine the SEU response of the CRAM and BRAM cells in the FPGA. The resource utilization for the memory test is shown in Table 1. The basic structure and the data depth for each BRAM module are shown in Figure 2a. We utilized 100% BRAM by four 16-bit width RAM modules. Few flip-flop (FF) and look-up tables (LUT) were occupied in the implemented project, as shown in Table 1. The bitstreams (bit) together with readback (rbd), mask (msd), and logical location (ll) files were generated by the Vivado software and then uploaded to the computer by the Joint Test Action Group (JTAG) interface. The original bitstream was chosen as a golden file. Meanwhile, the readback bitstreams, operated based on the Tool Command Language (TCL) in Vivado, could be generated dynamically and uploaded to a computer to distinguish the upset data. In addition, the C ++ based visual interface was designed to achieve the comparative procedure between the golden file and the readback bitstreams. Then the error information was distinguished, classified, and calculated based on the type of resources. interface, and resulting difficulty in fault analysis, which is not easy for the SEE evaluation.

Pulsed Laser Testing System
As shown in Figure 3a, a pulsed laser irradiation platform was employed to evaluate the SEE sensitivity for the DUT. The detailed parameters of the laser for the irradiation test are shown in Table  2. The DUT was placed in a three-dimensional mobile platform that could give the DUT positional parameters directly to realize accurate and stable movement during the test. The high-energy pulsed laser with a 1064 nm center wavelength and 25 ps pulse width was chosen as the radiation source. The backside irradiation with 5 µm spot size was selected, leading the incident photons passing to the active regions directly without considering the high-density metal layers. The lens should move a ▽d towards the DUT to direct the laser focused onto the active areas of the DUT. The value of ∆d can be calculated from the formula where η(Si) is the refractive index of silicon, and Tsub is the thickness of the silicon substrate. Moreover, the optical polarization and attenuation module are also required. An energy controlling system with an operational software was applied to control the initial energy (Einitial) changing from ~85 pJ to ~11.6 nJ, while the effective energy in the substrate regions (Eeff−sub) of DUT is given by where ϵ1 and ϵ2 represent the refractive index for air and silicon, respectively. For the memory test, a wide range of laser energies were used, while only inferior laser energies were applicable to the functional test.  For the functional test, the embedded Microblaze soft (Intellectual Property) IP core was implemented in the DUT. This was done to control the external double data rate (DDR4) synchronous dynamic RAM (SDRAM) using an integrated memory interface generators (MIG) IP. The schematic for the block design is shown in Figure 2b, and the analytical methods for this test are the same as that in the memory test. The peripheral DDR4 SDRAM in the KCU116 evaluation platform was employed to realize an effective evaluation by checking the read and write function of the implemented IPs in the FPGA. This test was a representative example to evaluate the SEFI rate and its influence on the FinFET FPGA. As shown in Table 1, though the BRAM, LUT, I/O resources utilized are below 40%, a lot of logic and clock resources are included in the functional test. The currents and power consumption for the functional test were not very low due to the embedded Microblaze IP. Higher resource occupation may lead to over-temperature, low efficiency of the JTAG interface, and resulting difficulty in fault analysis, which is not easy for the SEE evaluation.

Pulsed Laser Testing System
As shown in Figure 3a, a pulsed laser irradiation platform was employed to evaluate the SEE sensitivity for the DUT. The detailed parameters of the laser for the irradiation test are shown in Table 2. The DUT was placed in a three-dimensional mobile platform that could give the DUT positional parameters directly to realize accurate and stable movement during the test. The high-energy pulsed laser with a 1064 nm center wavelength and 25 ps pulse width was chosen as the radiation source. The backside irradiation with 5 µm spot size was selected, leading the incident photons passing to the active regions directly without considering the high-density metal layers. The lens should move a d towards the DUT to direct the laser focused onto the active areas of the DUT. The value of ∆d can be calculated from the formula where η(Si) is the refractive index of silicon, and T sub is the thickness of the silicon substrate. Moreover, the optical polarization and attenuation module are also required. An energy controlling system with an operational software was applied to control the initial energy (E initial ) changing from~85 pJ to~11.6 nJ, while the effective energy in the substrate regions (E eff−sub ) of DUT is given by The heavy-ion tests were carried out at the Heavy Ion Research Facility in Lanzhou (HIRFL) at the Institute of Modern Physics, Chinese Academy of Sciences. As shown in Figure 3b, at the HIRFL, the test board was located in the air at the end of the terminal, and a laser beamline could be applied to calibrate the position of the DUT. The area of the beamline was 2.30 cm × 2.3 cm, which could realize a fully covered irradiation. The parameters of the LET values and ranges for 181 Ta ions are shown in Figure 4. During the irradiation, high energy 181 Ta ions were used with the initial linear energy transfer (LET) value at 80.5 MeV·cm 2 ·mg −1 . Considering that the DUT is a flip-chip device with ~490 µm silicon on the top of the die, the silicon substrate was thinned down to 60 µm. This was less than the range of incident ions (~99.3 µm in air/~89.0 µm in DUT surface). Furthermore, the flux of incident ions was controlled in ~3 to ~10 ions·cm −2 ·s −1 in case the current surged.

Heavy Ion Irradiation
The heavy-ion tests were carried out at the Heavy Ion Research Facility in Lanzhou (HIRFL) at the Institute of Modern Physics, Chinese Academy of Sciences. As shown in Figure 3b, at the HIRFL, the test board was located in the air at the end of the terminal, and a laser beamline could be applied to calibrate the position of the DUT. The area of the beamline was 2.30 cm × 2.3 cm, which could realize a fully covered irradiation. The parameters of the LET values and ranges for 181 Ta ions are shown in Figure 4. During the irradiation, high energy 181 Ta ions were used with the initial linear energy transfer (LET) value at 80.5 MeV·cm 2 ·mg −1 . Considering that the DUT is a flip-chip device with~490 µm silicon on the top of the die, the silicon substrate was thinned down to 60 µm. This was less than the range of incident ions (~99.3 µm in air/~89.0 µm in DUT surface). Furthermore, the flux of incident ions was controlled in~3 to~10 ions·cm −2 ·s −1 in case the current surged.

Pulsed Laser Results
The voltage variations in multiple channels are shown in Figure 5a, and the detailed changes of voltages and currents in a single port are shown in Figure 5b. The voltages and I/O currents were basically stable when the energy of the pulsed laser was below 11.6 nJ.
basically stable when the energy of the pulsed laser was below 11.6 nJ.
In the memory test, the full-1 data were written in the BRAM module. The obvious threshold feature was characterized. The SEU threshold for both BRAM and CRAM was 3.5 nJ, though the upset rate for the two was quite different. We found that in this test, the SEFI threshold was 10.2 nJ, and the SEL threshold was11.6 nJ. The laser-induced upset rates (per device) are given by where A is the area of the DUT. The Nupset indicates the total upset bits. T is the nature period of the pulsed laser, and t is the scanning time. The detailed upset results are shown in Figure 6. Compared to the upsets in the BRAM, the upsets in CRAM showed a very low cross-section when the laser energy was below 7.8 nJ. However, high energy (10.2 nJ) will induce a large number of upsets in the CRAM and even dominate the total upsets in the FPGA. Meanwhile, the upsets for the BRAM are roughly the same as that in 7.8 nJ. The successive errors that occurred in adjacent lines or rows of bitstream were regarded as a burst error. As shown in Figure 7, 2-to 4-bit errors were observed in 7.8 nJ or higher energy laser irradiation. More than five bits or burst errors only frequently appeared in 10.2 nJ, which corresponded to the surging of cross-sections in Figure 6 in 10.2 nJ. Besides, no hard error (nonrecoverable by reconfiguration) in the memory cell was observed even when the energy of the laser was increased to ~11.6 nJ. However, when the energy of the laser was >11.6 nJ, the DUT could be damaged by the SEL with an obvious temperature surge in merely 3-5 s. After that, the DUT could not be detected by the hardware manager in Vivado. All the reconfiguration procedures for the thermal damaged DUTs failed.
In the functional test, if the SEU threshold (3.5 nJ) was satisfied (as shown in Table 3), the write/read functions for the DDR4 controller would be invalid. This indicated that the SEFI threshold had declined to 3.5 nJ. Though the reconfiguration operation can recover the write/read controller, it is time-consuming. The results for the functional test corresponded to the upsets in the CRAM, indicating that the upset for an essential bit in the CRAM would induce system-level failure. Thus, the upset threshold for the CRAM is a crucial parameter for the SEE sensitivity evaluation of the FPGA.  In the memory test, the full-1 data were written in the BRAM module. The obvious threshold feature was characterized. The SEU threshold for both BRAM and CRAM was 3.5 nJ, though the upset rate for the two was quite different. We found that in this test, the SEFI threshold was 10.2 nJ, and the SEL threshold was 11.6 nJ. The laser-induced upset rates (per device) are given by where A is the area of the DUT. The N upset indicates the total upset bits. T is the nature period of the pulsed laser, and t is the scanning time. The detailed upset results are shown in Figure 6. Compared to the upsets in the BRAM, the upsets in CRAM showed a very low cross-section when the laser energy was below 7.8 nJ. However, high energy (10.2 nJ) will induce a large number of upsets in the CRAM and even dominate the total upsets in the FPGA. Meanwhile, the upsets for the BRAM are roughly the same as that in 7.8 nJ. The successive errors that occurred in adjacent lines or rows of bitstream were regarded as a burst error. As shown in Figure 7, 2-to 4-bit errors were observed in 7.8 nJ or higher energy laser irradiation. More than five bits or burst errors only frequently appeared in 10.2 nJ, which corresponded to the surging of cross-sections in Figure 6 in 10.2 nJ. Besides, no hard error (nonrecoverable by reconfiguration) in the memory cell was observed even when the energy of the laser was increased to~11.6 nJ. However, when the energy of the laser was >11.6 nJ, the DUT could be damaged by the SEL with an obvious temperature surge in merely 3-5 s. After that, the DUT could not be detected by the hardware manager in Vivado. All the reconfiguration procedures for the thermal damaged DUTs failed.
Electronics 2020, 9, x FOR PEER REVIEW 7 of 12       In the functional test, if the SEU threshold (3.5 nJ) was satisfied (as shown in Table 3), the write/read functions for the DDR4 controller would be invalid. This indicated that the SEFI threshold had declined to 3.5 nJ. Though the reconfiguration operation can recover the write/read controller, it is time-consuming. The results for the functional test corresponded to the upsets in the CRAM, indicating that the upset for an essential bit in the CRAM would induce system-level failure. Thus, the upset threshold for the CRAM is a crucial parameter for the SEE sensitivity evaluation of the FPGA.

Heavy Ion Results
The bitstream for the memory test was used in heavy-ion irradiation and the results are shown in Table 4. The~900 ions/cm 2 frequency of current surging (SEL) phenomena were measured. Two kinds of SEFI were observed, including the loss of link for the JTAG interface (~3.6 × 10 −2 cm 2 /device) and the burst errors (~1.6 × 10 −3 cm 2 /device) induced by the upset of the global registers. The cross-section results for the clock induced errors were~10 −3 cm 2 /bit, while more than 2-million-bit upsets were detected after a clock error. Both the loss of link and the burst errors appeared in a high frequency, which may affect the capture of SEU in the irradiation test. Thus, in the SEU measurement, the very low fluence was used to guarantee the stable readback of the DUT. Apart from the high SEFI frequency, the multi-bit upsets were observed in the heavy-ion test ( Figure 8). The proportions of 2-bit errors, 3-bit errors, and burst errors were not very small. The influence of the burst errors would be another essential issue that needs to be solved before application in a radiation environment. Besides, the observed 2-5-bit upsets indicated that the high-LET 181 Ta induced charge sharing phenomenon in bulk FinFET circuits may also exist. This result should be considered when designing the radiation hardness techniques.
Electronics 2020, 9, x FOR PEER REVIEW 8 of 12 frequency, which may affect the capture of SEU in the irradiation test. Thus, in the SEU measurement, the very low fluence was used to guarantee the stable readback of the DUT. Apart from the high SEFI frequency, the multi-bit upsets were observed in the heavy-ion test ( Figure 8). The proportions of 2-bit errors, 3-bit errors, and burst errors were not very small. The influence of the burst errors would be another essential issue that needs to be solved before application in a radiation environment. Besides, the observed 2-5-bit upsets indicated that the high-LET 181 Ta induced charge sharing phenomenon in bulk FinFET circuits may also exist. This result should be considered when designing the radiation hardness techniques.

Analysis of the Radiation Sensitivity
SEL is a severe concern that can cause unpredictable faults by forming a positive feedback loop in parasitic PNPN structures. This outcome can persist until either the power is removed or thermal damage occurs [12]. As shown in Figure 9, radiation-induced carriers activate the PNPN structure and result in a sharp current surge. The SEL phenomenon in the DUT frequently occurs in both heavy-ion and high energy laser irradiation. The~1.1 × 10 −3 cm 2 /device SEL cross-section was very high when compared to the SEL cross-sections for the hardened FPGAs [6][7][8]13]. Besides, both the thermal damage and the power-off in the DUT induced by the SEL phenomenon could render the evaluation of SEFI and SEU invalid. Thus, the protection of the SEL is vital in the irradiation test and the further hardened design of the SEL is also necessary for space applications.
The upset cross-sectional results for the BRAM were similar to the evaluation of the SRAM at the same FinFET technology. The cross-sectional results were related to the actual sensitive regions of the devices. For the FinFET devices, the upset rates mainly referred to the transistor's fin area and the details of the process technology [14]. The drift and diffusion of the carriers under the electric field and the parasitic bipolar effects should also be considered. If enough charges were collected in the sensitive regions, the upsets would be produced. However, the ~2.1 × 10 −9 cm 2 /bit SEU crosssection is not high and it is even lower than the basic BRAM cross sections for the 90 nm and 65 nm FPGA (~10 −8 cm 2 /bit to ~10 −7 cm 2 /bit). Since the sensitive region for the FinFET transistors is reduced, superior cross-sectional results of the SEU are mainly due to the increase in total bits in the Ultrascale + FPGA. Moreover, the SEU in the BRAM is not very severe for the function of the FPGA. It can be mitigated by triple modular redundancy (TMR) and error detection and correction (EDAC) codes [3].
The characterization of SEFI is difficult. As shown in Figure 10, errors in the logic of the communication interface (CI), in the clock or other global registers, or in some essential switches, (CRAM) will lead to SEFI occurrence. The majority of SEFI was caused by errors in the CI and global buffers, resulting in burst errors appearing in the bitstream. However, upsets in some CRAMs may also have had significant influence and are closely associated with SEFI. Meanwhile, the expression of these upsets in bitstreams is usually a single bit error. The ~10 −3 cm 2 /bit to ~10 −2 cm 2 /bit SEFI crosssection results for the DUT were more severe than the other FPGAs with large feature size, which should be concerning for its influence in a radiation environment [6][7][8]13,15,16].
For the SEUs in CRAM, single-bit errors and multiple bit errors were distinguished. As shown in Figure 11, the multiple bit errors usually existed in the LUT and switch array due to their adjacent sensitive nodes. The swift 181 Ta ions produced high-density electron-hole pairs, and the severe charge sharing phenomenon widely existed in the bulk process. Thus, we observed the maximal 5-bit errors in the same or contiguous word line and contiguous bit lines. Attention should be paid to this in the hardening design. Similar results for the multi-bit upsets were also discovered in the 28 nm Kintex-7 FPGA, though the LET values used in the irradiation test were not high [16]. The upset cross-sectional results for the BRAM were similar to the evaluation of the SRAM at the same FinFET technology. The cross-sectional results were related to the actual sensitive regions of the devices. For the FinFET devices, the upset rates mainly referred to the transistor's fin area and the details of the process technology [14]. The drift and diffusion of the carriers under the electric field and the parasitic bipolar effects should also be considered. If enough charges were collected in the sensitive regions, the upsets would be produced. However, the~2.1 × 10 −9 cm 2 /bit SEU cross-section is not high and it is even lower than the basic BRAM cross sections for the 90 nm and 65 nm FPGA (~10 −8 cm 2 /bit to~10 −7 cm 2 /bit). Since the sensitive region for the FinFET transistors is reduced, superior cross-sectional results of the SEU are mainly due to the increase in total bits in the Ultrascale + FPGA. Moreover, the SEU in the BRAM is not very severe for the function of the FPGA. It can be mitigated by triple modular redundancy (TMR) and error detection and correction (EDAC) codes [3].
The characterization of SEFI is difficult. As shown in Figure 10, errors in the logic of the communication interface (CI), in the clock or other global registers, or in some essential switches, (CRAM) will lead to SEFI occurrence. The majority of SEFI was caused by errors in the CI and global buffers, resulting in burst errors appearing in the bitstream. However, upsets in some CRAMs may also have had significant influence and are closely associated with SEFI. Meanwhile, the expression of these upsets in bitstreams is usually a single bit error. The~10 −3 cm 2 /bit to~10 −2 cm 2 /bit SEFI cross-section results for the DUT were more severe than the other FPGAs with large feature size, which should be concerning for its influence in a radiation environment [6][7][8]13,15,16].
The upset cross-sectional results for the BRAM were similar to the evaluation of the SRAM at the same FinFET technology. The cross-sectional results were related to the actual sensitive regions of the devices. For the FinFET devices, the upset rates mainly referred to the transistor's fin area and the details of the process technology [14]. The drift and diffusion of the carriers under the electric field and the parasitic bipolar effects should also be considered. If enough charges were collected in the sensitive regions, the upsets would be produced. However, the ~2.1 × 10 −9 cm 2 /bit SEU crosssection is not high and it is even lower than the basic BRAM cross sections for the 90 nm and 65 nm FPGA (~10 −8 cm 2 /bit to ~10 −7 cm 2 /bit). Since the sensitive region for the FinFET transistors is reduced, superior cross-sectional results of the SEU are mainly due to the increase in total bits in the Ultrascale + FPGA. Moreover, the SEU in the BRAM is not very severe for the function of the FPGA. It can be mitigated by triple modular redundancy (TMR) and error detection and correction (EDAC) codes [3].
The characterization of SEFI is difficult. As shown in Figure 10, errors in the logic of the communication interface (CI), in the clock or other global registers, or in some essential switches, (CRAM) will lead to SEFI occurrence. The majority of SEFI was caused by errors in the CI and global buffers, resulting in burst errors appearing in the bitstream. However, upsets in some CRAMs may also have had significant influence and are closely associated with SEFI. Meanwhile, the expression of these upsets in bitstreams is usually a single bit error. The ~10 −3 cm 2 /bit to ~10 −2 cm 2 /bit SEFI crosssection results for the DUT were more severe than the other FPGAs with large feature size, which should be concerning for its influence in a radiation environment [6][7][8]13,15,16].
For the SEUs in CRAM, single-bit errors and multiple bit errors were distinguished. As shown in Figure 11, the multiple bit errors usually existed in the LUT and switch array due to their adjacent sensitive nodes. The swift 181 Ta ions produced high-density electron-hole pairs, and the severe charge sharing phenomenon widely existed in the bulk process. Thus, we observed the maximal 5-bit errors in the same or contiguous word line and contiguous bit lines. Attention should be paid to this in the hardening design. Similar results for the multi-bit upsets were also discovered in the 28 nm Kintex-7 FPGA, though the LET values used in the irradiation test were not high [16].  For the SEUs in CRAM, single-bit errors and multiple bit errors were distinguished. As shown in Figure 11, the multiple bit errors usually existed in the LUT and switch array due to their adjacent sensitive nodes. The swift 181 Ta ions produced high-density electron-hole pairs, and the severe charge sharing phenomenon widely existed in the bulk process. Thus, we observed the maximal 5-bit errors in the same or contiguous word line and contiguous bit lines. Attention should be paid to this in the hardening design. Similar results for the multi-bit upsets were also discovered in the 28 nm Kintex-7 FPGA, though the LET values used in the irradiation test were not high [16].
Electronics 2020, 9, x FOR PEER REVIEW 10 of 12 Figure 11. Types of single-bit and multi-bit upset for the CRAM.

Influences and Strategies
Based on the heavy-ion and pulsed laser results, the basic radiation sensitivity for the Xilinx UltraScale+ FPGA was evident. Thus, we provide some conclusions and suggestions regarding SEE sensitivity and hardening strategies, which may be very useful for both FPGA users and IC designers. As for the users, they can employ some necessary hardening strategies to satisfy the criteria of space applications and maximize their advantages on performance. However, considering the SEE sensitivity of the DUT, if necessary, the advanced radiation-hardened FPGA with Ultrascale+ architecture may also have irreplaceable contributions. This is especially useful for the extreme radiation environment. Meanwhile, the basic physical design can reduce the SEE sensitivity to a great extent [3,[6][7][8], which cannot be entirely replaced by the usage of redundant routing connections.
In radiation environments, the ion-induced SEL cannot be neglected because of its highfrequency occurrence and the destructive effects. Thus, current monitoring and automatic power-off are required. For future radiation-hardened FPGA in this technology, physical hardness techniques such as guard rings or guard strips seem useful to reduce the risk of intra-device interactions by providing spatial and electrical isolation and keeping the wells pinned to the appropriate potential [12]. The SEFI phenomenon is also common and hard to be fully eliminated in the widely used interface and global resources. Hence, dynamic monitoring and reconfiguration should be considered for commercial devices. Besides, for IC designers, the double interlocked storage cells (DICEs) are preferable for use to replace the standard cells in SEFI sensitive ports [1,11,[17][18][19]. Though the full hardened structures are area and power-consuming [3], the cross-section results for SEFI can be effectively controlled at ~10 −7 cm 2 /bit in the 90 nm bulk process [6,7]. For the SEU, multiple types of protections for the bit-level or module level can be inserted by FPGA users, such as the full TMR and EDAC codes. It means that some actions can be taken during the placement and routing implementation like the usage of redundant routing connections [1,20] or soft error tolerance place and route algorithms to achieve the physical separation or sensitive cell redundancy [21]. However, the adjacent ~5-bit upsets in the bitstream were measured in high-LET heavy ion irradiation, indicating some long-distance separation of the sensitive nodes. This can be achieved either by FPGA designers or FPGA users, especially for the essential information.

Development of the SEE Evaluation Method
The majority of the SEE evaluations for the FPGA are based on the unique design testing systems [3,[6][7][8]. Both the software and hardware implementation were completed before the irradiation test. Some flexible testing methods were proposed and realized such as the pin connected motherboarddaughterboard structure with a reused motherboard to satisfy the cost reduction strategy. However, the design of the software and the communication interface are still time-consuming [13]. Thus, the SEE evaluation based on the FPGA evaluation platform has advantages in time and cost. The related test logics were created in the Kintex-7 evaluation platform in previous work [15,16]. These logics

Influences and Strategies
Based on the heavy-ion and pulsed laser results, the basic radiation sensitivity for the Xilinx UltraScale+ FPGA was evident. Thus, we provide some conclusions and suggestions regarding SEE sensitivity and hardening strategies, which may be very useful for both FPGA users and IC designers. As for the users, they can employ some necessary hardening strategies to satisfy the criteria of space applications and maximize their advantages on performance. However, considering the SEE sensitivity of the DUT, if necessary, the advanced radiation-hardened FPGA with Ultrascale+ architecture may also have irreplaceable contributions. This is especially useful for the extreme radiation environment. Meanwhile, the basic physical design can reduce the SEE sensitivity to a great extent [3,[6][7][8], which cannot be entirely replaced by the usage of redundant routing connections.
In radiation environments, the ion-induced SEL cannot be neglected because of its high-frequency occurrence and the destructive effects. Thus, current monitoring and automatic power-off are required. For future radiation-hardened FPGA in this technology, physical hardness techniques such as guard rings or guard strips seem useful to reduce the risk of intra-device interactions by providing spatial and electrical isolation and keeping the wells pinned to the appropriate potential [12]. The SEFI phenomenon is also common and hard to be fully eliminated in the widely used interface and global resources. Hence, dynamic monitoring and reconfiguration should be considered for commercial devices. Besides, for IC designers, the double interlocked storage cells (DICEs) are preferable for use to replace the standard cells in SEFI sensitive ports [1,11,[17][18][19]. Though the full hardened structures are area and power-consuming [3], the cross-section results for SEFI can be effectively controlled at 10 −7 cm 2 /bit in the 90 nm bulk process [6,7]. For the SEU, multiple types of protections for the bit-level or module level can be inserted by FPGA users, such as the full TMR and EDAC codes. It means that some actions can be taken during the placement and routing implementation like the usage of redundant routing connections [1,20] or soft error tolerance place and route algorithms to achieve the physical separation or sensitive cell redundancy [21]. However, the adjacent~5-bit upsets in the bitstream were measured in high-LET heavy ion irradiation, indicating some long-distance separation of the sensitive nodes. This can be achieved either by FPGA designers or FPGA users, especially for the essential information.

Development of the SEE Evaluation Method
The majority of the SEE evaluations for the FPGA are based on the unique design testing systems [3,[6][7][8]. Both the software and hardware implementation were completed before the irradiation test. Some flexible testing methods were proposed and realized such as the pin connected motherboard-daughterboard structure with a reused motherboard to satisfy the cost reduction strategy. However, the design of the software and the communication interface are still time-consuming [13]. Thus, the SEE evaluation based on the FPGA evaluation platform has advantages in time and cost. The related test logics were created in the Kintex-7 evaluation platform in previous work [15,16]. These logics allows multiple design instances to be flexibly tested in parallel, increasing the rate of data acquisition in the radiation test [15,16]. However, the functional test with the rational use of peripheral DDR4 SDRAM in the evaluation platform is closer to the actual application than the single logic test. This is beneficial to the SEE sensitivity characterization of the FPGA. In the future, for high-density and complex FPGA systems, the SEE evaluation with the help of peripheral devices may become a valuable method. Furthermore, some additional classical projects with high resource utilization under tight timing constraints are also required in our future research. This includes the influence of single event transients in these projects that may show much more complex influences in irradiation tests. As for the projects with high resource utilization, the testing methods should not be limited by the given interfaces in the FPGA evaluation platform. The uniquely designed built-in self-test circuits in the DUT also have advantages in characterizing the SEE features.

Conclusions
The SEE sensitivity for the commercial 16 nm FinFET FPGA was fully evaluated by heavy-ion and laser irradiation. The measured results for the SEL, SEFI, and SEU in the CRAM were essential parameters for the FinFET ULSI. The SEE mitigation strategies for both IC designers and users were also provided based on the SEE testing results. The evaluation results will be very useful for the application of high-density FinFET devices in space or high energy physics environments. For the future application of FinFET-based ULSI, apart from the destructive SEL that needs to be fully prevented. FPGA users should consider the proper trade-off strategies for both performance and radiation tolerance.