Abstract
In this paper, two light-load efficiency improvement methods are presented and applied to the ultrahigh step-down converter. The two methods are both based on skip mode control. Skip Mode 1 only needs one half-bridge driver integrated circuit (IC) to drive three switches, so it has the advantages of easy signal control and lower cost, whereas Skip Mode 2 requires one half-bridge driver integrated circuit IC, one common ground driver IC, and three independent timing pulse-width-modulated (PWM) signals to control three switches, so the cost is higher and the control signals are more complicated, but Skip Mode 2 can obtain slightly higher light-load efficiency than Skip Mode 1. Although the switching frequency used in these methods are reduced, the transferred energy is unchanged, but the output voltage ripple is influenced to some extent.
1. Introduction
1.1. Motivation and Incitement
Nowadays, the 48 V direct bus (DC) bus is very popular in the telecom system and networking communication equipment. The front-end AC-DC converter generates a stable 48 V DC bus from the alternating current (AC) grid. The traditional two-stage step-down converter architecture generates a low output voltage (usually under 3.3 V) from 48 V to feed the digital circuit. The 48 V DC bus is first stepped down by the first-stage converter to the 12 V DC bus to supply the power on load (POL) converter, and then the POL converter creates a low voltage to the load. Two-stage DC-DC converter requires a relatively large component count and provides relatively low efficiency.
1.2. Literature Review
The methods proposed in [1,2,3,4] use a two-stage buck converter to obtain a high step-down voltage gain, but the methods used in [1,2,3,4] require a lot of active switches, passive components, and driving circuits. The method mentioned in [5] is to use a first-order high-efficiency open-loop bus converter, which converts from a 48 V DC high voltage to a 12 V DC intermediate bus, and then generates low voltage from the POL to supply the load. In addition, the bus converter requires four active switches and two magnetic elements. If the second-stage buck converter is added, six switches and three magnetic elements are required, and a separate control integrated circuit (IC) is required. The methods proposed in [6,7,8,9,10,11] need to use multiple sets of switching regulators in parallel and to adopt interlaced pulse-width-modulated (PWM) signals to improve the conversion ratio of input and output. Compared with the traditional buck converter, under the same input and output voltage conditions, these converters can operate in a larger duty cycle and the corresponding switching loss can be reduced. In addition, this kind of architectures requires interleaved operation with at least two phases, which is more suitable for high output current applications.
The methods proposed in [7,12,13,14,15,16,17,18,19] use coupled inductors to achieve high step-down ratio output. These circuits are relatively simple, but there will be leakage inductances to generate high voltage spikes on the switches. To reduce the breakdown risk from high voltage spikes, passive snubbers must be used to absorb and suppress the leakage energy of the winding, making the efficiency lower. Although the authors of [19] proposed that active snubbers can recover the leakage energy of the windings, these circuits are quite complicated. In the schemes in [6,13], there are many switching elements and magnetic elements, making the circuits too complicated and the corresponding cost high, and they are not suitable for low and medium power applications.
1.3. Contribution and Paper Organization
The above research results have many limitations and shortcomings in practical applications, so the authors of [20,21] proposed a new high step-down converter, which, compared with the traditional buck converter, has the following three advantages: (i) the use of a single coupled inductor only requires the addition of an active switch with common ground and a small-capacity capacitor, and this switch can be driven by an existing buck control IC; (ii) the voltage gain of this circuit does not contain nonlinear components, and hence the control is simple; and (iii) although the circuit shown in [20,21] has high efficiency at rated load, this circuit has the problem of lower efficiency at light load.
Therefore, based on the circuit structure in [20,21], this paper presents two skip mode control methods to improve the light-load efficiency. Although the switching frequency used in these methods are reduced, the transferred energy is unchanged, but the output ripple is affected to some extent. In addition, the mode exchange is very smooth. The rest of this paper is organized as follows. Section 2 briefly describes the used circuit. Section 3 elaborates on basic circuit operating principles, containing Normal Mode, Skip Mode 1, and Skip Mode 2. Section 4 gives some experimental results to verify that the light-load efficiency can be improved based on the proposed PWM control strategies. Section 5 gives some discussions. Some conclusions are drawn in Section 6.
2. Used Circuit
Figure 1 shows the circuit used herein, which contains three active switches Q1, Q2, and Q3; capacitors CB and Co; one coupled inductor L with two windings N1 and N2; one magnetizing inductance Lm; and two leakage inductances LLK1 and LLK2. In addition, Q2 and Q3, with both gates of Q2 and Q3 connected together, are driven synchronously. Accordingly, only one half-bridge driver is needed to drive three active switches. In addition, this circuit is always operated in the continuous current mode (CCM), and the illustrated waveforms shown in Figure 2a–c are for Normal Mode, Skip Mode 1, and Skip Mode 2, respectively.
Figure 1.
Circuit architecture in [20,21].
Figure 2.
(a) Illustrated waveforms of Normal Mode; (b) Illustrated waveforms of Skip Mode 1; (c) Illustrated waveforms of Skip Mode 2.
3. Basic Circuit Operating Principles
There are six operating states in this circuit, which are described with reference to Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8. In all figures utilized to describe basic circuit operating behavior, orange is used to define the original current direction, whereas blue is used to indicate actual current direction.
Figure 3.
Current path in State 1 under Normal Mode.
Figure 4.
Current path in State 2 under Normal Mode.
Figure 5.
Current path in State 3 under Normal Mode.
Figure 6.
Current path in State 4 under Normal Mode.
Figure 7.
Current path in State 5 under Normal Mode.
Figure 8.
Current path in State 6 under Normal Mode.
3.1. Normal Mode
3.1.1. State 1
As shown in t0–t1 of Figure 3, Q1 is turned on, but Q2 and Q3 are turned off. The input voltage Vin charges the capacitor CB and magnetizes the magnetizing inductor Lm. Both the currents iN1 and iN2 are equal and increasing. During this stage, the input voltage Vin transmits energy to the output voltage Vo.
3.1.2. State 2
As shown in t1–t2 of Figure 4, Q1 is turned-off, and Q2 and Q3 remain off. This is the deadtime interval, and the currents iN1 and iN2 continue due to the leakage inductances LK1 and LK2. The currents iN1 and iN2 flow through the body diodes of Q2 and Q3.
3.1.3. State 3
As shown in t2–t3 of Figure 5, Q1 remains off, but Q2 and Q3 are turned on. The currents iN1 and iN2 flow through body diodes of Q2 and Q3. At this instant, Q2 and Q3 are turned on with zero voltage switching (ZVS). As the current iN1 finally drops to zero, the circuit enters the next state.
3.1.4. State 4
As shown in t3–t4 of Figure 6, Q1 remains off, and Q2 and Q3 remain on. During this stage, the energy stored in CB will magnetize the winding N1 in the opposite direction and transfer the energy to the winding N2 and then to the output terminal in the transformer mode, so the currents iN1 and iN2 increase.
3.1.5. State 5
As shown in t4–t5 of Figure 7, Q1, Q2, and Q3 are turned off. During this stage, the free-wheeling current in the leakage inductance LLK1 of the winding N1 will flow through the body diode of Q1, so the voltage vds1 reduces to zero. LLK1 is demagnetized continuously, and the energy stored in LLK1 is returned to the input voltage Vin and gradually decreases. During this interval, iN1 < iN2. Since Q3 is turned off, there is still excess current flowing through the body diode of Q3. As iN1 rises to zero, it enters State 6.
3.1.6. State 6
As shown in t5–t0 of Figure 8, Q1 is turned on, but Q2 and Q3 are still kept turned-off. Since the voltage vds1 is zero in State 5, if Q1 is turned on during this state, then Q1 has ZVS turned on. In addition, due to the leakage inductance and iN1 being smaller than iN2, there is still excess current flowing through Q3, but Q3 has been turned off, so the body diode of Q3 is forced to conduct. As iN1 = iN2, the current no longer flows through the body diode of Q3 and it returns to State 1.
3.2. Skip Mode 1
When this circuit is in Skip Mode 1 at light-load operation, there are nine operating states, which are described in Figure 9a–e. Among them, the behavior of t0–t5 is the same as Normal Mode, so only the actions of t5–t0 are described.
Figure 9.
Current path in different state under Skip Mode 1: (a) State 1; (b) State 2; (c) State 3; (d) State 4; (e) State 5.
3.2.1. State 6
As shown in t5–t6 of Figure 10, after the demagnetizing of LLK1 in State 5 is completed, Q1, Q2, and Q3 are all turned off at this time, but iLk1 and iLk2 continue to flow through the windings N1 and N2, so there is still current flowing through the body diode of Q3.
Figure 10.
Current path in State 6 under Skip Mode 1.
3.2.2. State 7
As shown in t6–t7 of Figure 11, at this time Q2 and Q3 are turned on for the second time, the capacitor CB magnetizes Lm, causing iLm to rise, and at the same time CB is discharged to the output through the N1 and N2, which are under the transformer mode.
Figure 11.
Current path in State 7 under Skip Mode 1.
3.2.3. State 8
As shown in t7–t8 of Figure 12, Q2 and Q3 are turned-off for the second time, so iLK1 flows through the body diode of Q1, making vds1 zero. Hence, Q3 is turned on with ZVS.
Figure 12.
Current path in State 8 under Skip Mode 1.
3.2.4. State 9
As shown in t8–t0 of Figure 13, when vds1 is zero, Q1 is turned on, and Q1 can be turned on with ZVS.
Figure 13.
Current path in State 9 under Skip Mode 1.
3.3. Skip Mode 2
When this circuit is in Skip Mode 2 at light-load operation, there are nine operation states, which are described in Figure 14a–d. Among them, the behavior of t0–t4 is the same as Skip Mode 1, so only the actions of t4–t0 are described.
Figure 14.
Current path in different state under Skip Mode 2: (a) State 1; (b) State 2; (c) State 3; (d) State 4.
3.3.1. State 5
As shown in t4–t5 of Figure 15, Q1 and Q2 are turned off. During this state, the free-wheeling current in leakage inductance LLK1 of the winding N1 flows through the body diode of Q1, so the voltage vds1 reduces to zero. If Q1 is turned on at this moment, ZVS is turned on. Although Q1 is turned on, LLK1 is demagnetized continuously, and the energy stored in LLK1 is returned to Vin and gradually decreases. During this state, iN1 < iN2. Since Q3 is kept at the turned-on state, there is still excess current flowing through Q3. As iN1 rises to zero, it enters State 6.
Figure 15.
Current path in State 5 under Skip Mode 2.
3.3.2. State 6
As shown in t5–t6 of Figure 16, after the demagnetizing of LLK1 in State 5 is completed, Q1, Q2, and Q3 are all turned off at this time, but iLK1 and iLK2 continue to flow through the windings N1 and N2, so there is still current flowing through the body diode of Q3.
Figure 16.
Current path in State 6 under Skip Mode 2.
3.3.3. State 7
As shown in t6–t7 of Figure 17, at this time, Q2 is turned on for the second time, the capacitor CB magnetizes Lm, causing iLm to rise, and at the same time CB discharges the output through N1 and N2, which are under the transformer mode.
Figure 17.
Current path in State 7 under Skip Mode 2.
3.3.4. State 8
As shown in t7–t8 of Figure 18, Q2 and Q3 are turned off for the second time, so iLK1 flows through the body diode of Q1, making vds1 zero. Hence, Q3 is turned on with ZVS.
Figure 18.
Current path in State 8 under Skip Mode 2.
3.3.5. State 9
As shown in t8–t0 of Figure 19, when vds1 is zero, Q1 is turned on at this time, and Q1 can be turned on with ZVS.
Figure 19.
Current path in State 9 under Skip Mode 2.
4. Experimental Results
The system parameters and components specifications are presented in Table 1.
Table 1.
System requirements and component specifications.
First, the conversion efficiency in Normal Mode, Skip Mode 1, and Skip Mode 2 are measured. As shown in Figure 20, both Skip Mode 1 and Skip Mode 2 can provide better conversion efficiency than Normal Mode when the load is below 15% of rated load, so the controller can enter skip mode to improve conversion efficiency up to 5%.
Figure 20.
Efficiency comparison at light load among Normal Mode, Skip Mode 1, and Skip Mode 2: (a) from zero to 30% of rated load; and (b) from zero to rated load.
Figure 21, Figure 22 and Figure 23 show the gate driving signals for Normal Mode, Skip Mode 1, and Skip Mode 2. Figure 24 shows the waveforms iN1 and iN2 in Normal Mode under different load levels. Figure 24 shows that, as the output current increases, the current ripples of iN1 and iN2 also increase. Figure 25 shows the waveforms iN1 and iN2 under different load levels in Skip Mode 1. After Q1 is turned off, Q2 is turned on twice in succession. When Q2 is turned on for the first time, iN1 is higher and transmits more energy to the output terminal. At the second ON, iN2 is lower and transmits less energy to the output terminal. Figure 26 shows the waveforms iN1 and iN2 under different load levels in Skip Mode 2. After Q1 is turned off, Q2 is turned on twice in succession. When Q2 is turned on for the first time, iN1 is higher and transmits more energy to the output terminal. At the second ON, iN2 is lower and transmits less energy to the output terminal. Figure 27 shows the waveforms vC1 and iC1 under different loads in Normal Mode. Figure 28 shows the waveforms vC1 and iC1 under different load levels in Skip Mode 1. Figure 29 shows that vC1 and iC1 under different loads in Skip Mode 2. In Figure 27, Figure 28 and Figure 29, the voltages across CB are almost the same.
Figure 21.
vgs1, vgs2, and vgs3 under Normal Mode: (a) 0.2 A; (b) 1 A; (c) 2 A; (d) 4 A; (e) 10 A; and (f) 20 A.
Figure 22.
vgs1, vgs2, and vgs3 under Skip Mode 1: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 23.
vgs1, vgs2, and vgs3 under Skip Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 24.
vgs1, vgs2, iCB, and iN2 under Normal Mode: (a) 0.2 A; (b) 1 A; (c) 2 A; (d) 4 A; (e) 10 A; and (f) 20 A.
Figure 25.
vgs1, vgs2, iCB, and iN2 under Skip Mode 1: (a) 0.2A; (b) 1A; (c) 2A; and (d) 4A.
Figure 26.
vgs1, vgs2, iCB, and iN2 under Skip Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 27.
vgs1, vgs2, vCB, and iCB under normal Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; (d) 4 A; (e) 10 A; and (f) 20 A.
Figure 28.
vgs1, vgs2, vCB, and iCB under Skip Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 29.
vgs1, vgs2, vCB, and iCB under Skip Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 30, Figure 31 and Figure 32 show the output voltage ripples vo (AC) operating in Normal Mode, Skip Mode 1, and Skip Mode 2, respectively. In these three figures, the difference in output voltage ripple between Normal Mode and Skip Mode 1 below the output current of 2 A is slight, but Skip Mode 1 has a little higher output voltage ripple at 4 A than Normal Mode. Below the output current of 1 A, Skip Mode 2 has a slightly higher voltage ripple than Skip Mode 1, but both are similar above the output current of 2 A.
Figure 30.
vgs1, vgs2, Skip_EN, and vo(AC) under Normal Mode: (a) 0.2 A; (b) 1 A; (c) 2 A; (d) 4 A; (e) 10 A; and (f) 20 A.
Figure 31.
vgs1, vgs2, Skip_EN, and vo(AC) under Skip Mode 1: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 32.
vgs1, vgs2, Skip_EN, and vo(AC) under Skip Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 33 and Figure 34 are the waveforms for the mode exchange between Normal Mode and Skip Mode 1 under different load levels. Under different output current levels, the mode exchange has a slight effect on vo.
Figure 33.
SkipEN and vo(DC) under Normal Mode switched to Skip Mode 1: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 34.
SkipEN and vo(DC) under Skip Mode 1 switched to Normal Mode: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 35 and Figure 36 are the waveforms for the mode exchange between Normal Mode and Skip Mode 2 under different output current levels. Under different output current levels, the mode exchange has a slight effect on vo.
Figure 35.
SkipEN and vo(DC) under Normal Mode switched to Skip Mode 2: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Figure 36.
SkipEN and vo(DC) under Skip Mode 2 switched Normal Mode: (a) 0.2 A; (b) 1 A; (c) 2 A; and (d) 4 A.
Accordingly, the transient responses due to mode exchange between Normal Mode and Skip Mode 1 and between Normal Mode and Skip Mode 2 are quite similar.
5. Discussion
The light-load efficiency and the output voltage ripple discussed herein are under the condition that the traditional PWM control strategy used in [20,21] is considered as Normal Mode. Therefore, based on the same circuit structure as in [20,21], this paper presents two skip mode control strategies to improve the light-load efficiency. Although the switching frequency used in these two strategies is reduced, the transferred energy is unchanged, but the output voltage ripple is influenced to some extent as compared to Normal Mode. In addition, the mode exchange among the three control strategies is very smooth. The proposed PWM control strategies can be applied to the structures in [20,21] to improve the light-load efficiency.
6. Conclusions
This paper presents two PWM control strategies to increase the efficiency at the light-load condition for the high step-down converter. The experimental results show that the light-load efficiency can be effectively improved without generating a larger output voltage ripple. The skip mode is provided to improve the light-load efficiency up to 5% when the load is below 15% of rated load. The light-load efficiency can be improved by two types of modified PWM control sequence as Skip Mode 1 and Skip Mode 2. Furthermore, the mode exchange is quite smooth, and the output voltage ripple does not change significantly.
Author Contributions
Conceptualization, Y.-T.Y.; methodology, Y.-T.Y.; software, C.-W.W.; validation, Y.-T.Y.; formal analysis, Y.-T.Y.; investigation, C.-W.W.; resources, Y.-T.Y.; data curation, C.-W.W.; writing—original draft preparation, K.-I.H.; writing—review and editing, K.-I.H.; visualization, C.-W.W.; supervision, K.-I.H.; project administration, K.-I.H.; and funding acquisition, Y.-T.Y. All authors have read and agreed to the published version of the manuscript.
Funding
This research was funded by the Ministry of Science and Technology, Taiwan, under the Grant Number: MOST 109-2222-E-167-003-MY3.
Data Availability Statement
No new data were created or analyzed in this study. Data sharing is not applicable to this article.
Conflicts of Interest
The authors declare no conflict of interest.
Abbreviations
| AC | Alternating Current |
| CCM | Continuous Current Mode |
| DC | Direct Current |
| IC | Integrated Circuit |
| POL | Power on Load |
| PWM | Pulse-Width-Modulated |
| ZVS | Zero Voltage Switching |
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