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Journal of Low Power Electronics and Applications, Volume 4, Issue 2

June 2014 - 7 articles

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Articles (7)

  • Article
  • Open Access
6 Citations
17,638 Views
15 Pages

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

  • Yongxun Liu,
  • Toshihide Nabatame,
  • Takashi Matsukawa,
  • Kazuhiko Endo,
  • Shinichi O'uchi,
  • Junichi Tsukada,
  • Hiromi Yamauchi,
  • Yuki Ishikawa,
  • Wataru Mizubayashi and
  • Yukinori Morita
  • + 4 authors

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SC...

  • Article
  • Open Access
11 Citations
10,207 Views
15 Pages

MOS Current Mode Logic Near Threshold Circuits

  • Alexander Shapiro and
  • Eby G. Friedman

Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML...

  • Review
  • Open Access
5 Citations
13,790 Views
19 Pages

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip...

  • Article
  • Open Access
2 Citations
8,678 Views
9 Pages

Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs

  • Kazuhiko Endo,
  • Shinji Migita,
  • Yuki Ishikawa,
  • Takashi Matsukawa,
  • Shin-ichi O'uchi,
  • Junji Tsukada,
  • Wataru Mizubayashi,
  • Yukinori Morita,
  • Hiroyuki Ota and
  • Hitomi Yamauchi
  • + 1 author

A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coup...

  • Article
  • Open Access
6 Citations
8,266 Views
20 Pages

With the advanced technology used to design VLSI (Very Large Scale Integration) circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attract...

  • Article
  • Open Access
16 Citations
14,570 Views
13 Pages

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

  • Pooja Batra,
  • Spyridon Skordas,
  • Douglas LaTulipe,
  • Kevin Winstel,
  • Chandrasekharan Kothandaraman,
  • Ben Himmel,
  • Gary Maier,
  • Bishan He,
  • Deepal Wehella Gamage and
  • John Golz
  • + 11 authors

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. P...

  • Review
  • Open Access
11 Citations
9,391 Views
12 Pages

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

  • Nobuyuki Sugii,
  • Yoshiki Yamamoto,
  • Hideki Makiyama,
  • Tomohiro Yamashita,
  • Hidekazu Oda,
  • Shiro Kamohara,
  • Yasuo Yamaguchi,
  • Koichiro Ishibashi,
  • Tomoko Mizutani and
  • Toshiro Hiramoto

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in...

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J. Low Power Electron. Appl. - ISSN 2079-9268