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J. Low Power Electron. Appl., Volume 3, Issue 2 (June 2013) – 7 articles , Pages 54-214

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Open AccessArticle
Bias-Flip Technique for Frequency Tuning of Piezo-Electric Energy Harvesting Devices
J. Low Power Electron. Appl. 2013, 3(2), 194-214; https://doi.org/10.3390/jlpea3020194 - 18 Jun 2013
Cited by 7 | Viewed by 5169
Abstract
Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. Manufacturing tolerances make it difficult to match the Energy Harvesting Device (EHD) [...] Read more.
Devices that harvest electrical energy from mechanical vibrations have the problem that the frequency of the source vibration is often not matched to the resonant frequency of the energy harvesting device. Manufacturing tolerances make it difficult to match the Energy Harvesting Device (EHD) resonant frequency to the source vibration frequency, and the source vibration frequency may vary with time. Previous work has recognized that it is possible to tune the resonant frequency of an EHD using a tunable, reactive impedance at the output of the device. The present paper develops the theory of electrical tuning, and proposes the Bias-Flip (BF) technique, to implement this tunable, reactive impedance. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
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Open AccessArticle
Reconfigurable Threshold Logic Gates using Memristive Devices
J. Low Power Electron. Appl. 2013, 3(2), 174-193; https://doi.org/10.3390/jlpea3020174 - 24 May 2013
Cited by 16 | Viewed by 5352
Abstract
We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized [...] Read more.
We present our design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using silver–chalcogenide memristive devices combined with CMOS circuits. Results from simulations and physical circuits are shown. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in discrete hardware using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
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Open AccessArticle
A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers
J. Low Power Electron. Appl. 2013, 3(2), 159-173; https://doi.org/10.3390/jlpea3020159 - 24 May 2013
Viewed by 6240
Abstract
Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power [...] Read more.
Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking. The circuit enables flexible tuning of the offset voltage. Measurements taken from a 45 nm test chip show the circuit is able to limit the offset to 20 mV. A 16kB SRAM is designed using the auto-zeroing circuit for the sense amps. The reduction in the total read energy and delay is reported for various configurations of the memory. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
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Open AccessReview
Synergistic Sensory Platform: Robotic Nurse
J. Low Power Electron. Appl. 2013, 3(2), 114-158; https://doi.org/10.3390/jlpea3020114 - 24 May 2013
Viewed by 4683
Abstract
This paper presents the concept, structural design and implementation of components of a multifunctional sensory network, consisting of a Mobile Robotic Platform (MRP) and stationary multifunctional sensors, which are wirelessly communicating with the MRP. Each section provides the review of the principles of [...] Read more.
This paper presents the concept, structural design and implementation of components of a multifunctional sensory network, consisting of a Mobile Robotic Platform (MRP) and stationary multifunctional sensors, which are wirelessly communicating with the MRP. Each section provides the review of the principles of operation and the network components’ practical implementation. The analysis is focused on the structure of the robotic platform, sensory network and electronics and on the methods of the environment monitoring and data processing algorithms that provide maximal reliability, flexibility and stable operability of the system. The main aim of this project is the development of the Robotic Nurse (RN)—a 24/7 robotic helper for the hospital nurse personnel. To support long-lasting autonomic operation of the platform, all mechanical, electronic and photonic components were designed to provide minimal weight, size and power consumption, while still providing high operational efficiency, accuracy of measurements and adequateness of the sensor response. The stationary sensors serve as the remote “eyes, ears and noses” of the main MRP. After data acquisition, processing and analysing, the robot activates the mobile platform or specific sensors and cameras. The cross-use of data received from sensors of different types provides high reliability of the system. The key RN capabilities are simultaneous monitoring of physical conditions of a large number of patients and alarming in case of an emergency. The robotic platform Nav-2 exploits innovative principles of any-direction motion with omni-wheels, navigation and environment analysis. It includes an innovative mini-laser, the absorption spectrum analyser and a portable, extremely high signal-to-noise ratio spectrometer with two-dimensional detector array. Full article
(This article belongs to the Special Issue Energy Efficient Sensors and Applications)
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Open AccessArticle
Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT) Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT) in a Digital Radio Mondiale (DRM) and DRM+ Receiver
J. Low Power Electron. Appl. 2013, 3(2), 99-113; https://doi.org/10.3390/jlpea3020099 - 24 May 2013
Cited by 8 | Viewed by 3841
Abstract
This paper presents a compact structure of recursive discrete Fourier transform (RDFT) with prime factor (PF) and common factor (CF) algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point [...] Read more.
This paper presents a compact structure of recursive discrete Fourier transform (RDFT) with prime factor (PF) and common factor (CF) algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051) and 11.5 (or 0.1176) mW at 25 (or 0.273) MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications. Full article
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Open AccessArticle
Low Power Dendritic Computation for Wordspotting
J. Low Power Electron. Appl. 2013, 3(2), 73-98; https://doi.org/10.3390/jlpea3020073 - 21 May 2013
Cited by 15 | Viewed by 4829
Abstract
In this paper, we demonstrate how a network of dendrites can be used to build the state decoding block of a wordspotter similar to a Hidden Markov Model (HMM) classifier structure. We present simulation and experimental data for a single line dendrite and [...] Read more.
In this paper, we demonstrate how a network of dendrites can be used to build the state decoding block of a wordspotter similar to a Hidden Markov Model (HMM) classifier structure. We present simulation and experimental data for a single line dendrite and also experimental results for a dendrite-based classifier structure. This work builds on previously demonstrated building blocks of a neural network: the channel, synapses and dendrites using CMOS circuits. These structures can be used for speech and pattern recognition. The computational efficiency of such a system is >10 MMACs/μW as compared to Digital Systems which perform 10 MMACs/mW. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
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Open AccessArticle
Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling
J. Low Power Electron. Appl. 2013, 3(2), 54-72; https://doi.org/10.3390/jlpea3020054 - 29 Apr 2013
Cited by 28 | Viewed by 4669
Abstract
Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their [...] Read more.
Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz. Full article
(This article belongs to the Special Issue Selected Papers from SubVt 2012 Conference)
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