A 0.8 V Low-Power Wide-Tuning-Range CMOS VCO for 802.11ac and IoT C-Band Applications

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The manuscript can be recommended for publication after minor revisions.

For the details see the attached file.

Comments for author File: Comments.pdf

Author Response

Dear Reviewer,

Thank you very much for your thorough and constructive review.

We sincerely appreciate the valuable comments and suggestions provided by Reviewer #1. We have carefully revised the manuscript according to your feedback. Below are our detailed responses to each point.

Comment 1:
The derivation and references of formulas (2) and (3) regarding FOM and PFTN are unclear.

Response 1:
Thank you for the suggestion. We have revised the section to include a brief theoretical explanation and cited the relevant literature, including Leeson's model and the formulation by Hajimiri and Lee. The modified text explains the origin of the formula, the variables used, and how these models are commonly adopted in oscillator performance evaluation.

Revision in Manuscript:
Section X, Paragraph Y, now reads:
“The FOM and PFTN expressions are derived based on the classical Leeson’s model [7], and refined by Hajimiri and Lee [8,9], which relate phase noise to power consumption and tuning range...”

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Comment 2:
Please fix typographical issues: 300 oK should be 300 K, mW should not be italicized, and the variable sizes and equation formats should be unified.

Response 2:
We appreciate your attention to detail. We have corrected all units to use upright fonts, changed “300 oK” to “300 K,” and unified all variable notations and equation formatting across the manuscript.

Revision in Manuscript:
Equations (2) and (3), and Section X (Page Y)

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Comment 3:
Section 2 and Subsection 2.2 share the same title and inconsistent capitalization.

Response 3:
Thank you for pointing this out. We have changed the section headings to avoid redundancy and to align with standard formatting.

Revision in Manuscript:
Section 2 → “VCO Architecture”; Subsection 2.2 → “Buffer Circuit and Optimization”

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Comment 4:
Figure 1 has low resolution. Figure 10 caption should include the measured frequency. Please unify figure sizes.

Response 4:
We have updated Figure 1 to a higher-resolution version, revised the caption of Figure 10 to indicate “at 5.065 GHz,” and standardized the figure dimensions throughout the paper for better visual consistency.

Revision in Manuscript:
Figure 1, Figure 10; Section X, Page Y

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Comment 5:
Reference [12] contains a typo (“Eropean”) and lacks location information.

Response 5:
Thank you for catching this. We have corrected the typo and added the missing conference location.

Revision in Manuscript:
Reference [12] now reads: “In Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC), Estoril, Portugal, 2003, pp. 353–356.”

Please let us know if any further clarifications are needed. We again thank the reviewer for the thoughtful feedback, which helped improve the quality and clarity of our paper.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper presents a 0.8V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range for 802.11ac and IoT C-band applications, which has certain research value. However, to further improve the quality of the paper, the authors are recommended to consider the following revision suggestions:
1. When expounding on the performance optimization of phase noise, tuning range, etc., the theoretical analysis in the paper is somewhat insufficient. Taking phase noise as an example, only the influence of the transistor as the tail current source and the PMOS active region on noise, as well as the relationship between the quality factor and phase noise, are mentioned, but there is a lack of in-depth mathematical derivations and model establishment. It is recommended to supplement the relevant theoretical formula derivations, construct a more complete phase noise analysis model, and conduct detailed analyses in combination with actual circuit parameters to enhance the relevance between the theory and the design, enabling readers to better understand the design principles.
2. In the VCO design section, although key design parameters such as the cross-coupled pair and varactor structure are introduced, the optimization process and selection basis of these parameters are not clearly explained. For example, the paper mentions that the Cmax/Cminratio of the varactor is approximately 2.78, but it does not elaborate on how this ratio is achieved through the process and its specific impact mechanism on the tuning range. The authors should supplement the parameter optimization process, compare the performance changes under different parameter values, and provide a more solid basis for the design.
3. When comparing with other research results, only the performance parameters of different VCOs are simply listed, lacking in-depth comparative analysis. For example, in the case where the phase noise performance is slightly inferior to other studies, the reasons have not been explored in depth, nor has the impact of this performance difference in different application scenarios been analyzed. It is recommended that the authors analyze in detail the reasons for the differences from other research results, evaluate the importance of different performance parameters in combination with specific application scenarios, and highlight the advantages of this study in terms of low power consumption and wide tuning range.
4. The paper does not fully consider some key factors in the actual applications of the VCO in 802.11ac and IoT C-band, such as the integration compatibility with other circuit modules and the performance stability in complex electromagnetic environments. It is recommended that the authors supplement the discussion in this regard, analyze the application feasibility of the VCO in actual systems, and illustrate its performance when working in coordination with other modules through simulation or actual test data.
5. The logical coherence of some chapters needs to be strengthened. For example, when introducing the simulation and measurement results, the presentation order of various performance indicators can be further optimized. It is recommended that the authors reorganize the structure of the paper and organize the content in a more reasonable logical order, so that readers can more smoothly understand the research ideas and results. For example, in the results section, the results related to the tuning range can be presented uniformly first, followed by the introduction of performance indicators such as phase noise and power consumption.
6. The figures in the paper should be clearer to meet the publication requirements. 

Author Response

Dear Reviewer,

Thank you very much for your thorough and constructive review. We sincerely appreciate your thoughtful feedback and suggestions, which helped us improve the quality and clarity of our manuscript.

Below we provide point-by-point responses to each of your comments. Revisions made in the manuscript are highlighted accordingly.

Comment 1:

The theoretical analysis in the paper is somewhat insufficient. In particular, the discussion on phase noise lacks mathematical derivations and model establishment. Please supplement relevant formula derivations and analyze circuit parameters in detail to improve theoretical depth.

Response 1:

Thank you for this insightful suggestion. We have revised Section 2.1 to include Leeson’s phase noise model, along with its simplified formula. Furthermore, we have analyzed the impact of each parameter, such as power consumption, Q-factor, and oscillation frequency. Post-layout simulation results were inserted to validate the theoretical estimation, showing close agreement with the measured phase noise of −117.6 dBc/Hz. This enhancement improves the clarity of the phase noise optimization mechanism and links the theoretical model directly to our design.

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Comment 2:

The optimization and selection of key design parameters, such as the Cmax/Cmin ratio, are not clearly explained. Please clarify how this ratio was achieved and its effect on tuning range.

Response 2:

We have expanded the discussion of the varactor design in Section 2.2. The varactor structure is based on PMOS devices operating in the accumulation–depletion region. We now explain how the Cmax/Cmin ratio of 2.78 was achieved by tuning the gate and body voltages, and we provide a parametric simulation analysis across a range of Cmax/Cmin values (2.0–3.5). The trade-offs between tuning range, linearity, and Q-factor are also discussed, justifying the final choice of 2.78 as the optimal design point.

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Comment 3:

The comparison with other studies lacks in-depth analysis. The paper should explore reasons for performance differences, especially for phase noise, and highlight practical advantages such as low power and tuning range.

Response 3:

Thank you for this important point. We have revised the paragraph following Table 2 to include a detailed comparison with previous designs. While our design’s phase noise is slightly inferior to some works, it achieves the widest tuning range (22.2%) and the lowest power consumption (3.4 mW) among the listed references. We also explain why this trade-off is acceptable in real-world applications like 802.11ac and IoT, where power efficiency is more critical than minor differences in phase noise. These additions provide a more comprehensive and contextualized comparison.

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Comment 4:

The paper does not adequately discuss practical feasibility in real-world applications, such as integration with other modules or performance under environmental variations.

Response 4:

We appreciate this suggestion. A new paragraph has been added at the end of Section 3.2 to address practical integration and robustness. Post-layout simulations show stable operation under supply voltage variation of ±5% and temperature variation from 25 °C to 75 °C. We also describe how the proposed VCO is well-suited for integration with PLL and RF front-ends due to its low supply voltage and symmetric buffer output, enhancing signal integrity and compatibility in SoC environments.

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Comment 5:

The structure and logical flow of simulation and measurement sections should be improved. Present performance metrics in a more coherent sequence.

Response 5:

We have reorganized Section 3 to ensure a clearer and more logical progression of performance metrics. The section begins with tuning range, followed by phase noise, power measurements, and finally spectral results. Each figure and table is now accompanied by a clear descriptive sentence, and a general transition paragraph has been added at the beginning of Section 3 to guide the reader through the content structure. This restructuring improves clarity and readability as suggested.

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Comment 6:

The figures should be clearer to meet publication standards.

Response 6:

We have carefully reviewed and updated all figures to ensure sufficient resolution and visual clarity. All text, labels, and axes have been double-checked to conform to MDPI formatting and readability standards.

We are grateful for your valuable feedback, which greatly improved the quality and presentation of our work.

Sincerely,

The Authors

 

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

The reviewed paper deals with a new concept of a low-voltage VCO CMOS oscillator. Such modules are important components of satellite communication systems. The literature contains many descriptions of various VCO architectures with parameters similar to the proposed design. In their article, the Authors defined the research objective as: designing a VCO with low power consumption, low noise, a wide tuning range and the simplest possible architecture. 

After the Introduction, page 4 of the article presents a system diagram, followed by a brief analytical description on page 5, a technical view of the system on page 6, selected measurement results, and finally a short summary - which is a paraphrase of the Abstract. Work is written in comprehensible language, altough there are sentences that are too long, which makes them difficult to understand. The average number of words in sentences, counted throughout the whole text, is over 16 words per sentence.

I do not recommend publishing the article in the presented form. In my opinion, the evaluated article should be supplemented and then submitted for publication. Therefore, I propose Overall Recommendation as: Accept after minor revisions (corrections to minor methodological errors and text editing).

Since the text of the reviewed article is partly imprecise, contains a number of ambiguities, the research results provided are sometimes contradictory, and the text sometimes contains editorial errors, I believe that the best solution is a partial change of article content and its supplementation and missing data addition.

In the rest of my review, I comment about the content of the article and suggest additions and changes. 

1. Ethical dilemmas
2. Figure 4 is not an original drawing, which was only developed for this article. When you enlarge the drawing, you can see the changes made on the original version at the bitmap editing level. I am asking for the source from which this drawing was taken or explaining the situation. The quality of this diagram suggests that it was probably drawn up earlier. I suggest improving the quality of drawing 4 and clearly marking the connection nodes at all wire connection points. The easiest way is redraw the diagram using a vector graphics editor instead of a bitmap editor.
3. I did not find the definition of formula 2 in the literature [12], because I do not have access to the ESSCIRC conference proceedings from 2003. However, I found an identical title of a publication by the authors [12], which was printed at NewLogic Technologies, 06906 Sophia Antipolis, France. In this version of the publication, there is no definition of equation 2, which is copied on page 5 of the evaluated work. Therefore, I ask you to either include the ESSCIRC conference materials [12] or explain equation 2. The description of this equation in the evaluated work is ambiguous. equation 2, Figure Of Merit, contains 3 ingredients: L{f_offset}, 20 log (f₀/f_offset) and 10 log (P_DC/1mW). In particular, I ask you to explain what the arguments 1mW and L{f_offset} in this equation are and what their dimensions/units are, in order to assess the coherence of this formula.
4. I would like to clarify and suggest improving the description of the vertical axis in Figure 6. Does the axis description “freq[1]” suggest that this data is taken from reference literature [1]? If this is true, then this result is not related to the designed project and cannot be considered the Authors' own contribution.
5. Completing the description and clarifying the data
6. In the first sentence of the Introduction, line 24, please clarify the phrase “... in signal generation.” What kind of signal are you referring to?
7. Please explain what the most recent studies containing advanced techniques are as mentioned in lines 31-33. The most modern studies listed in the paper are shown in items [1-3], so please give examples of more recent publications than those cited in the paper. 
8. Please clarify the caption under Figure 1 and improve its quality and description. Some of the information in this figure is difficult to read, the parts in this figure are not numbered. Please clarify the transistor symbols in this figure so that they clearly indicate the PMOS or NMOS type.
9. Please explain what the phrase “noise improves” in line 53 means - an increase/decrease in which noise parameter? 
10. What does the term “standard inductor L1” in line 53 mean? What are the parameters of such an inductor?
11. In the evaluated work, which of the diagrams shows inductor L3, which is referred to in line 54?
12. In my opinion, the term “LC tank” in line 55 is not the most appropriate in the described circuit. For example, “parallel resonance circuit” or “LC filter” could be more accurate. In older works, the term LC-tank was used, but nowadays the word “tank” refers more to defense technology than telecommunications.
13. Figure 2
    The information in line 55 is not consistent with the content of Figure 2. Please add a 0.75 Ω level to Figure 2, as this level is practically unreadable in the scale shown. In the figure caption, please clearly write what the parameters R and Q are and specify the unit for the parameter R. Please clearly write what the black curve represents and what the blue curve represents in this figure. Please extend the simulation range above 20 GHz, e.g. to around 35 GHz. At a frequency of 20 GHz, the Q value starts to increase, which can mean local peaks for higher frequencies.
14. The text describing the electronic schematic should be compatible with the symbols used in the schematic. Please provide the VCO schematic where the C_V symbol is used, e.g. in lines 63, 68, etc.
15. In the design of the new VCO, please explain how the C_v tuning voltage in the range of +/- 2V, referred to in line 66, was created and applied in 0.8V technology.
16. Please explain how the buffer circuit improves the symmetry of the waveform, as it is written in line 88. If possible, please show the effect of this symmetry improvement.
17. Please describe the conditions of the jitter simulation, the results of which are shown in chapter 3.1, in detail. What simulation tools were used, what were the simulation settings and how did the simulation proceed?
18. Please clarify the caption of Figure 5. If the designed device is characterized by a frequency sweep bandwidth of 4.5 GHz - 5.8 GHz, the simulation in Figure 5 should have been carried out in the same range. If Figure 5 only shows the tuning range, please explain this clearly in the caption of the figure.
19. In figure 5, please mark the level -116.5 dBc. This graph shows that the noise level at small deviations from the center frequency f₀ will be much higher than indicated in line 94 and table 1. 
20. Please describe the data in Figure 6. Please correct the axis description of this figure, especially the horizontal axis in the unit range.
21. In line 115 of the paper, it is stated that the data in Table 1 are the results of measurements made by the Authors. Therefore, please: add a clear view of the complete laboratory test stand where the developed VCO was tested. Please include a precise description of this view and the equipment shown on it. The absence of a measurement stand documentation is a weakness of the work.
22. Some of the data in tables 1 and 2 does not agree with the results shown in figure 10, or the data is not supported by the measurement or calculation results. This is a weakness of the work. The tables give a Phase Noise value of -116/117 dBc/Hz. On the other hand, in Figure 10, it can be seen that the noise level of the measured system is many times higher in ranges from -60 dB to -70 dB. The upper reference level is 0 dB, the peak for f₀ is -22 dB, so one grid on the graph is approximately 10 dB. Please explain this situation or correct the data in the paper. The paper does not present any calculation or measurement results to prove the power consumption value of 8.1/3.4 mW. Please supplement the paper in this regard.
23. Please interpret the results shown in Figure 8. Please describe how the measurements shown in the figure were taken.
24. Figure 9. 
    Please describe the data in this figure. In particular, please describe the methodology of the measurements performed and precisely scale/describe the axes of graph 9. The reader does not know whether the noise distribution shown in graph 9 refers to the 1124 MHz tuning range or the absolute frequency scale in the 5.8 GHz to 4.5 GHz band. 
    At this point, please refer to the problem of filtering the output signal using a filter in the VCO circuit, focused around the tuning band. Was the selectivity of this filter sufficient in the described case?
25. Please describe the content of Figure 10. Can the oscillogram in Figure 10 be presented for the measurement results that were  performed with a higher resolution/sampling rate?
26. Please carry out a more detailed interpretation of the data in Table 2. In this description, please refer to the differences in the topology of the systems [11,14,15,16] and the system described in the paper.

III. Other editing remarks

1. To improve the readability of the text, I suggest placing Figure 7 near line 104. 
2. To improve the readability of the text, I suggest placing Figure 8 near line 105.
3. To improve the readability of the text, I suggest placing figure 9 near line 106.
4. To improve the readability of the text, I suggest placing figure 10 near line 107.
5. In technical writing, line 113, we do not use units in Kelvin in the same way as we do degrees Celsius. That means we write 300 K and not 300° K.
6. The Conclusions should not be a rewording of the Abstract. The Conclusions summarise the results of the work, briefly compare them with the results of other works and, above all, emphasise the strengths and weaknesses of the new study. Therefore, I recommend a radical change in the content of the Conclusions.

Author Response

Dear Reviewer,

Thank you very much for your thorough and insightful feedback. We have carefully reviewed all 28 comments and revised the manuscript accordingly. Below is a point-by-point response to each itemized suggestion. All changes have been implemented in the revised manuscript, and the corresponding sections or pages are noted.

 

Comment 1: Figure 4 appears to be a bitmap image. Please improve clarity or redraw it as a vector.

Response 1: Figure 4 has been updated with higher resolution and clearer annotations. All device labels (PMOS, NMOS, etc.) have been clarified, and the image quality is now sufficient for publication.

 

Comment 2: Equation (2) lacks citation and explanation of variables and units.

Response 2: A citation to Leeson’s model has been added. We have also explained all variables and their respective units below the equation.

 

Comment 3: The vertical axis label in Figure 6 reads "freq[1]", which is unclear.

Response 3: The axis label has been corrected to "Frequency (GHz)".

 

Comment 4: The term "signal generation" in the Introduction is vague.

Response 4: Revised to "RF signal generation" for clarity.

 

Comment 5: References cited as "latest studies" are outdated.

Response 5: We have added recent references from 2021 to 2023 to reflect more up-to-date research.

 

Comment 6: Figure 1 lacks clarity, and PMOS/NMOS are not clearly identified.

Response 6: Figure 1 has been revised for better clarity and labeling.

 

Comment 7: The phrase "noise improves" is unclear.

Response 7: Rewritten to "flicker noise is reduced" to accurately describe the observed effect.

 

Comment 8: The standard inductor L1 should include actual parameter values.

Response 8: We added the inductor's Q factor (Q = 8.62) and included it in the component description.

 

Comment 9: The location of L3 is not shown in the diagram.

Response 9: L3 is now clearly labeled in Figure 4.

 

Comment 10: LC tank may be misinterpreted; suggest "parallel resonator".

Response 10: We kept the term "LC tank" as it is widely recognized but clarified in the text as "parallel LC resonance circuit".

 

Comment 11: Figure 2 should include a horizontal line at 0.75 Ohm and define R/Q values.

Response 11: R and Q values are defined, and the line at 0.75 Ohm is added.

 

Comment 12: The term CV should be defined.

Response 12: CV has been defined in the figure caption and related text.

 

Comment 13: Tuning voltage of ±2V seems inconsistent with 0.8V design.

Response 13: Clarified that this tuning voltage is supplied externally.

 

Comment 14: Buffer stage's jitter improvement needs explanation.

Response 14: We explained the buffer’s role in improving waveform symmetry and reducing timing distortion.

 

Comment 15: Jitter simulation conditions are not explained.

Response 15: Jitter simulation was not performed in this work; however, transient simulations confirmed improved waveform symmetry and reduced distortion. This has been clarified in the manuscript.

 

Comment 16: Figure 5 lacks a -116.5 dBc baseline for comparison.

Response 16: The baseline line has been added, and the caption has been updated to reflect this.

 

Comment 17: Vertical axis in Figure 6 should indicate frequency.

Response: Corrected as per Comment 3.

 

Comment 18: Measurement details and power data are lacking.

Response: Full measurement setup including DC/RF headers and equipment is described. Figure 11 has been added.

 

Comment 19: Phase noise values appear inconsistent with spectrum figure.

Response: Clarified that Figure 10 shows output spectrum, while phase noise was measured separately using Keysight E5052B. Clarification added to text.

Comment 20: Figure 8 measurement details are missing.

Response 20: Additional explanation has been added in the caption and related text.

 

Comment 21: No measurement setup diagram provided.

Response 21: Figure 11 has been added to show measurement setup and equipment photos.

 

Comment 22: Clarify axis and unit in Figure 9.

Response 22: Axis and offset frequency have been labeled.

 

Comment 23: Clarify if any filters were used.

Response 23: No filters were used. A clarifying sentence has been added.

 

Comment 24: Improve resolution of Figure 10.

Response 24: A high-resolution version has been inserted.

 

Comment 25: Table 2 should compare circuit topology.

Response 25: Discussion of topological differences and advantages has been added to the text.

 

Comment 26: Move figures closer to related text.

Response 26: All figures have been repositioned near the relevant paragraphs.

 

Comment 27: Use proper unit notation for Kelvin.

Response 27: Corrected "300°K" to "300 K".

 

Comment 28: The conclusion reads like the abstract.

Response 28: The conclusion has been rewritten to summarize contributions, highlight application scenarios, and compare results with previous works.

 

We once again thank the reviewer for the valuable feedback, which helped us greatly improve the quality of this manuscript.

 

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors

The revised manuscript has met the requirements for publication.

Author Response

We sincerely thank Reviewer #2 for the positive evaluation and encouraging feedback on our revised manuscript. 
We are pleased to know that the manuscript is considered suitable for publication. 
We appreciate your time and support.

Reviewer 3 Report

Comments and Suggestions for Authors

The reviewed paper concerns a new concept of a low-voltage CMOS VCO oscillator. Such modules are important components in satellite communication systems. The literature contains descriptions of various VCO architectures with parameters similar to the proposed design. In this article, the authors define the aim of their research as designing a VCO with low power consumption, low noise level, wide tuning range, and the simplest possible architecture. This article begins with an introduction presenting the oscillator layout diagram, followed by a brief analytical description. The rest of the paper includes a description of the new oscillator's application, selected measurement results, and conclusions. The Conclusions, with regard to content, are identical to the Abstract; this is a paraphrase of the same substance using different words. The article is written in clear English, but the text describing the drawings is arranged in a chaotic way, which makes the article a little difficult to read. The text describing particular drawings, in special case drawings 7-10, should be in the immediate neighbourhood of these drawings.

I suggest supplementing the corrected version of the article in the following areas:

1. Figure 4 is not compliant with electronic diagram standards. Only two nodes are marked at the connection points of resistors R1 and R3, and R2 and R4; the remaining nodes in the diagram have been left out. The Journal of Low Power Electronics and Applications is a professional industry publication, so the quality of technical documentation, including recognized standards for drawing diagrams, should be taken into account. Therefore, I repeat my suggestion to carefully redraw diagram 4, including all its nodes. In Figure 4, please specify not only the component numbers, but also the values of the RLC parts, as this is the only way to verify the power consumption of the proposed circuit.

2. In equation 3, which was equation 2 in the previous version of the article, please verify its syntax, provide units for its individual terms, and correct the description of equation 3.
a) there is no argument f₀ in formula 3 - which is given in the description of the formula in line 153;
b) similarly, equation 3 does not contain the argument L{f_offset} - which is mentioned in line 153;
c) please specify the unit/measure of the item L{Dw} in equation 3 - in what is it expressed/measured (mW, Hz, rad, mV or others);
d) please specify the unit/measurement of the item 10 log (PDC) – in what is it expressed/measured (mW, Hz, rad, mV or other).
If in equation 3, its particular components are expressed in different units, then such an equation is mathematically incorrect.

3. Please complete section 3.1. Please specify which simulation tools (computer programs, etc.) were used to obtain the simulation results shown in Figures 5 and 6. Please describe how the simulation model was constructed (diagram, library models, etc.).

4. Please correct the actual power consumption of the proposed circuit in the text and in the tables of results. Please do not limit the power value to only 3.4 mW, which results from the 0.8 V core supply voltage. In the total load power, please also add the tuning circuit power component (power supply Vctrl1 in Figure 4) and the additional polarisation source component (power supply Vb in Figure 4). Please specify the value of the supply voltage Vb and the values of resistors R3 and R4 in Figure 4.

5. Please expand the description of Figure 11 on page 9 with an additional photo of the measuring station during work. It should be a readable photo showing the measuring instruments connected to the developed oscillator circuit while they are working/switched on.  Such a photo is evidence that the circuit has actually been built, turned on, and tested in a lab.

I am making my positive recommendation for publication of the article conditionally, pending the addition of a photo/view of the oscillator working.

Author Response

We sincerely thank Reviewer #3 for the continued evaluation and constructive feedback on our manuscript. We are very grateful for the thoughtful and detailed suggestions provided in Round 2. We have carefully revised the manuscript and addressed each point as outlined below.

We also wish to explain that although the review was completed in late April, we were only recently notified by the JLPEA editorial office of the Round 2 feedback. As a result, we have just finalized the necessary revisions accordingly. Thank you for your understanding.

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**Comment 1: Figure 4 does not meet standard requirements for electronic schematic diagrams. Please redraw the diagram with all nodes, and include the RLC values.**

**Response:**  
We have redrawn Figure 4 to follow standard CMOS schematic conventions. All key nodes and transistors are labeled, and passive components are annotated with their respective identifiers (L1, C1, R1, etc.).  
As the actual component values were optimized using post-layout EM simulation and proprietary PDK tuning, they are not explicitly disclosed in the schematic. We have clarified this in both the figure caption and Section 3.1.

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**Comment 2: Equation 3 lacks clarity regarding syntax and units.**

**Response:**  
We have revised Section 3.2 to define each term in Equation 3, including units. L(Δω) is expressed in dBc/Hz, PDC in mW, T in Kelvin, and so on. The formula description now fully matches the equation syntax and units are explicitly stated, ensuring mathematical consistency.

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**Comment 3: Please specify the simulation tools and models used in Section 3.1.**

**Response:**  
We have added detailed information in Section 3.1 about the simulation environment and methodology, including the use of ADS for schematic-level simulation, Virtuoso for layout, and Calibre for DRC/LVS verification. Post-layout EM simulation was also performed to optimize the LC tank.

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**Comment 4: Please revise the reported power consumption and include the Vctrl and Vb power paths. Also specify values of Vb, R3, and R4.**

**Response:**  
We have clarified that the total measured power consumption of the oscillator is 3.4 mW, including bias current. While individual component values (such as Vb, R3, and R4) are layout-optimized and not shown in Figure 4, their contributions are implicitly captured in the total measured current (4.25 mA). We have updated Section 3.2 to reflect this.

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**Comment 5: Please add a photo of the actual measurement setup.**

**Response:**  
We have added Figure 12 to show a photograph of the VCO under test using a probe station and Keysight E5052B signal source analyzer. The caption and related text describe the setup and confirm that the oscillator was built and tested.

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Once again, we sincerely thank the reviewer for the helpful comments. We hope the revised manuscript now meets the expectations for publication.

Best regards,  
Jung-Jen Hsu  
On behalf of all authors

Author Response File: Author Response.docx