Chamberlin, A.; Gerber, A.; Palmer, M.; Goodale, T.; Gundi, N.D.; Chakraborty, K.; Roy, S.
Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs. J. Low Power Electron. Appl. 2024, 14, 4.
https://doi.org/10.3390/jlpea14010004
AMA Style
Chamberlin A, Gerber A, Palmer M, Goodale T, Gundi ND, Chakraborty K, Roy S.
Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs. Journal of Low Power Electronics and Applications. 2024; 14(1):4.
https://doi.org/10.3390/jlpea14010004
Chicago/Turabian Style
Chamberlin, Andrew, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty, and Sanghamitra Roy.
2024. "Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs" Journal of Low Power Electronics and Applications 14, no. 1: 4.
https://doi.org/10.3390/jlpea14010004
APA Style
Chamberlin, A., Gerber, A., Palmer, M., Goodale, T., Gundi, N. D., Chakraborty, K., & Roy, S.
(2024). Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs. Journal of Low Power Electronics and Applications, 14(1), 4.
https://doi.org/10.3390/jlpea14010004
