A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design
, Kuang-Po Hsueh 2, Zhen-Jie Hong 1, Kuan-Ting Lin 1, Yao-Tsung Tsai 3 and Hsien-Chin Chiu 4Round 1
Reviewer 1 Report
The self-aligned device structure to improve reliability was interested. And, simulation methodology was reasonable. But, the most important figure 7 to confirm device performance and kink effect is not shown. The authors should be resubmit.
Author Response
The self-aligned device structure to improve reliability was interested. And, simulation methodology was reasonable. But, the most important figure 7 to confirm device performance and kink effect is not shown. The authors should be resubmit.
Ans: Thanks for reviewer’s comments. The format of original word file was changed when it is under reviewing process. We have resubmitted it with a proper figure position to avoid this problem happen again.
The authors would like to thanks for the reviewer’s valuable comments.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
How does the phrase "low impact ionization rate" become abbreviated into "IPR"? It does not seem straight forward to understand for general audience.
Electric field does not need to be abbreviated into EF.
In Fig 1, please don't use any abbreviation. It should be self-explanatory without having to find for the meaning of the abbreviation in the text. Also, please include more description in the caption. Please indicate the thickness and dimensions of the layers in the figure.
What is the evidence for the new CES electron path?
Why is the gate covered with oxide/insulator on top and bottom?
Is the Si p- or n-doped?
Please reorganize Fig 5 so that it is much easier to understand. It looks messy now. The labels (a, b and c) should be by the side of the figures.
Fig. 4, 5 and 6 needs more explanation in the captions. Each figure needs to be self-explanatory. The readers must be able to understand the figures just by reading the captions, instead of having to read the text in the entirety.
Fig 7 has been cut. It cannot be seen completely. Please correct this.
Fig 8 cuts the text and needs to be corrected. The font of "Figure 8" seems inconsistent with the others.
Overall, the manuscript looks ok but needs more explanation to precisely describe the effects the the current transistor is able to provide.
Author Response
Reviewer: #2
How does the phrase "low impact ionization rate" become abbreviated into "IPR"? It does not seem straight forward to understand for general audience.
Ans: Thanks for reviewer’s comments. We have changed it with Low-IIR in line 16 to avoid the misunderstanding. All IPR are corrected to IIR in the manuscript.
Electric field does not need to be abbreviated into EF.
Ans: We have corrected it.
In Fig 1, please don't use any abbreviation. It should be self-explanatory without having to find for the meaning of the abbreviation in the text. Also, please include more description in the caption. Please indicate the thickness and dimensions of the layers in the figure.
Ans: We have modified figure 1 based on reviewer’s suggestion.
What is the evidence for the new CES electron path?
Ans: When drain voltage is lower than the gate one, the current path will flow along the gate side channel. The current path will be changed once Vds is higher than Vgs owing to a smaller channel resistance near the top area of field plate. We have added more description in line 63-66 and line 95. The simulated electron current paths with three different drain bias are also shown below. (I am not sure whether the reviewer can obseve the simulated figures here or not. The figures can be observed in the attached pdf file. )
Why is the gate covered with oxide/insulator on top and bottom?
Ans: The oxide below the gate serves as gate oxide, and the insulator above the gate is designed to be the same thickness as the one above the field plate. This design can make the gate electrode and drain one, respectively, metal-connect to their corresponding layer in the subsequent process. We have added more description in line 76-77.
Is the Si p- or n-doped?
Ans: The channel layer is formed by depositing an undoped amorphous silicon layer and then recrystallized to poly-Si by solid-phase crystallization with 24 hours 600 ◦C treatment. The Gate, field plate, and drain/source layers are n+ doped poly-Si. It is illustrated in line 71-73.
Please reorganize Fig 5 so that it is much easier to understand. It looks messy now. The labels (a, b and c) should be by the side of the figures.
Ans: We have modified figure 5. Simulation titles are also added in the sub-figures. Since each sub-figure contains two pictures for comparison, it might cause misunderstanding if we put the label by one side of a figure. We put the label (a, b and c) below each sub-figure. More descriptions are also added along with the labels to enhance the readability of the figures.
Fig. 4, 5 and 6 needs more explanation in the captions. Each figure needs to be self-explanatory. The readers must be able to understand the figures just by reading the captions, instead of having to read the text in the entirety.
Ans: Thanks for reviewer’s comments. More explanations are added in the figure captions. Simulation titles are also added in all figures.
Fig 7 has been cut. It cannot be seen completely. Please correct this.
Ans: The format of original word file was changed when it is under reviewing process. We have modified it with a proper figure position to avoid this problem happen again.
Fig 8 cuts the text and needs to be corrected. The font of "Figure 8" seems inconsistent with the others.
Ans: We have corrected the font of “Figure 8”.
Overall, the manuscript looks ok but needs more explanation to precisely describe the effects the the current transistor is able to provide.
The authors would like to thanks for the reviewer’s valuable comments.
Author Response File: Author Response.pdf
Reviewer 3 Report
In this study, a current and electric field split (CES) TFT structure is proposed to decrease problems caused by impact ionization, and its high performance due to suppressed impact ionization is demonstrated. This is very important study for developing advanced system-on-panels. This paper will attract many readers of this journal.
The reviewer recommends minor revision.
To remove slight confusion of readers, please clarify that the data shown in Figures 7 and 8 were obtained by not simulation but experiments.
Author Response
In this study, a current and electric field split (CES) TFT structure is proposed to decrease problems caused by impact ionization, and its high performance due to suppressed impact ionization is demonstrated. This is very important study for developing advanced system-on-panels. This paper will attract many readers of this journal.
The reviewer recommends minor revision.
To remove slight confusion of readers, please clarify that the data shown in Figures 7 and 8 were obtained by not simulation but experiments.
Ans: Thanks for reviewer’s comments. We have added more description in line 115, 126 and figure captions to describe those figures are obtained by experiments.
The authors would like to thanks for the reviewer’s valuable comments.
Author Response File: Author Response.pdf
