Comparison of Various Factors Affected TID Tolerance in FinFET and Nanowire FET

Abstract

Analysis of the radiation effects in a device is of great importance. The gate all around (GAA) structure that contributes to device scaling not only solves the short channel effects (SCE) problem but also makes the device more resistant in radiation environments. In this article, the total ionizing dose (TID) simulation of nanowire FET (NW) and FinFET was performed. Both these devices were compared and analyzed in terms of the shift of threshold voltage (V_T). The channel insulator was composed of two materials, SiO₂ and HfO₂. To improve the accuracy of the simulation, the interfacial trap parameter of SiO₂ and HfO₂ was applied. Based on the simulation result, the NW with a larger oxide area and larger gate controllability showed less V_T shift than that of the FinFET. It was therefore proved that NW had better TID resistance characteristics in a radiation environment. The gate controllability was found to affect the TID effect more than the oxide area. In addition, we analyzed the manner in which the TID effect changed depending on the V_DD and channel doping.

1. Introduction

The effects of the total ionizing dose (TID) on electronic devices are critical issues in various fields such as space and nuclear applications. To reduce the radiation effects on the electronic components, three radiation hardening methods have been widely considered: radiation hardening by process (RHBP), radiation hardening by shielding (RHBS), and radiation hardening by design (RHBD) [1,2,3,4]. The international thermonuclear experimental reactor (ITER) studies the TID effect for the development of a precise remote control system [5]. Electronic equipment operating in a radiation environment is subject to radiations that lead to defects in transistors. The TID effects, single event effects (SEEs), and displacement damage (DD) can lead to disturbances in the reliable operation of semiconductor devices due to radiation [6,7,8,9,10]. In particular, in the TID effect, the trapped holes in the oxide of transistor in the electron hole pairs (EHP) are caused by radiation and change in the threshold voltage (V_T) [11]. The hole trapped in the oxide results in the inversion charge of the channel region and leads to change in V_T. In particular, nanoscale devices can affect other static and dynamic parameters [12]. Therefore, the reliability of the device is degraded. The devices with a 3D gate structure can solve the SCE problem and enable continuous scaling [13,14,15]. In particular, FinFET, which has a tri-gate structure, and NW, which has a gate all around (GAA) structure, are being studied as effective solutions for device miniaturization [16]. Therefore, both structures devices must be studied for mitigating the radiation effects. In this paper, the TID simulation of NW and FinFET was used to analyze that received more of the TID effect, depending on the structural part of the device. The experiments were performed considering the oxide area and gate controllability, which are the structural elements affected by the TID effect. For a more accurate comparison, the TID simulation was performed by calibrating the size and current level of the NW and FinFET. Through these experiments, compared to the FinFET, we observed that the V_T of the NW changed insignificantly and that this device was more resistant in the radiation environment. This result shows that gate controllability is more effective for causing radiation tolerance than the oxide area. However, the oxide area of the hole trap is a key factor in the TID effect. As the oxide area increases, the number of trapped holes also increases and consequently, the reliability of the device is further degraded. However, by introducing the GAA structure, the gate controllability can be improved to suppressing the TID effect in the oxide area. In addition, the TID characteristics were confirmed by changing the V_DD and channel doping, which affect the resistance to the TID effect. Therefore, the importance of improving gate controllability, which is a method of suppressing the TID effect, is herein presented.

2. Simulation Methodology

2.1. Design Structure for TID Simulation

Prior to the simulation, the NW was stacked in five stages to match the current level and device size.

Table 1. Design specifications of the FinFET and 5ch-NW.

Condition Factor	FinFET	5ch-NW
S/D Doping	1 × 1021 (cm−3)	1 × 1021 (cm−3)
Channel Doping	1 × 1016 (cm−3)	1 × 1016 (cm−3)
EOT	0.812 (nm)	0.812 (nm)
Tfin, Dnw/Lg	6/12 (nm)	6/12 (nm)
Hfin, Hnw	42 (nm)	30 (nm)
Total area (HfO2 + SiO2 + Silicon)	489.5 (nm2)	474.9 (nm2)
Oxide area (HfO2 + SiO2)	237.5 (nm2)	333.6 (nm2)
Parameter explanation
Tfin: FinFET’s width	Dnw: 5ch-NW’s diameter
Lg: channel length	Hfin: FinFET’s height
Hnw: 5ch-NW’s total height

presents the basic physical device parameters used in this study. With the use of a 3D technology computer-aided design (TCAD) simulation tool, the FinFET and 5ch-NW were similarly constructed (Table 1). T_fin is the FinFET width, D_nw is the 5ch-NW diameter, L_g is the channel length, H_fin is the FinFET height, and H_nw is the 5ch-NW’s total height. In addition, the FinFET was manufactured by referring to the International Technology Roadmap for Semi-conductors (ITRS) [17]. Figure 1 shows the TCAD structure of the FinFET and 5ch-NW.

The electrodes of the devices were made of tungsten, the body of silicon, the p-type doping was boron, and the n-type doping was phosphorus. The devices placed SiO₂ (0.5 nm, k = 3.9) and HfO₂ (2 nm, k = 25) on the FinFET and 5ch-NW channel insulator material. The equivalent oxide thickness (EOT) can be calculated using Equation (1).

$$\mathrm{EOT}=\frac{({\mathrm{SiO}}_2 k)}{\left(\mathrm{High} k\right)}\left(T_{Hi-k}\right)$$

(1)

The electrical properties were also calibrated for a fair comparison of the TID effects. Figure 2 shows the I_D-V_G characteristics with the FinFET and 5ch-NW and demonstrates that the electrical characteristics of FinFET and 5ch-NW were calibrated.

2.2. TID Simulation of Various Factors

The TID simulation used the Silvaco victory device software [18]. The Klaassen model used in the simulation reflects various parameters such as electron and hole mobility, trap parameters, and recombination parameters [19,20,21,22,23]. The trap-detrap model parameters in the oxide region by radiation were used in the same way as in [24]. For a more precise simulation, the interfacial trap coefficient between SiO₂ and HfO₂ was calculated by introducing an interfacial trap parameter between the insulators. We generated the corresponding I_D-V_G curves by applying the TID effect. The radiation source was a γ-ray irradiation performed using a Co⁶⁰ source [25]. Radiation was irradiated 1 rad/s for the devices. The input V_DD was equal to 0.65 V and the sweep V_G was in the range 0–0.7 V for the electrical characteristics of 100 Krad, 1 Mrad, 10 Mrad, and 100 Mrad. The simulation confirmed the TID effect on the structural aspects of the FinFET and 5ch-NW. All comparative calculations were performed with the same efficiency as the charge capture [9].

To observe V_DD influence, the V_DD was simulated by varying it from 0.65 V to 0.1 V. The V_T shift amount was compared based on the V_DD in the TID simulation. We applied the V_DD conditions mentioned above to FinFET and 5ch-NW, and the V_G sweep was done in the same way from 0 V to 0.7 V.

The TID characteristics of the two aforementioned devices according to the changed channel doping concentration were confirmed as the channel doping concentration changed. The TID effect change was confirmed by the V_T shift. The channel doping concentration was changed from 1 × 10¹⁶ cm⁻³ to 1 × 10¹⁸ cm⁻³. After changing the channel doping of both the devices, the initial simulation without radiation was compared to the simulation with TID of 10 Mrad.

3. Results and Discussion

Figure 3 shows the basic structure of the FinFET and 5ch-NW as well as the interface hole trap after TID simulation. Figure 3a,b show that the physical thickness and EOT of the insulator were the same. Figure 3c,d show the interface hole traps of the FinFET and 5ch-NW, respectively. The hole traps at the interface between SiO₂ and HfO₂ was confirmed to improve simulation accuracy. Figure 3c,d also show that the hole-trapped interface between Si and SiO₂.

TID is a phenomenon generated because of the accumulation of radiation irradiated to the device. When the radiation penetrates through the insulator region of a device, EHP is generated through the ionization process. Due to their difference in mobility, the generated electrons rapidly diffuse out from the dielectric region. However, some holes are captured in the insulator region trap sites, thereby increasing the leakage current and causing a negative V_T shift [26,27].

Figure 4 illustrates the TID simulation method. In Figure 4a, V_G according to the transient time takes the shape of a pulse. The I_D-V_G curve changes depending on if the pulse is rise or down. In this figure, we can see the upsweep when the purse is rising. Additionally, we can see the downsweep when the purse is going down. The width of the pulse is related to the amount of dose. We can see the simulation results when the pulse is end. The results show the V_T shift and that means the hole is trapped in the interface.

Figure 5 shows the electrical characteristics of the device with the TID effects for each radiation level. We extracted the V_T when the drain current was 1 × 10⁻⁷ [A] using the current constant method in Figure 5. It shows that the V_T shifted because the holes generated by the radiation were trapped in the insulator. Therefore, the shift tendency increases with the increase in the TID. In Figure 5, relatively low levels of radiation did not affect the transfer characteristics. Due to the nanoscale oxide area, the hole trap caused by the radiation was reduced. Additionally, the GAA structure increased the gate holding power and reduced the effect of the trapped charge.

Figure 5c,d show the log scale of I_D-V_G where the off current increase phenomenon, caused by the TID effects, was confirmed. In the figure, we can see that the off current change of 5ch-NW was less than that of FinFET. This shows that the effect of suppressing the SCE also suppressed the TID effects.

Table 2. V_T data of each device according to the amount of TID.

VDD = 0.65 V	FinFET (VT)	5ch-NW (VT)
Initial	329 mV	402 mV
100 k (rad)	325 mV	402 mV
1 M (rad)	323 mV	400 mV
10 M (rad)	312 mV	388 mV
100 M (rad)	281 mV	360 mV

presents the V_T value for each TID amount of both the FinFET and 5ch-NW.

Figure 5e,f show the transconductance of the FinFET and 5ch-NW. It can be noticed that the transconductance increases with radiation, as shown in Figure 5e,f, because of the decrease of V_T and the flow of more drain current at the same gate voltage.

Figure 6 shows the details the V_T shift for each device. In the case of FinFET, a 48 mV shift from 100 Mrad than the initial was observed. In the case of the 5ch-NW, roughly 42 mV shift from 100 Mrad than the initial was observed. The 5ch-NW therefore showed less V_T shifts than the FinFET, as per the simulation results.

The 5ch-NW had a larger oxide area than the FinFET. Therefore, it was reflected to have a greater TID effect and a larger V_T shift. However, these were less in the case of the 5ch-NW because of superior gate controllability. The GAA structure improved the gate controllability because all the sides are covered with the gate. This does not only address SCE, but also improves tolerance to the TID effect [28]. Structurally, the oxide area of 5ch-NW was approximately 96.1 nm², which is larger than that in FinFET. However, the TID effect in 5ch-NW was less than that in FinFET in the above-mentioned experiment. Therefore, it shows that the gate controllability factor is more crucial than the oxide area in TID effect suppression.

Figure 7 depicts a graph of the TID simulation result with V_DD set at 0.1 V and 0.65 V. In Figure 7c, at higher radiation, the V_T shifts significantly than in the case of lower radiation because of the hole traps in the FinFET and 5ch-NW. Additionally, because of the strong TID effect, the FinFET and 5ch-NW are less affected by V_DD at the higher radiation. However, the FinFET is affected by V_DD when low radiation is applied, because the gate controllability of the FinFET is weaker than that of the 5ch-NW. Therefore, the 5ch-NW is not significantly affected by V_DD.

Table 3. V_T shift according to the V_DD variation.

	FinFET (ΔVT)		5ch-NW (ΔVT)
	VDD = 0.1 V	VDD = 0.65 V	VDD = 0.1 V	VDD = 0.65 V
100 k (rad)	1 mV	4 mV	0 mV	0 mV
1 M (rad)	3 mV	6 mV	2 mV	2 mV
5 M (rad)	11 mV	12 mV	6 mV	6 mV
10 M (rad)	17 mV	17 mV	14 mV	14 mV

lists the V_T shift according to the variation of V_DD. In the case of 5ch-NW, there was almost no change owing to its better gate controllability, which reduced the V_DD influence.

Figure 8 shows that the I_D-V_G changed due to the TID effect. Figure 8a shows the I_D-V_G of the FinFET, and Figure 8b shows the I_D-V_G of the 5ch-NW. We can see that the V_T changed and how it was different if the channel doping was changed. First, the V_T decreased due to the TID effect, and the V_T decreased on the same way when the channel doping was changed. In the case of channel doping at 1 × 10¹⁶ cm⁻³, it was confirmed that the V_T variation due to the TID effect was similar to the V_T variation at 1 × 10¹⁸ cm⁻³. Therefore, the V_T increased when the channel doping increased in both the FinFET and 5ch-NW, and the V_T decreased due to the TID effect at both 1 × 10¹⁶ cm⁻³ and 1 × 10¹⁸ cm⁻³.

Table 4. V_T variation according to the channel doping.

	FinFET (ΔVT)		5ch-NW (ΔVT)
Channel doping	1 × 1016 cm−3	1 × 1018 cm−3	1 × 1016 cm−3	1 × 1018 cm−3
Initial	329 mV	345 mV	402 mV	411 mV
10 Mrad	312 mV	329 mV	388 mV	398 mV
ΔVT (%)	5.16%	4.63%	3.48%	3.16%

lists the V_T variation based on channel doping. The doping of the FinFET changed from 1 × 10¹⁶ cm⁻³ to 1 × 10¹⁸ cm⁻³, and that of the 5ch-NW was also changed in a similar way. Increasing channel doping in FinFET and 5ch-NW caused an increase in the initial V_T. In addition, when radiation was applied, the V_T and the TID effect decreased for all cases, regardless of doping. When the doping was changed to 1 × 10¹⁸ cm⁻³, the change in V_T was less in the 5ch-NW than that in the FinFET as less of the interface and oxide traps were generated in the case of the former [29]. As channel doping increased, 10 M radiation appears to have significantly reduce V_T, however, this can only attributed to the increase in the absolute value of the initial amount. In fact, very silght difference was observed when calculating the percentage variation of the aforementioned amount. As presented in Table 4, the V_T variation percentage was found to be similar between the channel doping of 1 × 10¹⁶ cm⁻³ and 1 × 10¹⁸ cm⁻³ for both the FinFET and 5ch-NW. Thus, channel doping had little or no influence on the TID effect in the FinFET and 5ch-NW.

4. Conclusions

In this paper, we found that the 5ch-NW GAA devices exhibited less ionizing radiation sensitivity when compared to the FinFET device. Structurally, the 5ch-NW device had an oxide area of approximately 96.1 nm², which is larger than that of the FinFET. However, in our experiment, the TID effect of 5ch-NW was observed to be less than that of the FinFET. It was shown that the gate controllability factor is more crucial to the suppression of the TID effect than the oxide area. The GAA structure, which has larger gate controllability, confirmed that the TID effect problem can be effectively resolved. The GAA structure and high-k dielectric materials have to be introduced to improve gate controllability. Furthermore, the 5ch-NW was not found to be affected by V_DD. However, the FinFET was affected by V_DD when low radiation was applied. Therefore, devices with strong gate controllability were not affected by TID and channel doping had little or no influence on the TID effect.