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Open AccessArticle

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

1
Department of Computer Science and Engineering, Chungnam National University, Daejeon 34134, Korea
2
The 2nd R&D Institute, Agency for Defence Development (ADD), Seoul 138110, Korea
3
The Division of Computer Convergence, Chungnam National University, Daejeon 34134, Korea
*
Author to whom correspondence should be addressed.
Appl. Sci. 2020, 10(7), 2464; https://doi.org/10.3390/app10072464
Received: 25 February 2020 / Revised: 26 March 2020 / Accepted: 30 March 2020 / Published: 3 April 2020
(This article belongs to the Special Issue Operating System Issues in Emerging Systems and Applications)
Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model. View Full-Text
Keywords: avionics systems; real-time system; execution model; multicore architecture; interference analysis avionics systems; real-time system; execution model; multicore architecture; interference analysis
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Park, S.; Kwon, M.-Y.; Kim, H.-K.; Kim, H. Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS. Appl. Sci. 2020, 10, 2464.

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