# Comparison of Interleaved Boost Converter and Two-Phase Boost Converter Characteristics for Three-Level Inverters

^{1}

^{2}

^{3}

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## Abstract

**:**

## 1. Introduction

## 2. Circuit Configuration

#### 2.1. Interleaving Scheme

_{p}and D

_{n}are the duty ratios given to the switches (S

_{1}and S

_{2}) in Figure 1 and Figure 2, respectively. Figure 3a shows the case where D ≤ 0.5 and Figure 3b shows the case where D > 0.5. As shown in Figure 3a, the controller modulates the command value using two carriers f

_{c1}and f

_{c2}with a phase difference of 180 degrees to generate the gate signals for the switches. Here, each switch, carrier, and duty ratio correspond to f

_{c1}and D

_{p}for S

_{1}, and f

_{c2}and D

_{n}for S

_{2}, respectively. Due to the interleaving method, the frequency of the input current ripple is twice the carrier frequency.

#### 2.2. Switching Modes

_{1}and S

_{2}are on, MODE2 in Figure 4b and Figure 5b is a mode in which both S

_{1}and S

_{2}are off, MODE3 in Figure 4c and Figure 5c is a mode in which S

_{1}is off and S

_{2}is on, and MODE4 in Figure 4d and Figure 5d is a mode in which S

_{1}is on and S

_{2}is off. For D > 0.5 in Figure 3b, magnetic energy is stored in both reactors with MODE 1 in Figure 4a and Figure 5a and boosted with MODE 3 in Figure 4c and Figure 5c and MODE 4 in Figure 4d and Figure 5d alternately. The upper and lower capacitor voltages (v

_{cp}, v

_{cn}) of the series circuit are controlled separately by charging the upper capacitor with MODE 3 in Figure 5c and the lower capacitor with MODE 4 in Figure 5d.

## 3. Input Current Ripple Analysis

_{L}of the input current i

_{L}for both circuits. As the operating mode of the input current, this chapter assumes a current continuous mode. For simplicity of analysis, each phase of the parallel circuit and the upper and lower of the series circuit are symmetrical. Each inductance value and duty ratio of the two switches are also the same. In other words, this chapter is analyzed with L

_{1}= L

_{2}= L and D

_{p}= D

_{n}= D. This chapter also discusses the input current ripple considering the rated current of the reactor.

#### 3.1. Input Current Ripple in Parallel Circuits

_{L}is the sum of each reactor current ripple Δi

_{L}

_{1}and Δi

_{L}

_{2}. Figure 3a shows the gate signal and each reactor current i

_{L}

_{1}and i

_{L}

_{2}when D ≤ 0.5. When both S

_{1}and S

_{2}are off, each reactor current ripple Δi

_{L}

_{1}and Δi

_{L}

_{2}are as follows [7]:

_{L}

_{1}, Δi

_{L}

_{2}> 0 as defined in Figure 3 due to V

_{i}< v

_{dc}.

_{L}becomes their sum, and considering v

_{dc}= V

_{i}/(1 − D), the current ripple becomes Equation (3).

_{1}and S

_{2}are on, each reactor current ripple Δi

_{L}

_{1}and Δi

_{L}

_{2}are as in Equation (4).

_{L}is expressed as Equation (5).

#### 3.2. Input Current Ripple in Series Circuits

_{L}is half that of one phase in a parallel circuit. In other words, the current ripple is half of Equation (1) when D ≤ 0.5. Moreover, when v

_{dc}= V

_{i}/(1 − D) is taken into account, Equation (6) is obtained.

^{2}). If the inductance value of the series circuit is set to one-quarter of the parallel circuit, the input current ripple of the two circuits will be equal.

## 4. Output Voltage Control

#### 4.1. PI Control

_{L}

_{1}, i

_{L}

_{2}) and output voltage (v

_{dc}) are obtained by sensors, and the deviation between the voltage command value and the actual voltage is input to the PI controller to obtain the input current command. The deviation between the current command value and the actual current is then input to the PI controller to calculate the duty ratio of the boost converter, which is modulated by a carrier wave to generate a gate signal. In Figure 7, the capacitor voltages (v

_{cp}, v

_{cn}) and reactor current (i

_{L}) are obtained by sensors, and the duty ratio is calculated as in Figure 6. The difference between Figure 6 and Figure 7 is that a control system for the neutral point potential (NPP) is added to control the balance between the upper and lower capacitor voltages. Neutral point potential v

_{n}is defined as the following equation:

_{n}* = 0. The current PI controller outputs v

_{dc_ref}so that D

_{p}equals D

_{n}when the neutral point potential is 0 V. The NPP PI controller outputs v

_{n_ref}according to the error of the neutral point potential from the command value to realize the balance control. Defining the difference between D

_{p}and D

_{n}as D’= D

_{p}− D

_{n}, the NPP PI controller corrects D

_{n}with D’ when the neutral point potential varies.

#### 4.2. Output Voltage Control Using Optimal Regulator

_{1}= (D

_{p}+ D

_{n}− 1) T for MODE1, T

_{3}= (1 − D

_{p}) T for MODE3, and T

_{4}= (1 − D

_{n}) T for MODE4, for D > 0.5 shown in Figure 3b.

**u**(t)≔ V

_{i}, $\overline{{D}_{p}}$ = 1 − D

_{p}, $\overline{{D}_{n}}$ = 1 − D

_{n}, C = C

_{p}= C

_{n}, R = R

_{p}= R

_{n}. From Equations (9)–(12), the state Equation (9) is a nonlinear system. In this paper, the state equation is designed to be linearized around the equilibrium point. The equilibrium point is set as

**x**(t) =

**X**,

**u**(t) =

**U**. Assuming that the variation in the equilibrium point is sufficiently slower than the carrier period, a small signal model is obtained as follows:

_{cp}and v

_{cn}are able to follow the step response. The state equation of the expanded system with additional state variable

**ω**(t), which is the integral of the deviation

**e**(t) between the controlled variables v

_{cp}, v

_{cn}and their reference values, is expressed as the following equations:

**K**and

**G**in Equation (23). The evaluation function is expressed as the following:

**Q**is the weight coefficient matrix for each state variable and

**R**is the weight coefficient matrix for the magnitude of the control input.

## 5. Experimental Verification

#### 5.1. PI Control Design

#### 5.2. Optimal Regulator Design

**Q**and

**R**of the LQR are set as

**Q**= diag [q

_{1}, q

_{2}, q

_{3}, q

_{4,}q

_{5}] and

**R**= diag [r

_{1}, r

_{2}], in which diag denotes the diagonal matrix. Each coefficient corresponds to q

_{1}:i

_{L}, q

_{2}:v

_{cp}, q

_{3}:v

_{cn}, q

_{4}:Δv

_{cp}, q

_{5}:Δv

_{cn}, r

_{1}:$\overline{{D}_{p}}$, r

_{2}:$\overline{{D}_{n}}$.

**R**= diag [1, 1]. Comparing Figure 10a,b, it can be seen that the larger the weight on the deviation, the faster the response. Comparing Figure 10c,d, it can be seen that the response can be made faster by increasing the weight of Δv

_{cn}. Simulated results show that the desired response can be obtained when Figure 10e is used. For gain calculation, the “Arimoto-Potter method” is used. Table 3 shows the gains designed.

#### 5.3. Boost Operation and Neutral Point Potential Control Characteristics

#### 5.4. Input Current Ripple Characteristics

_{p}= R

_{n}= 50 Ω). Figure 12 and Figure 13 show the input current ripple of the parallel and series circuits, respectively. These are the results obtained by open-loop control for the duty ratios of 0.3, 0.5, and 0.6, respectively. When D = 0.3 and 0.6, the input current ripple of the series circuit is approximately one-quarter that of the parallel circuit. Figure 14 and Figure 15 show the simulated results of the input current for the same load condition. It can be seen that the simulation and experimental results are in good agreement for D = 0.5 and D = 0.6. Comparing Figure 12a and Figure 14a in the case of D = 0.3, there is a difference between them. It can be mainly attributed to the effect of the turn on and turn off time in the experiment. Figure 16 shows a comparison of the theoretical, simulated, and experimental results for the input current ripple. In the experimental results, the duty ratio was set to a maximum of 0.65 due to the limitation of the rated voltage of the experiment equipment. As shown in Figure 16, the input current ripple of the series circuit is one-quarter that of the parallel circuit.

#### 5.5. Output Voltage Response Characteristics

#### 5.6. Efficiency Characteristics

_{L}described in Section 5.4. The difference between the input current ripple ∆i

_{L}of the two circuits becomes large when the duty ratio is greater than 0.5. The input current ripple ∆i

_{L}of the parallel circuit is larger than that of the series circuit. Therefore, as shown in Figure 20, the efficiency of the parallel circuit decreases largely due to increased switching losses.

## 6. Conclusions

- The series circuit is capable of both boosting and neutral potential control by means of a boost converter connected in a dependent manner, and is effective for use in a three-level inverter.
- A theoretical analysis of the input current ripple of the series circuit was performed. The validity of the analysis was demonstrated by experiments and simulations using an experimental apparatus with an output voltage of 280 V.
- When the inductances of the series circuit and the parallel circuit are equal, the input current ripple of the series circuit is one-quarter that of the parallel circuit.
- When the inductance of the series circuit is one-quarter of the parallel circuit and the volume and weight of both circuits are equal, the input current ripple of the two circuits are equal.
- As an output voltage control method for the series circuit, a control method using an optimal regulator was proposed, and a design method using the state averaging method is presented. The proposed optimal regulator has a better load regulation response than the general PI control method, suggesting that it is effective in downsizing the smoothing capacitor.
- The series circuit has higher conversion efficiency in the light load, high voltage region than the parallel circuit, and is suitable for operation in this region.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 10.**Simulated results for weight coefficients design. (

**a**) Q = diag([1,1,1,1,1]); (

**b**) Q = diag([1,1,1,100,100]); (

**c**) Q = diag([5,5,5,100,100]); (

**d**) Q = diag([5,5,5,100,1000]); (

**e**) Q = diag([5,5,2,100,1000]); (

**f**) Q = diag([5,5,10,100,1000]).

**Figure 12.**Experimental results of input current ripple characteristics of parallel circuit. (

**a**) D = 0.3; (

**b**) D = 0.5; (

**c**) D = 0.6.

**Figure 13.**Experimental results of input current ripple characteristics of series circuit. (

**a**) D = 0.3; (

**b**) D = 0.5; (

**c**) D = 0.6.

**Figure 14.**Simulated results of input current ripple characteristics of parallel circuit. (

**a**) D=0.3; (

**b**) D = 0.5; (

**c**) D = 0.6.

**Figure 15.**Simulated results of input current ripple characteristics of series circuit. (

**a**) D = 0.3; (

**b**) D = 0.5; (

**c**) D = 0.6.

Input voltage V_{i} | 100 V |

Carrier frequency f_{c1}, f_{c2} | 10 kHz |

IGBT | FGH40T120SMD |

rated voltage | 1200 V |

rated current | 40 A |

Diode | FEP16DT |

rated voltage | 600 V |

rated current | 16 A |

DC reactor | - |

inductance L_{1}, L_{2} | 1.8 mH |

rated current | 9 A |

core | silicon steel plate |

resistance | 68.6 mΩ |

Capacitanc C_{p},C_{n} | 1500 uF |

Parameter | Value |
---|---|

K_{pi} | 4 |

T_{ii} | 4 ms |

K_{pv} | 0.075 |

T_{iv} | 40 ms |

K_{pn} | 2 |

T_{in} | 0.1s |

Feedback Gain | |||
---|---|---|---|

K_{1} | −0.028 | K_{6} | 1.310 |

K_{2} | −1.060 | G_{1} | 8.072 |

K_{3} | 0.744 | G_{2} | 0.886 |

K_{4} | 0.133 | G_{3} | −56.322 |

K_{5} | 3.302 | G_{4} | −45.360 |

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## Share and Cite

**MDPI and ACS Style**

Sakasegawa, E.; Chishiki, R.; Sedutsu, R.; Soeda, T.; Haga, H.; Kennel, R.M.
Comparison of Interleaved Boost Converter and Two-Phase Boost Converter Characteristics for Three-Level Inverters. *World Electr. Veh. J.* **2023**, *14*, 7.
https://doi.org/10.3390/wevj14010007

**AMA Style**

Sakasegawa E, Chishiki R, Sedutsu R, Soeda T, Haga H, Kennel RM.
Comparison of Interleaved Boost Converter and Two-Phase Boost Converter Characteristics for Three-Level Inverters. *World Electric Vehicle Journal*. 2023; 14(1):7.
https://doi.org/10.3390/wevj14010007

**Chicago/Turabian Style**

Sakasegawa, Eiichi, Rin Chishiki, Rintarou Sedutsu, Takumi Soeda, Hitoshi Haga, and Ralph Mario Kennel.
2023. "Comparison of Interleaved Boost Converter and Two-Phase Boost Converter Characteristics for Three-Level Inverters" *World Electric Vehicle Journal* 14, no. 1: 7.
https://doi.org/10.3390/wevj14010007