# A Comparison of Modulation Techniques for Modular Multilevel Converters

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Modular Multilevel Converter

_{MMC}. The Direct-Current bus (DC-bus) voltage (U

_{DC}) is equally distributed between all SMs, being the SM’s DC voltages, V

_{c}, equal to:

_{SM}. When S = 1, V

_{SM}= V

_{c}. If S = 0, V

_{SM}= 0 V. Therefore, the converter output voltages can take n + 1 voltage levels. Adding a new SM per arm increases in two voltage levels the possible values of the output. Half H-bridge topology is the most common SM [5], although there are other SM topologies that provide more output levels at the price of increasing the number of components, e.g., full H-bridge, multilevel Neutral Point Clamped (NPC) or Flying Capacitors (FC) cells [18].

## 3. Modulation Strategies under Study

#### 3.1. PS-SPWM

_{x}with x = 1, …, 5, for a single phase. The phase shift between the five carriers, VC

_{x}, is θ = 72°. The output waveform is the sum of all the signals.

#### 3.2. SVM

^{3}switching states and 6 × (n − 1)

^{2}triangles in the space vector diagram [23]. Figure 3 shows the space vector diagram for a six-level converter.

_{ul}and V

_{lu}are always two of the three closest vectors. The third vector is chosen according to:

_{ll}, the duty cycles are computed as:

_{uu}, then:

_{ul}, V

_{lu}, V

_{uu}or V

_{ll}).

#### 3.3. NLM

_{ref}is the desired output voltage included between the voltage levels V

_{N}and V

_{N}

_{−1}and d is the duty cycle. The duty cycle d, of each phase are obtained as:

#### 3.4. Comparison Simulation Results

#### 3.5. SM Voltage

_{Threshold}.

#### 3.6. Circulating Current

## 4. Generated Harmonic Content

_{a}, is defined as the value of the fundamental voltage harmonic, V

_{fund}, divided by the value of the reference signal, V

_{ref}:

_{f}. In the case of the PS-SPWM, r

_{f}relates the carrier frequency, f

_{cr}, and the frequency of the modulating signal, f

_{ref}, as:

_{f}is defined as the switching frequency, f

_{sw}, used to rotate between the three vectors in the SVM or to switch between the two voltage levels in the NLM, divided by the modulating signal frequency, f

_{ref}:

_{a}. The harmonics with the highest amplitude are generated at r

_{f}± 2 and r

_{f}± 4.

_{a}increases, the difference between modulation techniques is lower.

## 5. Experimental Results

#### 5.1. PS-SPWM

_{crs}).

#### 5.2. SVM

_{ll}or V

_{uu}, is chosen from (4). The duty cycles are obtained using V

_{ab}and V

_{bc}voltage reference signals and the three aforementioned voltage vectors by using (5) and (6).

#### 5.3. NLM

_{ref}) which is both upper rounded (V

_{N}) and lower rounded (V

_{N}

_{−1}) to the next nearest integer voltage level. The duty cycle is obtained from the voltage reference signal and its rounded value and (10).

_{N}and V

_{N}

_{−1}. The range of the signal is (0, 1), thus, it can be directly compared with the duty cycle and therefore the right voltage level is generated. Finally, the gate signals are generated depending on the amplitude of V

_{N}and V

_{N}

_{−1}. As in the previous case, a circular array is also used to distribute the switching losses. Figure 21 illustrates the NLM full control diagram. In the same way as in PS-SPWM, six blocks are necessary to generate the PWM master signals. Then, they are modified by the capacitor voltage balancing algorithm and inverted by the dead-time controller in order to obtain all the PWM signals which are then applied to the IGBTs.

#### 5.4. Comparison of the Modulation Methods

## 6. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

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**Figure 1.**(

**a**) Diagram of the modular multilevel converter (MMC); (

**b**) Diagram of the half H-bridge submodules (SM).

**Figure 4.**Graphic representation of fast SVM proposed in [14].

**Figure 7.**(

**a**) SPWM waveform; (

**b**) SVM waveform; (

**c**) NLM waveform. (Blue line: Normalized reference output. Red line: Normalized output waveform).

**Figure 25.**PS-SPWM operation with a 2 kW load. (

**a**) line-to-line output voltages and (

**b**) output currents.

**Figure 26.**SVM operation with a 2 kW load. (

**a**) line-to-line output voltages and (

**b**) output currents.

**Figure 27.**NLM operation with a 2 kW load. (

**a**) line-to-line output voltages and (

**b**) output currents.

Modulation Technique | N° Switching |
---|---|

PS-SPWM | 30 |

SVM | 48 |

NLM | 60 |

Parameter | Value |
---|---|

Nominal Power | 50 kVA |

Nominal Voltage | 400 V |

N° submodules per phase | 10 |

Submodule Capacitor | 2200 µF |

IGBT | SKM145GB066D |

IGBT Driver | Skyper 32 R UL |

DC-bus voltage | 1200 V |

MMC inductor | 0.5 mH |

Grid inductor | 5 mH |

Modulation Technique | Used FPGA Resources | |||
---|---|---|---|---|

LUTs | Flip-Flops | |||

PS-SPWM | 315 | 0.59% | 94 | 0.08% |

SVM | 992 | 1.86% | 482 | 0.45% |

NLM | 762 | 1.43% | 349 | 0.32% |

Modulation | THD |
---|---|

PS-SPWM | 1.70% |

SVM | 1.42% |

NLM | 1.51% |

© 2016 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC-BY) license (http://creativecommons.org/licenses/by/4.0/).

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**MDPI and ACS Style**

Moranchel, M.; Huerta, F.; Sanz, I.; Bueno, E.; Rodríguez, F.J.
A Comparison of Modulation Techniques for Modular Multilevel Converters. *Energies* **2016**, *9*, 1091.
https://doi.org/10.3390/en9121091

**AMA Style**

Moranchel M, Huerta F, Sanz I, Bueno E, Rodríguez FJ.
A Comparison of Modulation Techniques for Modular Multilevel Converters. *Energies*. 2016; 9(12):1091.
https://doi.org/10.3390/en9121091

**Chicago/Turabian Style**

Moranchel, Miguel, Francisco Huerta, Inés Sanz, Emilio Bueno, and Francisco J. Rodríguez.
2016. "A Comparison of Modulation Techniques for Modular Multilevel Converters" *Energies* 9, no. 12: 1091.
https://doi.org/10.3390/en9121091