13-Level Single-Source Switched-Capacitor Boost Multilevel Inverter

Abstract

Transformerless inverters (TIs) are becoming increasingly popular in solar photovoltaic (PV) applications due to their enhanced efficiency and cost-effectiveness. Unlike transformer-based inverters, TIs, which lack transformers and additional components, offer significant advantages in terms of reduced weight, compactness, and lower costs. Research studies have demonstrated that multilevel TIs can achieve lower total harmonic distortion (THD), reduced switching stresses, and higher AC output voltage levels suitable for high voltage applications. However, achieving these outcomes simultaneously with maximum power ratings and the lowest switching frequencies poses a challenge for TI topologies. In light of these challenges, this research proposes the implementation of a 13-level single-source switched-capacitor boost multilevel inverter (SSCBMLI) designed for solar PV systems. The SSCBMLI consists of a single DC power source, switched-capacitor (SC) units, and a full H-bridge. Compared to other existing 13-level multilevel inverter (MLI) configurations, the proposed SSCBMLI utilizes the fewest components to minimize development costs. Moreover, the SSCBMLI offers voltage boosting and can drive high inductive loads, self-voltage-balanced capacitors, an adaptable topology structure, and reliable system performance. Simulations and experimental tests are conducted using PLECS 4.5 and SIMULINK to assess the performance of the proposed SSCBMLI under varying modulation indices, source powers, and loads. A comparative analysis is then conducted to evaluate the SSCBMLI against existing inverter topologies.

1. Introduction

Solar PV energy stands out as one of the most versatile, accessible, and environmentally friendly renewable energy sources for power generation [1]. The initial high cost associated with PV system implementation has steadily decreased thanks to ongoing advancements in manufacturing and deployment techniques. Recognizing the potential for solar PV systems to become the most reliable and cost-effective energy source, several countries, including China, Germany, India, Japan, and the United States, have made substantial investments in deploying these systems for power generation. As of the end of 2020, the cumulative global installed PV capacity reached an estimated 7604 gigawatts direct current (GWdc), with a minimum of 1394 GWdc installed and commissioned in that year, according to the 2021 snapshot of global PV markets by the International Energy Agency-Photovoltaic Power System Program (IEA-PVPS). In the early days of solar PV systems, DC-AC inverters were commonly connected to the grid using transformers as interfaces to provide galvanic isolation and voltage boosting between the input and output sources [2]. However, incorporating transformers in inverters resulted in drawbacks such as increased size, cost, and weight [3]. Moreover, energy conversion efficiency was compromised, making transformers less desirable as power generation technology continued to evolve towards higher efficiency. Consequently, TIs developed without transformers have gained widespread use in PV applications due to their smaller size, lower cost, and reduced weight.

MLIs, also known as TIs with higher AC output voltage levels, have emerged as essential technology for high-power and medium-voltage regulation. Unlike conventional power electronic inverters that provide AC output voltage switching between only two levels, MLIs can generate desired AC output voltages at higher levels using DC voltage sources like fuel cells, capacitors, and renewable energy sources. The concept of MLIs with three levels was first proposed in 1975, and since then, three fundamental MLI technologies have been introduced, including diode-clamped, flying capacitor (FC), and cascaded H-bridge (CHB) topologies. These MLI types produce nearly sinusoidal output waveforms with lower THD, reduced switching losses, and a greater number of AC output voltage levels [4,5]. However, many high-level MLI configurations rely on a high number of input DC voltage sources and passive and active components, resulting in issues such as voltage imbalance, circuit complexity, low operational efficiency, and increased costs. Additionally, improper control algorithm design for switching states often depends on auxiliary circuits to regulate voltage across DC capacitors, further increasing system costs [6]. Furthermore, many MLI topologies lack extensibility in their structure, limiting their ability to handle higher AC output voltage levels and voltage boosting in various applications.

Recently, SC-MLIs have garnered significant attention in power electronics research to address these issues. They offer DC-DC voltage boosting and high-voltage DC-AC inversion capabilities, making them an attractive choice for various applications. Common SC-MLI topologies feature switching circuits with capacitors, diodes, or power switches, enabling them to generate high-level AC output voltage from the DC-link voltage through a series–parallel switching conversion method. This technique allows DC capacitors to charge and discharge at different switching states, with parallel connections to other voltage sources, such as the input DC voltage and other charged capacitors, providing self-voltage regulation—an invaluable solution for many high-power and high-voltage gain applications.

For instance, a SC cascaded half-bridge MLI with a single DC voltage source was proposed in [7]. Unlike conventional CHB-MLIs that require multiple isolated DC voltage sources, this topology uses SC units to replace the DC voltage sources, with a single DC voltage source dedicated to charging the capacitors. It employs four capacitors, four diodes, and ten switches to achieve a nine-level AC output voltage with a four-fold voltage gain from the input DC voltage source. An additional inductor is included to facilitate smooth capacitor charging, limit fault currents, and reduce electromagnetic interference. Comparative studies have shown that this topology offers higher efficiency due to the use of fewer switches.

Another multi-source SC-MLI topology with a K-type module was proposed in [8]. This topology utilizes two asymmetrical DC voltage sources (1DC and 2DC), two capacitors, and 14 switches to generate a 13-level AC output voltage. This asymmetrical MLI module eliminates the need for additional circuits, such as H-bridge, to create a negative AC output voltage level. Furthermore, the topology can be extended by cascading modules in series to achieve higher AC output voltage levels. However, each cascading connection requires an additional set of devices, which may potentially increase the overall system cost. It is worth noting that this topology is limited to a voltage boosting capability of only two times the input DC voltage source.

Similarly to [8], the topology in [9] is another SC-MLI topology with an asymmetrical DC voltage source. This topology uses one capacitor and three switches fewer than the previous one to produce a 13-level AC output voltage, reducing development costs. However, it lacks module extensibility.

The SC-MLI topology in [10] was proposed based on the packed U-cell (PUC) concept, incorporating optimized sliding-mode control to self-balance capacitor voltage in both stand-alone and grid-connected operations. The research paper primarily focuses on presenting a control technique tailored to the proposed topology, addressing the common challenge of capacitor voltage balancing in PUC-based MLIs. It employs only one capacitor, one DC voltage source, and six switches to generate a 7-level AC output voltage. To minimize THD when connecting the topology to the grid, a grid filter is applied. However, it is important to note that while this topology significantly reduces the number of components, it does require an auxiliary control circuit to handle voltage regulation issues across the capacitors. Additionally, it lacks a voltage boosting feature.

This paper introduces a novel SSCBMLI topology, which offers several advantages compared to recent MLI designs. These benefits stem from a reduced number of components, resulting in lower system losses, a smaller inverter size, and reduced cost. The proposed topology relies on a single DC voltage source to generate a 13-level AC output voltage with high gain, simplifying the control algorithm due to the minimal need for gate signals. Additionally, the topology’s DC capacitors possess self-balancing capabilities, eliminating the need for auxiliary circuits to regulate voltage. Furthermore, this proposed topology’s structure is extendable to provide higher AC output voltage levels and voltage boosting. To validate its performance, a comprehensive analysis and verification of the proposed MLI topology were conducted through simulation and hardware implementation.

2. The Proposed SSCBMLI

The circuit structure of the proposed 13-level SSCBMLI topology is shown in Figure 1. This topology consists of 4 key parts: the single-source cell, the SC cell, the extendable unit, and the H-bridge cell. Specifically, it comprises a sole DC voltage source (i.e., V_dc), two diodes (i.e., D₁ and D₂), three capacitors (i.e., C_u, C_d, and C₁), and 11 switches (i.e., comprising one transistor and 10 insulated gate bipolar transistors (IGBTs), each with an anti-parallel diode).

Figure 1. Circuit structure of the proposed 13-level SSCBMLI.

The H-bridge cell facilitates DC to AC inversion by altering the polarity of the AC output voltage at the load. Its inclusion reduces the number of switches and enhances the extensibility of the SC unit, thereby improving performance. In Figure 1, the SC cell manages the charging and discharging of capacitors (i.e., C_u and C_d) to the DC source voltage V_dc using a parallel connection (i.e., V_cu = V_cd = V_dc). This approach ensures self-voltage balancing across the DC capacitors without requiring an auxiliary voltage-regulation circuit.

2.1. Extensibility of Structure

The extendable unit, depicted in Figure 1, consists of a capacitor, a transistor, and two IGBTs with anti-parallel diodes. To achieve a higher AC output voltage level and greater voltage gain, the extendable unit can be expanded by adding similar units in parallel [11,12]. Figure 2 illustrates an example of the extendable unit structure with n = 1 and n = 2, where the unit is placed between the SC cell and the H-bridge cell.

Figure 2. Extended SC extendable unit structure with n = 1 and n = 2.

The voltage across each additional SC extendable unit capacitor C_n can be controlled to (3)(2ⁿ⁻¹)V_dc. For instance, when n = 1, capacitor C₁ charges to 3V_dc by summing the DC voltage source and SC cell voltages (i.e., V_c1 = V_dc + V_cu + V_cd). When n = 2 (i.e., with two SC extendable units), capacitor C₁ remains charged to 3V_dc, while capacitor C₂ charges to 6V_dc by summing the DC voltage source, the SC cell, and the voltage across C₁ (i.e., V_c2 = V_dc + V_cu + V_cd + V_c1). A crucial component of the extendable unit is the transistor, which enables parallel conduction with series voltage during capacitor charging.

As the number of SC extendable units N_ext increases in the proposed SSCBMLI topology, various parameters change, including diode count N_diode, capacitor count N_capacitor, gate driver count N_gate, switch count N_switch, total component count N_component, voltage boost V_boost, and voltage level N_level, as summarized in Table 1.

Table 1. Value change of parameters with SC extendable units.

Parameters	Vcn
Next	n
Ndiode	2
Ncapacitor	2 + n
Ngate	4 + 2n
Nswitch	8 + 3n
Ncomponent	13 + 4n
Vboost	3 × 2n
Nlevel	(3 × 2n+1) + 1

2.2. Operation, Switching, and Capacitor States

Figure 3 illustrates the detailed circuit operations and conducting paths for achieving voltage levels from 0 to +6V_dc. The red paths indicate capacitor discharging, and green paths represent capacitor charging. The analysis of the proposed model is conducted under ideal and steady-state conditions, assuming the capacitors have sufficient capacitance to maintain a constant voltage. In particular, capacitors C_u and C_d are charged by the DC voltage source V_dc, resulting in potentials V_cu and V_cd equal to V_dc. Capacitor C₁, on the other hand, is charged by V_dc, V_cu, and V_cd, leading to a potential V_c1 equal to the sum of V_dc, V_cu, and V_cd, which is equivalent to 3V_dc. During operation, the capacitors discharge to provide discrete voltage levels when connected in series with the load. Conversely, they are charged when connected to the DC voltage source and other capacitors in parallel. This design enables the proposed SSCBMLI topology to amplify the input voltage source by a factor of six, generating a 13-level AC output voltage when n = 1. It is noteworthy that the capacitor voltage control in the SC cell is achieved using the nearest level control (NLC) technique. This method selects the switching states such that the output voltage closely matches the reference waveform. By ensuring that the required voltage level is generated, the NLC inherently balances the capacitor voltages without requiring complex feedback or additional balancing circuits. This simplifies the control strategy while maintaining the desired output voltage waveform and system efficiency.

Figure 3. The operational states of the proposed SSCBMLI at zero and positive voltage levels.

Table 2 summarizes the switching states and capacitor conditions corresponding to each AC output voltage level, which are discussed below:

Table 2. Switching and capacitor states of the proposed 13-level SSCBMLI topology.

States	S1	S1′	S2	S2′	S3	S3′	S4	S5	S5′	S6	S6′	Cu	Cd	C1	Vout
1	1	0	0	1	0	1	1	1	0	1	0	D	D	C	0
2	0	1	1	0	0	1	0	1	0	0	1	C	C	-	+Vdc
3	0	1	0	1	0	1	0	1	0	0	1	D	C	-	+2Vdc
4	1	0	1	0	0	1	0	1	0	0	1	C	D	-	+2Vdc
5	1	0	0	1	0	1	1	1	0	0	1	D	D	C	+3Vdc
6	0	1	1	0	1	0	0	1	0	0	1	C	C	D	+4Vdc
7	0	1	0	1	1	0	0	1	0	0	1	D	C	D	+5Vdc
8	1	0	1	0	1	0	0	1	0	0	1	C	D	D	+5Vdc
9	1	0	0	1	1	0	0	1	0	0	1	D	D	D	+6Vdc
10	0	1	1	0	0	1	0	0	1	1	0	C	C	-	−Vdc
11	0	1	0	1	0	1	0	0	1	1	0	D	C	-	−2Vdc
12	1	0	1	0	0	1	0	0	1	1	0	C	D	-	−2Vdc
13	1	0	0	1	0	1	1	0	1	1	0	D	D	C	−3Vdc
14	0	1	1	0	1	0	0	0	1	1	0	C	C	D	−4Vdc
15	0	1	0	1	1	0	0	0	1	1	0	D	C	D	−5Vdc
16	1	0	1	0	1	0	0	0	1	1	0	C	D	D	−5Vdc
17	1	0	0	1	1	0	0	0	1	1	0	D	D	D	−6Vdc

0 V: in this state (S₁, S₂′, S₃′, S₄, S₅, and S₆ in operation), C_u and C_d discharge, while C₁ charges from both C_u, C_d, and V_dc. As a result, the output voltage remains at 0 V. +V_dc: in this state (S₁′, S₂, S₃′, S₅, and S₆′ in operation), C_u and C_d are charged directly by V_dc, and C₁ remains inactive, resulting in an output voltage equal to V_dc. +2V_dc: this voltage level can be achieved through two distinct conducting paths. In both paths, switches S₃′, S₅, and S₆′ are conducting. In the first path (S₁′ and S₂′ conducting), C_u discharges while C_d charges directly from V_dc. In the second path (S₁ and S₂ conducting), C_u is charged by V_dc while C_d discharges. Capacitor C₁ remains inactive in both cases, and the output voltage is the sum of V_dc and either V_cu or V_cd. +3V_dc: in this state (S₁, S₂′, S₃′, S₄, S₅ and S₆′ in operation), C_u and C_d discharge, and C₁ charges from C_u, C_d, and V_dc. The output voltage is the sum of V_dc, V_cu, and V_cd. +4V_dc: in this state (S₁′, S₂, S₃, S₅, and S₆′ in operation), C_u and C_d charge directly from V_dc, while C₁ discharges. The output voltage is the sum of V_dc and V_cu. +5V_dc: this voltage level is also achieved through two conducting paths. In both cases, S₃, S₅, and S₆′ are conducting. In the first path (S₁′ and S₂′ conducting), C_u discharges while C_d charges from V_dc. In the second path (S₁ and S₂ conducting), C_u charges from V_dc while C_d discharges. Capacitor C₁ remains discharging in both states, and the output voltage is determined by the sum of V_dc, V_cu, and V_c1 in the first state, or V_dc, V_cd, and V_c1 in the second state. +6V_dc: in this state (S₁, S₂′, S₃, S₅, and S₆′ in operation), C_u, C_d, and C₁ all discharge, resulting in all capacitors and the DC voltage source being connected in series. This configuration generates the peak voltage, with the output determined by the sum of V_dc, V_cu, V_cd, and V_c1. −V_dc to −6V_dc: the process for generating negative voltage levels mirrors that of the positive voltage levels, with the only difference being the operation of the H-bridge. In this case, switches S₅′ and S₆ conduct instead of S₅ and S₆′.

3. Simulation of the Proposed SSCBMLI Topology

3.1. Simulation Specifications

The simulation of the proposed 13-level SSCBMLI was conducted using PLECS 4.5, following the specifications provided in Table 3.

Table 3. Simulation specifications for the 13-level SSCBMLI.

Specification	Parameters
DC voltage source	Vdc = 100 V
AC fundamental frequency	f = 50 Hz
Diode forward voltage	Vd,f = 1.6 V
Diode on-resistance	Rd,on = 826.5 µΩ
Switch on-resistance	Rsw,on = 25 mΩ
Capacitors	Cu = Cd = 4700 µF, C1 = 3300 µF
Capacitor internal resistance	Rcu = Rcd = 32.8 mΩ, Rc1 = 30.0 mΩ
Resistive load	Rload = 210 Ω
Resistive-inductive load	Rload = 157.5 Ω, Lload = 0.335 H
Modulation index	0.3, 0.5, 0.8, 1.0

During the simulation, specifications for the power electronic components were derived from the manufacturer datasheets to ensure practical accuracy. Specifically, the capacitance values for C_u and C_d were chosen to be higher than that of C₁, based on their increased rates of charging and discharging during operation. To evaluate the performance of the proposed topology, a series of tests was conducted and validated under various conditions, including resistive (R) and resistive-inductive (RL) loads, changes in modulation index (MI), and fluctuations in source power.

3.2. Simulation Performance Verification

Figure 4 illustrates the AC output voltage and current produced by the 13-level SSCBMLI when the load transitions abruptly from an R load to an RL load at MI of 1.0. The 13-level SSCBMLI generates 13 discrete levels of AC output voltage and current at a unity MI, achieving a peak output voltage of approximately 600 V—significantly higher than the 100 V input DC voltage. This reflects the topology’s capacity to boost the input DC voltage V_dc, demonstrating a voltage gain of six. The AC output current generated under R and RL loads is also illustrated, with the first five cycles representing the R load response, and subsequent cycles reflecting RL load operation. The AC current waveform transitioning from non-sinusoidal to a stable sinusoidal pattern highlights the topology’s capability to accommodate RL loads effectively.

Figure 4. Simulation results of AC output voltage v_out and current i_out during R to RL load transition at MI = 1.0.

In Figure 4a, the AC output voltage levels and amplitude remain consistent during the transition from an R load to an RL load, demonstrating the topology’s ability to maintain a stable voltage output regardless of load changes. In Figure 4b, although the AC output current retains the same 13 discrete levels, its amplitude varies as the load shifts to an RL configuration. Under RL loading, the AC output current waveform exhibits a pure sinusoidal shape, further showcasing the topology’s effectiveness in accommodating and stabilizing under RL loads.

Figure 5 shows the waveforms of DC voltage, DC current, and power for capacitors C_u, C_d, and C_1, highlighting their charging and discharging behavior. Figure 5a,b show the DC voltage waveforms for capacitors C_u, C_d, and C₁, demonstrating their voltage regulation during charging and discharging cycles. Figure 5c presents the DC current waveforms, highlighting the charging and discharging current characteristics of the capacitors. Figure 5d depicts the power waveforms, illustrating the energy transfer and utilization, as well as the charging and discharging power dynamics of C_u, C_d, and C₁ within the circuit.

Figure 5. Simulation results showing voltages (V_cu, V_cd, V_c1), currents (I_cu, I_cd, I_c1), and powers (P_cu, P_cd, P_c1) for capacitors at MI = 1.0.

The DC voltage across C_u and C_d remains balanced at V_dc = 100 V each, while C₁ maintains at a DC voltage of 3V_dc = 300 V. This demonstrates that the capacitors possess inherent self-regulation capabilities, eliminating the need for auxiliary control circuits. During operation, the capacitors cyclically charge and discharge to maintain stable DC voltage levels.

3.3. Total Harmonic Distortion (THD) vs. Modulation Index (MI)

A THD analysis was conducted through simulation to assess power quality under R and RL loads at various MI values, based on AC output voltage and current waveforms captured over five cycles for each load at different MI values. Figure 6 and Table 4 reveal that the R load exhibits greater distortion in the AC current output waveforms than the RL load across different MI values. This higher harmonic content is due to the absence of reactive elements, such as inductance, in the R load circuit. In contrast, an RL load, which includes both resistance and inductance, introduces a filtering effect that dampens higher-frequency harmonics in the current waveform. Inductors resist changes in current, especially at higher frequencies, which helps reduce harmonic distortion, as observed in Table 4.

Figure 6. Simulation results of AC output voltage v_out and AC output current i_out for MI values: (a) 1.0, (b) 0.8, (c) 0.5, and (d) 0.3 under R load and RL load.

Table 4. Simulation results of voltage and current THD (%) for R and RL loads with varying MI.

Load	MI	Vout (V)	THD (%)	Iout (A)	THD (%)
R load (210 Ω)	1.0	588.13	6.41	2.80	6.18
	0.8	490.44	8.65	2.33	8.45
	0.5	295.76	12.38	1.41	12.18
	0.3	196.68	21.45	0.94	21.28
RL load (157.5 Ω and 0.335 H)	1.0	589.73	6.40	3.14	0.60
	0.8	491.29	8.66	2.53	1.59
	0.5	296.02	12.37	1.65	1.71
	0.3	196.73	21.47	1.08	5.27

The effects of MI variation on the AC output voltage and current are also notable. As MI decreases from 1.0 to 0.8, 0.5, and 0.3 (at 0.2 s, 0.3 s, 0.4 s, and 0.5 s, respectively), the amplitude of the modulating signal reduces, impacting both the amplitude and shape of the waveforms, as shown in Figure 7. Specifically, lower MI values result in decreased amplitude and potential changes in harmonic content, as summarized in Table 4.

Figure 7. Transition of AC output voltage v_out and current i_out for different MI values under R load (a,b) and RL load (c,d).

3.4. Efficiency and Power Loss Analysis

This section examines the efficiency and power dissipation of the proposed 13-level SSCBMLI topology, based on simulation results. To ensure realistic assessment, power components are configured in accordance with the manufacturer specifications. For this analysis, the models C3M0025065K and C3D16060D are used as switches and diodes in the simulation, which is conducted under steady-state conditions with a heat sink at an ambient temperature of 25 °C.

In this analytical framework, the total power loss P_loss,total, includes contributions from conduction losses P_cond and switching losses P_sw due to both active and passive switches, as well as resistive losses P_r and ripple losses P_rip from capacitors. Consequently, the total power loss and efficiency can be expressed as follows:

$$P_{loss,total}=P_{cond}+P_{sw}+P_r+P_{rip}$$

(1)

$$\eta ={\displaystyle \frac{P_{out}}{P_{out}+P_{loss,total}}}$$

(2)

Conduction loss refers to heat generated by the switches and diodes during steady-state operation. This loss is calculated by considering the average current and internal resistance of each switch and diode in its on-state. The total conduction loss P_cond,total, can thus be derived as follows:

$$P_{cond,total}=\sum _{N_{switch}}{I^2}_{avg,sw}{R}_{on,sw}+\sum _{N_{diodes}}{I^2}_{avg,d}{R}_{on,d}$$

(3)

where I_avg,sw represents the average current through the switch in its on-state, I_avg,d is the average diode current in its on-state, R_on,sw is the switch’s on-state resistance, and R_on,d is the diode’s on-state resistance.

Active switches also exhibit time delays during turn-on and turn-off phases. This delay, along with abrupt switching processes, creates overlaps in voltage and current, which results in switching losses. The total switching loss P_sw,total is then derived as follows:

$$P_{sw,total}=\sum _{N_{switch}}\left\{\sum _{N_{on, off}}{\displaystyle \frac{f}{6}}\left(V_{on}{I}_{on}{t}_{on}+V_{off}{I}_{off}{t}_{off}\right)\right\}$$

(4)

where f represents the operating frequency, V_on and I_on are the voltage and current during turn-on, t_on is the duration of the turn-on phase, and V_off and I_off represent voltage and current during turn-off, with t_off as the turn-off duration.

Capacitor resistive loss P_r results from power dissipation due to the internal resistance of the capacitors. Capacitor ripple loss P_rip, however, arises from voltage fluctuations during charging and discharging cycles. The capacitor resistive and ripple losses are expressed as follows:

$$P_{r,total}=\sum _{N_{capacitor}}{R}_c{\left(I_{c,charge}+I_{c,discharge}\right)}^2$$

(5)

$$P_{rip,total}=\sum _{N_{capacitor}}∆{V_c}^2\pi f_{c}C\tan \delta$$

(6)

where R_c is the capacitor’s internal resistance, I_c,charge and I_c,discharge represent current during charging and discharging, ∆V_c is the voltage drop across the capacitor, f_c is the switching frequency, and δ (i.e., set at two) represents the dissipation factor.

Table 5 presents the efficiency and power dissipation characteristics of the proposed 13-level SSCBMLI topology, evaluated under an R load, with source power adjusted across 50 W, 100 W, 200 W, 500 W, and 1000 W by varying resistance values.

Table 5. Efficiency and power dissipation of the proposed 13-level SSCBMLI topology.

Source Power (W)	50	100	200	500
Capacitor Loss (W)	0.015	0.080	0.235	1.130
Switch Loss (W)	0.018	0.061	0.216	1.310
Diode Loss (W)	1.056	2.191	4.704	13.406
Total Loss (W)	1.076	2.332	5.155	15.845
Resistance (Ω)	3640	1820	910	363
Output Voltage (V)	593.28	592.96	592.32	590.42
Output Current (A)	0.16	0.33	0.65	1.63
Efficiency (%)	97.84	97.68	97.43	96.84

Total power losses include contributions from conduction and switching losses in switches and diodes, as well as resistive and ripple losses in capacitors. The results indicate that the proposed topology achieves operational efficiency levels exceeding 95% for source power levels up to 1000 W, with output voltage reaching up to six times the input DC voltage. However, a slight decline in efficiency may occur as the source power increases, primarily due to higher current flow in conducting pathways, which leads to increased power losses.

4. Experiment of the Proposed SSCBMLI Topology

4.1. Experiment and Hardware Setup Specifications

The experiment for the proposed 13-level SSCBMLI topology was conducted according to the specifications outlined in Table 6 to validate its practical performance.

Table 6. Experiment specifications for the proposed 13-level SSCBMLI.

Specification	Models, Parameters, and Values	Manufacturer
DC voltage source	Vdc = 20 V
AC fundamental frequency	f = 50 Hz
MI	0.3, 0.5, 0.8, 1.0
R load	R = 210 Ω
RL load	R = 157.5 Ω, L = 0.335 H
Capacitor	C1 = C2 = 4700 µF, C3 = 3300 µF
Diode	MUR1560G	ONSEMI (Scottsdale, AZ, USA)
Switch	AUIRGP50B60PD1 and IGW30N60T (for S4 only)	Infineon Technologies (Munich, Germany)
DSP controller	EZDSP F28335	Spectrum Digital (Plano, TX, USA)
Gate driver	HCPL-3120	Broadcom (San Jose, CA, USA)
DC power Supply	GW Instek GPC-3030B	Good Will Instrument (New Taipei City, Taiwan)
Oscilloscope	DSO-X 2012A	Keysight Technologies (Santa Clara, CA, USA)
Power analyzer	Fluke 43B	Fluke Corporation (Everett, WT, USA)

The manufacturers for the components listed in Table 6 are ON Semiconductor (ONSEMI) for MUR1560G, and Infineon Technologies for both AUIRGP50B60PD1 and IGW30N60T.

A small-scale prototype was utilized, with a single input DC voltage set at 20 V. The prototype was tested under various MI conditions with both R and RL loads to obtain experimental results. To accommodate the higher charging and discharging rates, the capacitance values of C₁ and C₂ were chosen to be greater than that of C₃. In the experimental setup, the AUIRGP50B60PD1 was employed as an IGBT switch with an anti-parallel diode, while the IGW30N60T functioned as a transistor in S₄ of the extendable SC unit.

Figure 8 illustrates the block diagram of the experimental setup for the prototype (see Figure 9).

Figure 8. Block diagram of the simulation setup for the 13-level SSCBMLI.

Figure 9. Experiment setup for the 13-level SSCBMLI.

The Digital Signal Processor (DSP) controller, EZDSP F28335, generated gate signals based on the control algorithm implemented in SIMULINK R2018a. To drive the IGBTs, the gate signals were amplified from 5 V to ±15 V using the optocoupler gate driver HCPL-3120. These amplified signals were then transmitted to the IGBTs for switching. The prototype was powered by DC voltage and connected to a load bank. Voltage and current probes measured the outputs at the load, while an oscilloscope and power analyzer were used to visualize the output values and behaviors for data collection and analysis.

4.2. Experiment Performance Verification

A THD analysis was conducted on the prototype to assess the practical power quality generated by the proposed 13-level SSCBMLI topology. Similar to the simulation phase, the prototype was tested with an R load and an RL load, with MI values of 0.3, 0.5, 0.8, and 1.0. Figure 10 presents the experimental results of AC output voltage V_out and output current I_out, along with power analysis and harmonic profiles for both loads. All figures depict the AC output voltage waveform V_out and AC output current waveform I_out, with scales of 50 V/division and 0.5 A/division, respectively.

Figure 10. Experiment results of AC output voltage v_out and AC output current i_out for MI values: (a) 1.0, (b) 0.8, (c) 0.5, and (d) 0.3 under R load and RL load.

The experimental outcomes for AC output voltage and output current, along with their respective THD values for both R and RL loads under varying MI, are summarized in Table 7.

Table 7. Experiment results of voltage and current THD (%) for R and RL loads for variation of MI.

Load	MI	Vout (V)	THD (%)	Iout (A)	THD (%)
R load (210 Ω)	1.0	61.70	4.70	0.28	6.90
	0.8	51.80	7.40	0.23	8.40
	0.5	34.38	8.70	0.16	12.50
	0.3	20.70	19.70	0.10	25.70
RL load (157.5 Ω and 0.335 H)	1.0	64.00	4.80	0.29	1.70
	0.8	52.00	7.20	0.24	1.80
	0.5	34.20	9.90	0.16	2.90
	0.3	22.00	19.20	0.01	7.50

The tabulated results indicate that the minimum THD is observed at an MI of 1.0, with approximately 4.7% for the AC output voltage at the R, and 1.7% for the AC output current at RL load. Both voltage and current THD values increase significantly as MI decreases. Although the THD results obtained are considered low for 13-level MLIs, filters are commonly employed to further reduce output THD. Additionally, extending the proposed topology to achieve a higher number of output voltage levels can significantly reduce THD.

Table 8 presents a comparison between the simulation and experimental results for the THD of both the AC output voltage and output current in the proposed 13-level SSCBMLI topology. The analysis is conducted under varying MI values for R and RL loads. The results reveal minor variations between the simulation and experimental measurements. For instance, the experimental AC output voltage THD is 4.7%, slightly lower than the simulation result of 6.41% when the proposed SSCBMLI operates with a purely resistive load at MI = 1.0. These discrepancies are primarily attributed to the limitations of the power analyzer’s precision during the experimental phase. Additional contributing factors include non-ideal switching behavior, measurement noise, and real-world parasitics, which are not accounted for in simulations. Notably, during the experimental phase, the proposed topology demonstrates exceptionally low voltage THD, maintaining values below 5% at MI = 1.0. This result highlights the capability of the proposed topology to generate high-quality output voltage waveforms suitable for practical applications. On the other hand, current THD is more sensitive to variations in MI and load characteristics, with experimental results showing a slight increase compared to simulations, particularly at lower MI values. This difference is likely due to the inherent effects of load dynamics and the interactions between real-world inductive and resistive components. Overall, the comparison consistently validates the performance of the proposed 13-level SSCBMLI topology in both simulation and experimental phases, demonstrating its effectiveness and reliability in achieving low harmonic distortion under various operating conditions.

Table 8. Comparison between simulation and experiment results of voltage and current THD (%) for R and RL loads for variations of MI.

Load	MI	Simulation		Experiment
		Vout THD (%)	Iout THD (%)	Vout THD (%)	Iout THD (%)
R load (210 Ω)	1.0	6.41	6.18	4.70	6.90
	0.8	8.65	8.45	7.40	8.40
	0.5	12.38	12.18	8.70	12.50
	0.3	21.45	21.28	19.70	25.70
RL load (157.5 Ω and 0.335 H)	1.0	6.40	0.60	4.80	1.70
	0.8	8.66	1.59	7.20	1.80
	0.5	12.37	1.71	9.90	2.90
	0.3	21.47	5.27	19.20	7.50

4.3. Comparative Study

This section presents a comparative study, positioning the proposed 13-level SSCBMLI topology alongside existing 13-level MLI topologies from references [8,9,13,14,15,16,17,18,19,20,21,22,23]. Parameters used to highlight differences among these topologies include N_source, N_component, N_switch, N_diode, N_capacitor, N_gate, V_boost, and the circuit structure’s extensibility, all detailed in Table 9. As observed, the proposed topology incorporates only one DC voltage source, using the fewest components and gate drivers necessary to generate a 13-level AC output voltage while achieving high voltage boosting and extensibility. In contrast, MLI topologies in references [8,9,18] have fewer components but exhibit a reduced voltage-boosting factor. Other topologies, such as those in references [16,22,23], feature extensible structures with high voltage gain but require a higher component count. Therefore, the proposed topology stands out as the most cost-effective option, requiring fewer components and gate drivers and relying on a single DC voltage source. Furthermore, by extending the circuit structure, higher voltage gains and levels can be achieved with minimal additional components.

Table 9. Comparison of the proposed 13-level SSCMLI topology with existing 13-level MLI topologies.

Parameter	[8]	[9]	[13]	[14]	[15]	[16]	[17]	[18]	[19]	[20]	[21]	[22]	[23]	Proposed
Nsource	2	2	1	1	1	1	1	1	1	1	1	1	1	1
Ncomponent	16	12	18	18	20	21	18	16	18	21	18	25	39	16
Nswitch	14	11	13	14	12	14	13	12	10	14	15	10	29	11
Ndiode	0	0	2	1	4	2	2	0	4	4	0	10	5	2
Ncapacitor	2	1	3	3	4	5	3	4	4	3	3	5	5	3
Ngate	11	10	9	10	12	12	10	11	10	8	11	8	17	6
Vboost	2	2	6	6	3	6	6	1.5	6	6	6	6	6	6
Extensibility	Yes	No	No	No	No	Yes	No	Yes	No	No	No	Yes	Yes	Yes

This cost advantage is further analyzed in Table 10, which compares the component and gate driver costs of the proposed topology with other SSCBMLIs presented in [13,14,16,17,19,20,21,22,23], all achieving the same voltage boosting gain. Among these designs, the proposed topology demonstrates the lowest component count and an overall cost of USD 87.08, owing to its efficient configuration. In contrast, the referenced topologies achieve the same voltage boosting factor but require more components and gate drivers, leading to a higher overall cost. Consequently, the proposed topology strikes an optimal balance by delivering the same voltage boosting capability with fewer components and gate drivers, making it a cost-effective and practical solution for high-performance applications.

Table 10. Cost comparison of SSCBMLI with proposed topology for the same voltage gain of six.

Component	Manufacturer	Part Number	Rating	Unit Price ($)	[13]	[14]	[16]	[17]	[19]	[20]	[21]	[22]	[23]	Proposed
MOSFET	Infineon Technologies (Munich, Germany)	IRF640NPBF	200 V, 18 A	1.71	4	5	10	5	4	4	3	6	27	4
	Vishay Siliconix (Malvern, PA, USA)	IRF740PBF	400 V, 10 A	2.78	7	7	0	6	2	6	8	0	0	3
	Infineon Technologies (Munich, Germany)	IPP60R190P6XKSA1	600 V, 20.2 A	3.42	2	2	4	2	4	2	4	4	2	4
Diode	SMC Diode Solutions (San Jose, CA, USA)	STF12100	100 V, 15 A	0.28	0	1	2	1	2	2	0	10	5	0
	Cornell Dubilier (South Plainfield, NJ, USA)	SDURF1520	300 V, 15 A	0.28	2	0	0	1	2	2	0	0	0	3
	Knowles (Itasca, IL, USA)	SLPX102M100A3P3	100 V, 1000 µF	3.34	2	2	5	2	2	2	1	5	5	2
	EPCOS—TDK Electronics (Tokyo, Japan)	B43416C3108A000	300 V, 1000 µF	6.46	1	1	0	1	2	1	2	0	0	1
Driver	Broadcom Limited (San Jose, CA, USA)	HCPL-3120-060E	625 Vmax	3.23	9	10	12	10	10	8	11	8	17	6
Heatsink	Ohmite (Melrose Park, IL, USA)	WA-T220-101E		2.26	13	14	14	13	10	12	15	10	29	11
Total Cost ($)		With Heatsink			105	112	118	107	101.7	97.58	126.74	91.88	191.56	87.08
		Without Heatsink			75.9	80.6	86.8	78.1	79.1	70.46	92.84	69.28	126.02	62.22

Courtesy: www.digikey.com. Prices are subject to change based on market conditions.

5. Conclusions

This research introduces a novel MLI design, specifically a 13-level SSCBMLI topology. The proposed topology efficiently utilizes a single DC voltage source, employing a minimal number of components and gate signals to achieve a 13-level AC output voltage. The topology’s SC unit allows for extensibility, enabling the inverter to produce higher AC output voltage levels, which significantly enhances voltage gain. The series-parallel configuration of DC capacitors provides self-voltage balancing and voltage boosting without the need for additional circuits. With high overall efficiency and reliable performance under RL loads, this topology is well-suited for solar PV applications. Extensive testing, including both simulation and experimental analyses across various loads and MI values, has validated the performance and advantages of the proposed topology. The output THD for the proposed topology is exceptionally low for a 13-level MLI. A comparative study further shows that the proposed SSCBMLI utilizes the fewest components and gate drivers to achieve a 13-level AC output voltage, with a voltage gain six times the input DC voltage source. These advanced characteristics make the proposed 13-level SSCBMLI a feasible and cost-effective choice as a solar inverter, promising high power and voltage potential in future applications.