Modeling, Simulation and Development of Grid-Connected Voltage Source Converter with Selective Harmonic Mitigation: HiL and Experimental Validations

Abstract

This paper elaborates on a development technique for the grid-connected voltage source converter (VSC). We propose a simulation technique in the MATLAB/Simulink environment that emulates the operation of the discrete-time controlled grid-connected VSC. The switched-circuit modeling approach is used for simulation of the power stage in the continuous-time domain with the physical unit scale. The discrete-time control algorithm is implemented in an interpreted MATLAB function in the per-unit scale, which synchronizes with the switching period. Such a control algorithm is easily translated into the C language for programing of the 32-bit C2000 DSP controller with the same regulators’ parameters. The proposed platform was validated with a hardware-in-the-loop real-time simulator and with a 5-kVA 3-phase LCL-filtered grid-connected VSC. The discrete-time control scheme was implemented in the synchronous reference frame control with proportional-integral with multi-resonant controllers at harmonic orders 6th and 12th for suppression of the grid voltage harmonic orders 5th, 7th, 11th, and 13th. The experimental results closely agreed with the simulation results. The experimental grid currents complied with the IEEE 1547 standard thanks to the multi-resonant controllers. The proposed platform provides a smooth transition from implementation to a near-commercial prototype with a low investment cost in simulation and rapid prototyping tools. A MATLAB/Simulink VSC model is provided as an attachment of this paper.

1. Introduction

Power electronic converters now play a vital role in modern electric power generation and distribution systems [1,2]. Three-phase voltage source converters (VSCs) are widely used to interlink DC and AC systems as illustrated in Figure 1. Common applications of the three-phase VSCs include photovoltaic [3] and wind energy systems [4], grid integration of battery storage systems [5], traction motor drives for transportation applications [6], and electric vehicle charging stations, etc. [7].

Figure 1. Applications of VSCs in the electrical system.

Figure 2 illustrates the three-phase VSC structure where it can be divided into the power stage, switching signal generation, and discrete-time control system. The DC bus voltage $v_D$ control and the active/reactive power control are the outer control loops, which generate the reference grid current ${\mathbf{i}}_{\mathbf{g}}^{\mathbf{*}}$ for the inner current control loop. The grid current ${\mathbf{i}}_{\mathbf{g}}$ is required to track the reference and to reject low-frequency harmonics in the grid voltage ${\mathbf{v}}_{\mathbf{g}}$. Harmonic controllers are normally plugged into the fundamental component current controller. Multi-resonant controllers and repetitive controllers in the stationary reference frame $\alpha \beta$, and multiple synchronous reference frame control are the common solutions for grid voltage harmonic mitigation. Moreover, frequency adaptation capability is required to maintain the control performance with the grid frequency variation. The duty ratios from the current control loop are sent to the pulse width modulation (PWM) unit to generate the switching signals for the semiconductor switches of the VSC. The control scheme of the three-phase VSCs and other power converters are now normally implemented on a microcontroller (µC) or a digital signal processor (DSP).

Figure 2. Development platforms of the three-phase grid-connected VSC.

Development of a three-phase VSC starts from a simulation using power simulation software for the power stage, PWM, control systems such as PSIM or Simscape in MATLAB/Simulink (simulation platform 1 in Figure 2). This platform provides a quick validation before hardware prototyping. Component losses and thermal behavior can be easily modeled. However, a lack of deep knowledge in modeling the converter circuit and dynamic makes it difficult when designing the controllers. Moreover, the dedicated software cost is considerably high.

The power stage of the VSC can be simulated using the switched-circuit modeling technique [8] where the state equations are calculated for every switching state herein defined as simulation platform 2 in Figure 2. The semiconductors devices are normally considered as the ideal switches without voltage drops and switching and conducting losses. This technique can be modeled with basic blocks in MATLAB/Simulink. This switched circuit model can be easily connected with other control blocks that are already available in the Simulink. Investment cost in the software license is comparatively low. However, this method requires a deep understanding of the converter operation which takes additional time and effort compared with the simulation platform 1.

After computer simulation, the control scheme can be implemented into a rapid control prototyping (RCP) system, while the power stage of the VSC can be modeled in a hardware in the loop (HiL) system, defined as prototype platform 1 in Figure 2. RCP and HiL systems are normally equipped with field-programmable gate arrays (FPGAs) or high-performance microprocessors with digital and analog interfacing, which accelerates validation of the prototype. No programming effort is required since the control block diagrams in the simulation are directly translated into the RCP system. HiL systems provide high fidelity with a small-time step for real-time simulation of the semiconductor switches and passive components. It has been reported that the ratio of the switching period to the simulation time step should be greater than 60 times for equation-based modeling and 60,000 for physical-based modeling [9]. Common RCP systems for power electronic applications are dSPACE Microlabbox (Paderborn, Germany) [10,11] and OPAL-RT OP4510 (Montreal, QC, Canada) [12,13] and Imperix B-Box (Sion, Switzerland) [14] etc. Common commercial HiL systems are OPAL-RT OP4510 (Montreal, QC, Canada) [12], dSPACE SCALEXIO (Paderborn, Germany) [9], Typhoon HiL (Somerville, MA, USA) [15,16] and National Instruments LabVIEW FPGA (Austin, TX, USA) [17]. The VSC power stage emulated in a HiL system is easily connected with the control stage implemented in an RCP system or a DSP-based controller. Hardware simulation using HiL systems is normally used to validate control schemes for a large system such as a microgrid controller [18] or a high-power wind turbine converter [19].

The control scheme implemented in the RCP system can be connected to the physical hardware for the power converter, here defined as prototype platform 2 in Figure 2. This research platform is popular for quick verification of converter control methodologies, for which no programming effort is required. Physical units are virtually employed in such a system. Measured signals, i.e., voltages and currents are just scaled into the control block diagrams with their associated gains. Commercialization of prototype platform 2 takes further effort in the implementation of the control scheme. The control scheme is discretized and programmed onto a microcontroller or a DSP [20,21,22,23,24], here called prototype platform 3. The sampled currents and voltages are normally scaled into the per-unit (p.u.) system so that they are compatible with a limited numerical range of the DSP. This prototype platform 3 has a similar structure to commercial products for example power factor correction rectifiers, grid-connected inverters, and back-back converters [2,20,24]. Thus, it takes a little effort to commercialize the prototype platform 3.

Simulation platform 1 and prototype platforms 1 and 2 enable a smooth transition from modeling to implementation with a substantial investment in simulation software, RCP systems, and HiL systems. Alternatively, simulation platform 2 and prototype platform 3 are the cheapest development platforms, which are suitable for power converter research and development in developing countries. Example products and estimated costs of the simulation and prototype platforms are summarized in Table 1.

Table 1. Example products and estimated cost for the simulation and prototype platforms.

Platforms	Products	Cost	Implementation Effort
Simulation platform 1	MATLAB/Simulink with Simscape and Simscape Electrical	11,800 USD	Little
Simulation platform 2 & proposed method	MATLAB/Simulink	5900 USD	Moderate
Prototype platform 1	dSPACE Microlabbox Associated MATLAB/Simulink products	+30,000 USD	Little
Prototype platform 2	dSPACE Microlabbox OPAL-RT OP4510 Associated MATLAB/Simulink products	+80,000 USD	Little
Prototype platform 2	Texas Instruments LaunchXL379D Power electronic hardware for 5-kVA 3-ph VSC	2000 USD	Hard

This paper illustrates a development methodology for a DSP-based control power electronic converter that facilitates a smooth transition from implementation to a near-commercial prototype without a circuit-based simulation package and an RCP tool. This paper covers switched circuit modeling of the VSC, and its discrete-time control scheme developed in the MATLAB/Simulink environment from basic block diagrams. The control scheme is scaled into the per-unit system so that the regulators’ parameters can be directly transferred to the discrete-time control system implemented on a TMS320F28379D DSP controller from Texas Instruments (Dallas, TX, USA) as illustrated at the bottom of Figure 2. A three-phase grid-connected VSC with the proportional-integral plus multi-resonant (PIMR) controllers in the synchronous reference frame for mitigation of grid voltage harmonics is selected in this study. The proposed method was validated with a simulation platform 1 using the Simscape Electrical toolboxes in the MATLAB/Simulink, an HiL real-time simulator, and 5-kVA three-phase grid-connected VSC.

2. System Description

Figure 3 depicts an LCL-filtered three-phase grid-connected VSC with the synchronous reference frame control. The grid voltages, grid currents, and the DC bus voltage are sampled by the analog-to-digital converters (ADCs), which are represented as the zero-order hold (ZOH) blocks in the simulation. The sampled voltages are scaled by $K_{SV}$ into the per-unit system and $K_{SI}$ for the sampled currents. The superscript “ ´ ” denotes the signals in the p.u. scale. The grid currents are transformed to the synchronous reference frame, on which the $dq$-axes current $i_{gd}^{\prime }$ and $i_{gq}^{\prime }$ are regulated by the discrete-time current controllers $G_{ci}\left(z\right)$ with the reference current $i_{gd,ref}^{\prime }$ generated from the active power control loop and/or the DC bus voltage control loop and the reference current $i_{gq,ref}^{\prime }$ obtained from the reactive power control loop or by setting $i_{gq,ref}^{\prime }=0$ for a unity power factor. The distorted grid voltages $v_{ga}$, $v_{gb}$ and $v_{gc}$ are given by

$$\begin{array}{c}{v}_{ga}\left(t\right)={\widehat{V}}_1\cos \theta +{\displaystyle \sum }_h^n{\widehat{V}}_k\cos h\theta \\ v_{gb}\left(t\right)={\widehat{V}}_1\cos \left(\theta -2\pi /3\right)+{\displaystyle \sum }_h^n{\widehat{V}}_k\cos h\left(\theta -2\pi /3\right)\\ v_{gc}\left(t\right)={\widehat{V}}_1\cos \left(\theta +2\pi /3\right)+{\displaystyle \sum }_h^n{\widehat{V}}_k\cos h\left(\theta +2\pi /3\right)\end{array}\}$$

(1)

where $\theta =\omega t$ and $\omega$ is the grid frequency. The three-phase three-wire system contains the harmonic orders $h=5,7,11,13,\dots$. A phase-locked loop (PLL) is used to estimate the grid voltage angle $\widehat{\theta }$ for the reference frame transformation. The grid voltage in the stationary reference frame is obtained from

$${\overrightarrow{v}}_{\alpha \beta }=v_{g\alpha }+j{v}_{g\beta }=\frac{2}{3}\left(v_{ga}+v_{gb}{e}^{j\frac{2\pi }{3}}+v_{gb}{e}^{-j\frac{2\pi }{3}}\right).$$

(2)

Figure 3. Three-phase grid-connected LCL-filtered VSC with the discrete-time control scheme in the synchronous reference frame.

Note that the zero-sequence is neglected for the balanced system. Substituting (1) into (2), the grid voltage can be represented as

$${\overrightarrow{v}}_{\alpha \beta }={\widehat{V}}_1+{\widehat{V}}_5{e}^{-j5\theta }+{\widehat{V}}_7{e}^{j7\theta }+{\widehat{V}}_{11}{e}^{-j11\theta }+{\widehat{V}}_{13}{e}^{j13\theta }+\cdots .$$

(3)

Thus, the grid voltage in the synchronous reference frame is given by

$${\overrightarrow{v}}_{dq}={\overrightarrow{v}}_{\alpha \beta }{e}^{-j\theta }={\widehat{V}}_1+{\widehat{V}}_5{e}^{-j6\theta }+{\widehat{V}}_7{e}^{j6\theta }+{\widehat{V}}_{11}{e}^{-j12\theta }+{\widehat{V}}_{13}{e}^{j12\theta }+\cdots .$$

(4)

The voltage harmonic orders $\pm h=6,12,\cdots$ in the synchronous reference frame result from the harmonic orders $\left(h\pm 1\right)$ in the stationary reference frame, which become the disturbances of the $dq$-axes current control loops. The PIMR controller depicted in Figure 4 is adopted for the $dq$-axes current regulators [25]. The PMR transfer function in the s-domain is given by

$$G_{ci}\left(s\right)=K_p+\frac{K_{i1}}{s}+{{\displaystyle \sum }}_{h=6,12,\cdots }\frac{K_{ih}s}{s^2+{\left(h\omega \right)}^2}.$$

(5)

Figure 4. Proportional-integral plus multi-resonant controller.

The proportional-integral (PI) controller regulates the fundamental component current which is the DC quantities in the $dq$-axes. The multiple resonant (MR) controllers regulate both negative and positive sequence components [26], which can be used to attenuate the grid voltage harmonics at the frequencies $\pm 6\omega ,\pm 12\omega ,\cdots$ in the synchronous reference frame [25]. The double integrator structure of the resonant controllers uses the estimated grid frequency from the PLL for frequency adaptation. The equivalent transfer function of $G_{ci}\left(s\right)$ in the stationary reference frame is determined from [26].

$$G_{ci}^s\left(s\right)=G_{ci}\left(s+j\omega \right)+G_{ci}\left(s-j\omega \right).$$

(6)

Substitution of (5) into (6) becomes

$$G_{ci}\left(s\right)=K_p+\frac{2K_{i1}s}{s^2+{\omega }^2}+\underset{H\left(s\right)}{\underbrace{{{\displaystyle \sum }}_{h=6,12,\cdots }\frac{2K_{ih}\left(s^2+\left(1+h^2\right){\omega }^2\right)s}{s^4+2\left(1+h^2\right){\omega }^2{s}^2+{\left(1-h^2\right)}^2{\omega }^4}}}.$$

(7)

The harmonic compensators $H\left(s\right)$ in (7) are identical to individual resonant controllers $R\left(s\right)$ tuned at frequencies $\left(1\pm h\right)\omega$ in the stationary reference frame which is given by

$$R\left(s\right)={{\displaystyle \sum }}_{h=6,12,\cdots }\frac{K_{ih}s}{s^2+{\left(1\pm h\right)}^2{\omega }^2}.$$

(8)

Therefore, the stationary frame equivalence of the synchronous reference frame controller $G_{ci}\left(s\right)$ is similar to a proportional-multiple resonant controller implemented in the stationary reference frame [25], which is written by

$$G_{ci}^s\left(s\right)=K_p+\frac{2K_{i1}s}{s^2+{\omega }^2}+{{\displaystyle \sum }}_{h=6,12,\cdots }\frac{K_{ih}s}{s^2+{\left(1\pm h\right)}^2{\omega }^2}.$$

(9)

The outputs of the $dq$-axes current controllers with feedforward of the decoupled terms $K_{FW}$ form the VSC reference voltages $v_{d,ref}^{\prime }$ and $v_{d,ref}^{\prime }$, which are converted to the stationary reference frame $v_{\alpha ,ref}^{\prime }$ and $v_{\beta ,ref}^{\prime }$ using the inverse Park transformation given by

$${\overrightarrow{v}}_{\alpha \beta ,ref}^{\prime }=\left(v_{\alpha ,ref}^{\prime }+j{v}_{\beta ,ref}^{\prime }\right)=\left(v_{d,ref}^{\prime }+j{v}_{q,ref}^{\prime }\right)·e^{j\theta }.$$

(10)

The reference voltages $v_{\alpha ,ref}^{\prime }$ and $v_{\beta ,ref}^{\prime }$ are the inputs for the space vector modulation (SVM) which calculates the duty ratios $d_a$, $d_b$, and $d_c$ for the compare unit to generate the VSC switching commands.

The control scheme in Figure 3 is normally implemented on a DSP, and it must be executed within an interrupt service routine (ISR). Figure 5 illustrates the timing diagram of each ISR, which starts when the PWM carrier reaches zeros or the maxima. The controller sampling frequency $f_s$ doubles the switching frequency $f_{sw}.$ The analog signal sampling is synchronized with the ISR at time instance $k$ that occurs in the middle of the switching action to avoid switching noise. This requires a small filtering effort for each signal, which enhances the control loop bandwidth. The analog to digital conversion and scaling, and the PLL are executed every ISR. If the VSC operation is enabled, the other VSC control algorithms are performed, otherwise, they are skipped to the end of the ISR. The control scheme is executed within the sampling period $T_s=1/f_s$, and the calculated duty ratios $d_a\left(k\right)$, $d_b\left(k\right)$, and $d_c\left(k\right)$ are updated to the compare unit at the next time instance $k+1$.

Figure 5. Timing diagram and control sequence of the VSC discrete-time control.

The VSC currents $i_{Ia}$, $i_{Ib}$, and $i_{Ic}$ or the grid currents $i_{ga}$, $i_{gb}$, and $i_{gc}$ can be used as the feedback signals for the current control loop. For the VSC current feedback, current sensors can be embedded in the VSC where overcurrent is directly protected. However, the injected power to the grid is not directly controlled. Moreover, the grid currents are susceptible to grid voltage harmonics [27]. Therefore, the grid currents are used for the feedback signals to directly control the injected power. The per-phase transfer function of the LCL filter is given by

$$G_{LCL}\left(t\right)=\frac{i_g\left(s\right)}{v_I\left(s\right)}=\frac{s{C}_f{R}_f+1}{C_f{L}_1{L}_2{s}^3+C_f\left(L_1+L_2\right)R_f{s}^2+C_f\left(L_1+L_2\right)s}.$$

(11)

This yields the resonant frequency of the LCL filter $f_{LCL}$ as

$$f_{LCL}=\frac{1}{2\pi \sqrt{\left(\frac{L_1{L}_2}{L_1+L_2}\right)C_f}}.$$

(12)

For the inherent damping, the sampling frequency $f_s$ and the resonant frequency of the LCL filter $f_{LCL}$ have to satisfy the stability criterion given by [28]

$$\frac{f_s}{6}<f_{LCL}<\frac{f_s}{2}.$$

(13)

Table 2 lists the key parameters of the VSC and the LCL filter in this study. This LCL filter is inherited damped by the inductor winding resistances $R_1$ and $R_2$, and the capacitor equivalent series resistance $R_f$. This results in a resonant frequency of $f_{LCL}=5245$ Hz which satisfies the stability criterion in (13). Passive, active, or hybrid damping techniques can be used to further improve control stability with the presence of large grid impedance [29].

Table 2. Parameters of the VSC.

Parameters	Value
Nominal grid voltage	Three-phase 380 V line-line 50 Hz
Nominal power	5 kVA
Nominal DC bus voltage	650 V
DC bus capacitor, $C_D$	780 µF
Switching frequency, $f_{sw}$	10 kHz
Sampling frequency, $f_s$	20 kHz
DC bus resistor, $R_D$	94 kΩ
Converter-side inductor, $L_1$	1.4 mH
Winding resistance of $L_1$, $R_1$	0.110 Ω
Grid-side inductor, $L_2$	0.7 mH
Winding resistance of $L_2$, $R_2$	0.042 Ω
Filter capacitor, $C_f$	1.94 µF
Series resistor, $R_f$	0.001 Ω
Base voltage, $V_B$	311 V
Base current, $I_B$	10.74 A
Base impedance, $Z_B$	28.88 Ω

3. Modeling of the LCL-Filtered VSC

3.1. Switched Circuit Modeling of the Power Circuit

Figure 6 displays the equivalent circuit of the VSC. Resistors $R_1$ and $R_2$ are the winding resistance of the inductors $L_1$ and $L_2$. Resistors $R_f$ are the equivalent series resistance of the capacitors $C_f$ plus the series damping resistance of the LCL filter. Resistor $R_D$ is the effective DC bus capacitance of the DC bus voltage sensor and the discharging resistor. The semiconductor switches are represented by switches $S_a$, $S_b$, and $S_c$. The status of each switch is represented by “1” for the closed state and “0” for the opened state. The complementary switches ${\overline{S}}_a$, ${\overline{S}}_b$, and ${\overline{S}}_c$ operate opposite $S_a$, $S_b$, and $S_c$. Therefore, there are eight possible output states of the VSC. There are three reference points: $m$, $n$, and $o$. The DC bus current $i_o$ is supplied or drawn by another converter, which is positive for the inverting mode and negative for the rectifying mode.

Figure 6. Equivalent circuit of the three-phase grid-connected VSC with the LCL filter.

The grid currents $i_{ga}$, $i_{gb}$, and $i_{gc}$ can be written as follows

$$\begin{array}{c}{L}_2\frac{d{i}_{ga}}{dt}=\left(v_{Fa,m}+v_{mn}\right)-v_{ga,n}-R_2{i}_{ga}\\ L_2\frac{d{i}_{gb}}{dt}=\left(v_{Fb,m}+v_{mn}\right)-v_{gb,n}-R_2{i}_{gb}\\ L_2\frac{d{i}_{gc}}{dt}=\left(v_{Fc,m}+v_{mn}\right)-v_{gc,n}-R_2{i}_{gc}\end{array}\} .$$

(14)

where $v_{Fa,m}$, $v_{Fb,m}$, and $v_{Fc,m}$ are the voltages across the filter capacitor $C_f$ and the series resistor $R_f$ with respect to point $m$, which are given by

$$\begin{array}{c}{v}_{Fa,m}=v_{Cfa}+R_f\left(i_{ga}-i_{Ia}\right)\\ v_{Fb,m}=v_{Cfb}+R_f\left(i_{gb}-i_{Ib}\right)\\ v_{Fc,m}=v_{Cfc}+R_f\left(i_{gc}-i_{Ic}\right)\end{array}\} .$$

(15)

The voltages across the filter capacitor $C_f$, $v_{Cfa}$, $v_{Cfb}$, and $v_{Cfc}$ are determined from

$$\begin{array}{c}{C}_f\frac{d{v}_{Cfa}}{dt}=i_{ga}-i_{Ia}\\ C_f\frac{d{v}_{Cfb}}{dt}=i_{gb}-i_{Ib}\\ C_f\frac{d{v}_{Cfc}}{dt}=i_{gc}-i_{Ic}\end{array}\}.$$

(16)

The VSC currents $i_{Ia}$, $i_{Ib}$, and $i_{Ic}$ are given by

$$\begin{array}{c}{L}_1\frac{d{i}_{Ia}}{dt}=\underset{v_{Ia,m}}{\underbrace{\left(v_{Ia,o}+v_{om}\right)}}-v_{Fa,m}-R_1{i}_{Ia}\\ L_1\frac{d{i}_{Ib}}{dt}=\underset{v_{Ib,m}}{\underbrace{\left(v_{Ib,o}+v_{om}\right)}}-v_{Fb,m}-R_1{i}_{Ib}\\ L_1\frac{d{i}_{Ic}}{dt}=\underset{v_{Ic,m}}{\underbrace{\left(v_{Ic,o}+v_{om}\right)}}-v_{Fc,m}-R_1{i}_{Ic}\end{array}\} .$$

(17)

where the VSC voltages $v_{Ia,o}$, $v_{Ib,o}$, and $v_{Ic,o}$ with respect to point $o$ depends on the switching states as follows

$$\begin{array}{c}{v}_{Ia,o}=S_a{v}_D\\ v_{Ib,o}=S_b{v}_D\\ v_{Ic,o}=S_c{v}_D\end{array}\}.$$

(18)

For the balanced three-phase three-wire system, $v_{ga,n}+v_{gb,n}+v_{gc,n}=0$,$v_{Fa,m}+v_{Fb,m}+v_{Fc,m}=0$, $i_{ga}+i_{gb}+i_{gc}=0$ and $i_{Ia}+i_{Ib}+i_{Ic}=0$, which results in

$$v_{mn}=0.$$

(19)

Thus, the grid currents can be written as follows

$$\begin{array}{c}{L}_2\frac{d{i}_{ga}}{dt}=v_{Fa,m}-v_{ga,n}-R_2{i}_{ga}\\ L_2\frac{d{i}_{gb}}{dt}=v_{Fb,m}-v_{gb,n}-R_2{i}_{gb}\\ L_2\frac{d{i}_{gc}}{dt}=v_{Fc,m}-v_{gc,n}-R_2{i}_{gc}\end{array}\}.$$

(20)

Adding the sub-equations of (17) together, the common mode voltage $v_{om}$ is expressed as

$$v_{om}=-\frac{v_D}{3}\left(S_a+S_b+S_c\right).$$

(21)

This common-mode voltage $v_{om}$ intrinsically exists in the two-level VSC due to limited switching states, which creates a leakage current through the parasitic capacitance between the DC bus and the neutral points of the system. The VSC currents $i_{Ia}$, $i_{Ib}$, and $i_{Ic}$ are driven by the differential mode voltages $v_{Ia,m}$, $v_{Ib,m}$, and $v_{Ic,m}$ between the VSC legs and the neutral point $m$ of the capacitor bank, which can be written as

$$\begin{array}{c}{L}_1\frac{d{i}_{Ia}}{dt}=\underset{v_{Ia,m}}{\underbrace{v_D\left(2S_a-S_b-S_c\right)/3}}+v_{Fa,m}-R_1{i}_{Ia}\\ L_1\frac{d{i}_{Ib}}{dt}=\underset{v_{Ib,m}}{\underbrace{v_D\left(2S_b-S_a-S_c\right)/3}}+v_{Fb,m}-R_1{i}_{Ib}\\ L_1\frac{d{i}_{Ic}}{dt}=\underset{v_{Ic,m}}{\underbrace{v_D\left(2S_c-S_a-S_b\right)/3}}+v_{Fc,m}-R_1{i}_{Ic}\end{array}\}.$$

(22)

The VSC DC current $i_D$ is written as

$$i_D=i_{Ia}{S}_a+i_{Ib}{S}_b+i_{Ic}{S}_c.$$

(23)

If the DC bus is connected to another converter buffered by the DC bus capacitor $C_D$, the DC bus voltage $v_D$ is then modeled as

$$C_D\frac{d{v}_D}{dt}=i_o-i_D-\frac{v_D}{R_D}.$$

(24)

Figure 7a displays the VSC and LCL filter model developed in the MATLAB/Simulink environment, where (15), (16), (20), (22), and (23) are implemented. This model is valid when the DC bus voltage is greater than the peak value of the line-to-line grid voltage ${\widehat{V}}_{LL}$. The signal $EN$ is used for the enable ($EN=1$) and disable ($EN=0$) VSC operation. If the VSC is disabled and $v_D\ge {\widehat{V}}_{LL}$, the VSC currents $i_{Ia}$, $i_{Ib}$, and $i_{Ic}$ are kept reset at zero. Meanwhile, the grid currents $i_{ga}$, $i_{gb}$, and $i_{gc}$ circulate through $L_2$, $R_2$, $C_f$, and $R_f$. At the enable time $t_{EN}$, the switching signals $S_a$, $S_b$, and $S_c$ are enabled and the VSC is fully operated. Figure 7b shows the MATLAB/Simulink model of the DC bus voltage $v_D$ in (24), which is kept reset while the VSC is disabled. For the single-stage topology where the VSC is connected to a voltage source, the DC bus voltage equation in (24) is neglected.

Figure 7. MATLAB/Simulink model: (a) the VSC and LCL filter; (b) the DC bus voltage.

3.2. Averaged Circuit Modeling and Current Controller Design

The frequency response of the LCL filter below its resonant frequency is similar to that of the L filter [30]. Moreover, the control bandwidth is selected below the resonant frequency of the LCL filter. Thus, the LCL filter can be approximated as the L filter for design of the current controller. The grid currents can be simplified as

$$\begin{array}{c}{L}_t\frac{d{i}_{ga}}{dt}+R_t{i}_{ga}=v_{Ia,n}-v_{ga,n}\\ L_t\frac{d{i}_{gb}}{dt}+R_t{i}_{gb}=v_{Ib,n}-v_{gb,n}\\ L_t\frac{d{i}_{gc}}{dt}+R_t{i}_{gc}=v_{Ic,n}-v_{gc,n}\end{array}\}$$

(25)

where $L_t=L_1+L_2$, $R_t=R_1+R_2$. The VSC voltages are written by

$$\left[\begin{array}{c}{v}_{Ia,n}\\ v_{Ib,n}\\ v_{Ic,n}\end{array}\right]=\left[\begin{array}{c}{v}_{Ia,m}\\ v_{Ib,m}\\ v_{Ic,m}\end{array}\right]+v_{mn}.$$

(26)

According to (19) $v_{mn}=0$, the grid currents in (25) become

$$\begin{array}{c}{L}_t\frac{d{i}_{ga}}{dt}+R_t{i}_{ga}=v_{Ia,m}-v_{ga,n}\\ L_t\frac{d{i}_{gb}}{dt}+R_t{i}_{gb}=v_{Ib,m}-v_{gb,n}\\ L_t\frac{d{i}_{gc}}{dt}+R_t{i}_{gc}=v_{Ic,m}-v_{gc,n}\end{array}\}.$$

(27)

The variables in (26) are averaged over a sampling period $T_s=f_s$ for continuous-time domain approximation, which becomes

$$\begin{array}{c}{L}_t\frac{d⟨i_{ga}⟩}{dt}+R_t⟨i_{ga}⟩=⟨v_{Ia,m}⟩-⟨v_{ga,n}⟩\\ L_t\frac{d⟨i_{gb}⟩}{dt}+R_t⟨i_{gb}⟩=⟨v_{Ib,m}⟩-⟨v_{gb,n}⟩\\ L_t\frac{d⟨i_{gc}⟩}{dt}+R_t⟨i_{gc}⟩=⟨v_{Ic,m}⟩-⟨v_{gc,n}⟩\end{array}\}$$

(28)

where the brackets ‘⟨ ⟩’ represent the variables averaged over $T_s$. Equation (28) is scaled into the per-unit scale using the base voltage $V_B=I_B{Z}_B$ where $I_B$ is the base current and $Z_B$ is the base impedance, which yields

$$\begin{array}{c}{L}_t^{\prime }\frac{d⟨i_{ga}^{\prime }⟩}{dt}+R_t^{\prime }⟨i_{ga}^{\prime }⟩=⟨v_{Ia,m}^{\prime }⟩-⟨v_{ga,n}^{\prime }⟩\\ L_t^{\prime }\frac{d⟨i_{gb}^{\prime }⟩}{dt}+R_t^{\prime }⟨i_{gb}^{\prime }⟩=⟨v_{Ib,m}^{\prime }⟩-⟨v_{gb,n}^{\prime }⟩\\ L_t^{\prime }\frac{d⟨i_{gc}^{\prime }⟩}{dt}+R_t^{\prime }⟨i_{gc}^{\prime }⟩=⟨v_{Ic,m}^{\prime }⟩-⟨v_{gc,n}^{\prime }⟩\end{array}\}$$

(29)

where symbols ‘ $\prime$ ’ denotes variables in the per-unit scale, and $L_t^{\prime }=L_t/Z_B$ and $R_t^{\prime }=R_t/Z_B$. The grid currents in (29) are transformed to the synchronous reference frame, $dq$ axes, which results in

$$\begin{array}{c}{L}_t^{\prime }\frac{d⟨i_{gd}^{\prime }⟩}{dt}+R_t^{\prime }⟨i_{gd}^{\prime }⟩=⟨v_{Id}^{\prime }⟩-{\widehat{V}}_g^{\prime }+\underset{K_{FW}}{\underbrace{\omega L_t^{\prime }}}⟨i_{gq}^{\prime }⟩\\ L_t^{\prime }\frac{d⟨i_{gq}^{\prime }⟩}{dt}+R_t^{\prime }⟨i_{gq}^{\prime }⟩=⟨v_{Iq}^{\prime }⟩+\underset{K_{FW}}{\underbrace{\omega L_t^{\prime }}}⟨i_{gd}^{\prime }⟩\end{array}\}.$$

(30)

Figure 8 shows the equivalent control block diagram of the grid current in the synchronous reference frame with the per-unit scale. Note that the cross-coupling terms $K_{FW}=\omega L_t^{\prime }$ are due to the Park transformation, which can be decoupled in the control scheme. The delay terms $e^{-s{T}_d}$ represent the sampling delay caused by the digital control scheme and the transport delay caused by the PWM process, where $T_d=2T_s$ for the double update rate PWM is shown in Figure 5 [31]. The decoupled terms leave the currents $i_{gd}^{\prime }$ and $i_{gq}^{\prime }$ are separately controlled. The PI regulator for the fundamental component current is initially designed in the continuous-time domain. The parameters $K_{ih}$ for the resonant controllers are then selected in proportion to the integral gain $K_{i1}$. According to the design methodology in [31], the PI regulator parameters are selected as follows

$$K_p\approx {\omega }_{ci,max}{L}_t^{\prime }$$

(31)

$$K_{iI}\approx \frac{{\omega }_{ci,max}^2}{10}{L}_t^{\prime }$$

(32)

where ${\omega }_{ci,max}$ is the possible maximum cross-over frequency at a given phase margin ${\varphi }_{mi}$. The cross-over frequency ${\omega }_{ci,max}$ is given by

$${\omega }_{ci,max}=\frac{\pi /2-{\varphi }_{mi}}{T_d}.$$

(33)

Figure 8. Equivalent block diagram of the grid current in the synchronous reference frame.

Figure 9a shows the frequency response of the simplified open-loop transfer function with the PI controller and the PIMR controller. The target phase margin is set at ${\varphi }_{mi}={60}^{°}$ with the VSC parameter in Table 1, which results in ${\omega }_{ci,max}=2\pi \left(1111\right)$ rad/s. The PI controller parameters $K_p$ and $K_{i1}$ are determined from (31) and (32). The resonant controllers, orders 6th and 12th, are added to compensate the voltage harmonics, orders 5th, 7th, 11th, and 13th, whose resonant gains are set at $K_{i6}=K_{i12}=K_{i1}/3$. For the PI controller, the DC loop gain of 100 dB is large enough to track the reference currents with a zero steady-state error. However, the loop gains at 300 Hz and 600 Hz are considerably low to reject the voltage harmonic disturbances. For the PIMR controller, the DC loop gain and the loop gains at 300 Hz and 600 Hz are greater than 100 dB. The phase margin ${\varphi }_{mi}={50}^{°}$ of the system with the PIMR controller is still large enough to guarantee the control stability. The actual cross-over frequency ${\omega }_{ci}=2\pi \left(1120\right)$ rad/s is close to the desired value.

Figure 9. Frequency response of the current control loop: (a) simplified open-loop transfer function in synchronous reference frame with the PI controller (black) and the PIMR controller (red); (b) open-loop transfer function in the stationary reference frame.

The current controller is designed based on the simplified model. Stability assessment is necessary before implementation. The stationary reference frame equivalence of the current controller given in (9) and the transfer function of the LCL filter in (11) are used in the open-loop transfer function $G_o^s\left(s\right)$ in the stationary reference frame which is written as

$$G_o^s\left(s\right)=\underset{Controller}{\underbrace{G_{ci}^s\left(s\right)}}\underset{VSC\&PWM}{\underbrace{\frac{V_D}{2}{e}^{-sTd}}}\underset{LCL filter}{\underbrace{G_{LCL}\left(s\right)}}$$

(34)

Figure 9b depicts the frequency response of $G_o^s\left(s\right)$ in the stationary reference frame, where there are three cross-over frequencies ${\omega }_{c1}$, ${\omega }_{c2}$, and ${\omega }_{c3}$. The cross-over frequency near the loop bandwidth ${\omega }_{c1}=2\pi \left(1300\right)$ rad/s slightly shifts from that in the synchronous reference frame due to the presence of the 13th-harmonic peak gain. The phase margin ${\varphi }_{m1}=38°$ at ${\omega }_{c1}$ is still large enough to guarantee control stability. The other two cross-over frequencies ${\omega }_{c2}=2\pi \left(4400\right)$ rad/s and ${\omega }_{c3}=2\pi \left(5760\right)$ rad/s occur around the resonant frequency of the LCL filter ${\omega }_{LCL}$, of which phase margins ${\varphi }_{m2}=36°$ and ${\varphi }_{m3}=110°$ satisfy the stability criterion for the inherent damping of the LCL filter with grid-current feedback control [28].

4. Simulation

4.1. Simulation Structure

Figure 10 shows the simulation model developed in the MATLAB/Simulink environment. The simulation model emulates the experimental system, which is divided into 2 sections: continuous-time domain and discrete-time domain. The continuous-time domain represents the three-phase grid and the VSC power circuits with the switching signals $S_a$, $S_b$, and $S_c$ as the inputs, where the switched-circuit model of the VSC and the LCL filter shown in Figure 7a is adopted. The single-stage topology is considered in this study where the DC bus voltage is supplied by a constant voltage source $V_D$. The DC bus model in Figure 7b is neglected.

Figure 10. MATLAB/Simulink model of the discrete-time controlled 3-phase grid-connected VSC.

The discrete-time domain section emulates the control scheme depicted in Figure 3. The grid voltages $v_{ga}$ and $v_{gb}$, and grid currents $i_{ga}$ and $i_{gb}$ are scaled by the base voltage $V_B$ and base current $I_B$. Then, they are sampled by the ZOHs at the time instance $k$ with the period of $T_s$. This process represents the beginning of each ISR as shown in Figure 5. The discrete-time algorithms for PLL, reference frame transformations, $dq$-axes current control, and the continuous SVM [32] are written in a MATLAB m file, which is executed every sampling period $T_s$ by the interpreted MATLAB function block as shown in Figure 10. The outputs of this interpreted MATLAB function block are the duty ratios $d_a\left(k\right)$, $d_b\left(k\right)$, and $d_c\left(k\right)$, which are delayed by $T_s$. This causes the duty ratios $d_a\left(k\right)$, $d_b\left(k\right)$, and $d_c\left(k\right)$ to be updated at the time instance $k+1$ to compare with the triangular waveform. This waveform has the switching period $T_{sw}$ similar to that in Figure 5, which emulates the PWM process in the DSP. Thus, the controller parameters used in the simulation can be directly transferred to the experimental system if they use the same base units. The variable-step solver ODE45 with the maximum step size of $T_s/400=125$ ns was selected in the Simulink setting. The proposed simulation model developed in the MATLAB/Simulink 2020b is provided in [33].

4.2. Discrete-Time Control Scheme

Figure 11 shows the Park-based PLL the discrete-time domain used for grid synchronization. The grid voltages $v_{ga}^{\prime }$, $v_{gb}^{\prime }$, and $v_{gc}^{\prime }$ are transformed to the $\alpha \beta$ axes using the Clarke transformation. The Park transformation converts the grid voltages to the $dq$ axes, $v_{gd}^{\prime }$ and $v_{gq}^{\prime }$, which are cleaned by the low-pass filters with the constant $T_{PLL}$ for the distorted grid voltage. The integrator with a gain of the nominal grid frequency ${\omega }_{gn}$ estimates the grid voltage angle $\widehat{\theta }$ for the Park transformation. The PI controller regulates the $q$-axis voltage $v_{gqf}^{\prime }$ toward zero, which forces $\widehat{\theta }\cong \theta$, ${\widehat{\omega }}^{\prime }\cong \omega /{\omega }_{gn}$, and $v_{gdf}^{\prime }\cong {\widehat{V}}_g^{\prime }.$ The loop regulator is designed in the continuous-time domain using the symmetrical optimum (SO) method [34]. For simplicity, the low-pass filters and the PI regulators are discretized using the backward difference approximation because the sampling frequency is much greater than the PLL bandwidth. The coefficient for the low-pass filters in the discrete-time domain is given by

$${\alpha }_{PLL}=\frac{T_s}{T_s+T_{PLL}}.$$

(35)

Figure 11. Park-based phase-locked loop in the discrete-time domain for grid synchronization.

The saturation limit on the PI regulator output with an anti-windup is implemented through the correction gain $K_{cPLL}$ which is usually twice the integral gain $K_{iPLL}$ [35]. Meanwhile, the integrator for estimation of the grid voltage angle $\widehat{\theta }$ is discretized with the Tustin approximation with the lowest error. The estimated angle $\widehat{\theta }$ is then used for the axis transformations.

Figure 12 illustrates the discrete-time structure of the PIMR controller for control of the $dq$ axes currents with the controller parameters obtained from the previous section. The PI controller for the fundamental component current is discretized using the backward difference approximation. Anti-windup is also implemented with the correction gain $K_c$. For the resonant regulators, the forward difference approximation is used for the forward integrator, and the backward difference approximation is adopted for the feedback integrator [36]. This discretization technique is simple and does not create algebraic loops. The resonant frequency of the discrete controller is shifted from that in the continuous-time domain, especially at a higher frequency. However, it was analyzed in our previous work [37] that the shifted resonant frequency is marginal and creates an insignificant effect on the control performance. The two integrators can be discretized with the backward difference with an added one-step delay in the feedback path [36]. Discretization of both with the Tustin approximation causes a large shift of the resonant peak and poses implementation problems due to algebraic loops [36]. The resonant frequencies at the harmonic orders 6th and 12th are kept tuned with the estimated frequency ${\widehat{\omega }}^{\prime }$ from PLL for grid frequency adaptation. The fundamental current control has the intrinsic frequency adaptation capability through the Park transformation. Table 3 summarizes the parameters of the PLL and PIMR controller parameters.

Figure 12. Discrete-time implementation of the PIMR controller.

Table 3. Parameters of the discrete-time controllers.

Parameters	PLL	$dq$ Current Control
Bandwidth	61.3 Hz	1111 Hz
Phase margin	45°	60°
Proportional gain, $K_p$	1.2247	0.4922
Integral gain, $K_i{T}_s$	0.0096	0.0172
Correction gain, $K_c$	0.0192	0.0344
Resonant gains, $K_{i6}$ and $K_{i12}$	-	114.5518
Low-pass filter, $\alpha$	0.0045	-

5. Implementations

Figure 13 illustrates the experimental system. The power circuit was firstly modeled in an OPAL-RT OP4510 HiL real-time simulator with a time step of 220 ns to validate the discrete-time control scheme, which was implemented on a Texas Instruments TMS320F28379D 32-bit DSP controller as shown in Figure 13a. The emulated grid voltages and currents in the HiL system had the identical sensitivities to those used in the hardware implementation system as depicted in Figure 13b. A deadtime of 1 µs in each VSC leg was configured in the DSP. The VSC was constructed from Infineon IKW25T120 insulated-gate bipolar transistors (IGBTs) with isolated gate drivers from Texas Instruments ISO5851. Amorphous C cores (AMCC6.3 equivalence) were used for the construction of the inductors $L_1$ and $L_2$ of the LCL filter. The VSC was connected to a Chroma 61,860 60-kVA grid simulator. The DC bus was supplied to a Chroma 62150H-1000S DC power supply, 15 kW 0–1000 V, for the inverter operation. The discrete-time control scheme for the hardware implementation was identical to the HiL-based validation system. The ADC voltage range of this DSP is between 0 V to 3 V. Hall-effect current sensors, LEM HLSR 10-P/SP33, were used for measurement of the grid currents $i_{ga}$ and $i_{gb}$. The grid voltage sensors were constructed from voltage divider circuits with AMC1200 isolation amplifiers. In this prototype, the line-to-line voltages $v_{gab}$ and $v_{gbc}$ were measured, of which the instantaneous voltage vector was shifted by $-pi/6$ to be in the same angle with the instantaneous voltage vector of the phase voltage vector. A voltage reference, REF2030, provided a 1.50 V offset voltage for the grid current and grid voltage sensors.

Figure 13. Experimental system of the three-phase VSC: (a) HiL-based implementation; (b) hardware implementation.

The measured voltages and currents were scaled into the per-unit system with the appropriate scaling factors as illustrated in Figure 14. In this example, a grid current with the peak value of $I_B$ is measured by a current sensor with the sensitivity of $K_{Ti}$. An offset voltage $V_{OF,i}$ is added to the sensor output to accommodate the 0-$V_{ADC,max}$ input range of the ADC, where $V_{ADC,max}$ is the maximum input voltage of the ADC, normally 3 V or 3.3 V. This translates to decimal values of 0 to $\left(2^{N_{ADC}}-1\right)$, where $N_{ADC}$ is the ADC bit number. The ADC output that is equivalent in decimal is then normalized by $2^{N_{ADC}}$. The offset is now equivalent to $V_{OF,i}/V_{ADC,max}$, which is subsequently removed in the software. The normalized signal with offset removal is multiplied by a scaling factor to have a unity amplitude at the base value. The numerical notation in the DSP can be in the signed fixed-point representation or the floating-point format. Scaling of the grid voltage has the same process as the grid current. No offset removal is required for the DC bus voltage, while the other procedures are similar to those of the grid voltage and current. In general, the signal scaling factor is given by

$$K_s=\frac{V_{ADC,max }}{\left(Sensor Senitivity\right)\times \left(Base Value\right)}.$$

(36)

Figure 14. Grid current conversion and scaling process for the experimental system.

The discrete-time control algorithm implemented in the MATLAB m file was manually translated to the C language for the DSP with the same controller parameters. Thus, the simulation and the experiment are closely related. However, there is a code generation tool for this DSP family with an additional licensing cost. The internal signals of the discrete-time control scheme implemented on the DSP were converted to 0–3.0 V analog signals via two embedded 12-bit digital-to-analog converters (DACs) for monitoring on an oscilloscope.

6. Simulation and Experimental Validations

The DC bus was connected to the Chroma 62150H-1000S DC power supply with $v_D=700$ V. The grid voltage waveforms were set to be sinusoidal at the nominal phase voltage of 230 V, 50 Hz. The PI controllers for the fundamental component were enabled without the harmonic compensators. The reference currents were set to $i_{gd,ref}^{\prime }=1.0$ p.u. and $i_{gq,ref}^{\prime }$= 0 p.u. This caused the VSC to inject an active power of 5 kW into the grid. A simulation platform 1 of the VSC was developed in the Simscape Electrical of the MATLAB/Simulink 2020b, which is provided in [33]. Figure 15 compares the experiment and simulation results for the VSC-side currents $i_{Ia}$, $i_{Ib}$, and $i_{Ic}$, and the grid currents $i_{ga}$, $i_{gb}$, and $i_{gc}$. It can be observed the experimental VSC-side currents $i_{Ia}$, $i_{Ib}$, and $i_{Ic}$ of the HiL and hardware implementations have the current envelops due to the switching in close agreement with those of the proposed simulation method and the simulation platform 1. This confirms that the switched circuit modeling technique is applicable for the proposed platform. The waveforms of the experimental and simulation grid currents $i_{ga}$, $i_{gb}$, and $i_{gc}$ are near sinusoidal as the LCL filter absorbs the switching current ripples.

Figure 15. Simulation and experimental results of the VSC without the harmonic compensators under the sinusoidal voltages: (a) Proposed simulation method and simulation platform 1; (b) HiL-based experiment and hardware implementation.

Voltage harmonics listed in Table 4 were added to the fundamental component, which resulted in a total harmonic distortion (THD) of 4.69%. Figure 16 shows the grid voltages and the grid currents without the harmonic compensators (HC). The experimental results from the HiL and hardware implementations closely agree with the proposed simulation method and simulation platform 1. The grid voltage harmonics make the grid currents even more distorted with a THD of 10.84%. The PIMR controller was adopted for control of the VSC under the distorted grid. The PIMR controller is capable of mitigating the grid voltage distortion as depicted in Figure 17. The grid current waveforms in the steady state are near sinusoidal. The control performance is maintained when the frequency changes from 47 Hz to 50 Hz and from 50 Hz to 52 Hz through the estimated frequency ${\widehat{\omega }}^{\prime }$ from the PLL. This is the allowable frequency range for a VSC connected to the Thailand low-voltage grid [38]. Figure 18 compares the current harmonic spectrum of the VSC at the nominal power of 5 kW under the distorted grid voltage. For the PI controller without the HCs, the current harmonics, orders 5th and 7th, exceed the IEEE 1547 standard [39] and there is a significant presence of orders 11th and 13th, which reflects the grid voltage harmonics. Moreover, the 2nd harmonic current also exceeds the IEEE 1547 standard, which is believed to be due to DC offsets in the current measurement [40]. The PIMR controller effectively suppresses the grid voltage harmonics as the current harmonic orders 5th, 7th, 11th, and 13th are attenuated close to zero. The grid current with the PIMR controller has a THD of 1.08% and complies with the IEEE 1547 standard.

Table 4. Line-neutral voltage harmonics.

$V_1$	$V_5$	$V_7$	$V_{11}$	$V_{13}$	THD
220 Vrms	4%	2%	1%	1%	4.69%

Figure 16. Simulation and experimental results of the VSC without the harmonic compensators under the distorted voltages.

Figure 17. Simulation and experimental results of the VSC with the PIMR controller under the distorted voltages and frequency changes.

Figure 18. Current harmonic spectrum of the VSC at the nominal power of 5 kW under the distorted grid.

Dynamic performance of the VSC with the PIMR control scheme was validated with step changes in the reference currents as shown in Figure 19. The reference currents are initially set to $i_{gd,ref}^{\prime }=0$ p.u. and $i_{gq,ref}^{\prime }$= 0 p.u.; the reference currents are changed to $i_{gd,ref}^{\prime }=0.7$ p.u. and $i_{gq,ref}^{\prime }$= 0 p.u., and $i_{gd,ref}^{\prime }=i_{gq,ref}^{\prime }=0.7$ p.u., respectively. The experimental results of the grid currents at the steady-state conditions again are close to the proposed simulation method and simulation platform 1. The rising slope of the experimental $i_{ga}$ and $i_{gc}$ for the HiL and hardware implementations at the step changes of the reference currents as circled in Figure 19 are slightly lower than that of the simulation. This is believed to be due to voltage drops in the IGBTs and the grid simulator’s internal impedance, which were neglected in the simulation.

Figure 19. Transient performance of the VSC with the PIMR controller.

It is demonstrated that the proposed simulation technique mimics the converter and control scheme very closely. The results of the proposed simulation technique closely agreed with the results of the simulation platform 1 using the Simscape Electrical toolboxes in the MATLAB/Simulink 2020b, and with the experimental results of the HiL and hardware implementations. The discrete-time control scheme implemented in the interpreted MATLAB function can be easily translated to the C-code for the DSP, from which expensive RCP systems and Simulink coding toolboxes are not required. Furthermore, a HiL simulator is not necessary for the development of a low-power VSC (say up to 20 kW). This platform can be applied to other topologies. Our previous works in interleaved DC-DC converters [41], single-phase stand-alone inverter [42], and single-phase grid-connected VSCs [37,43] were developed using the proposed platform. However, validation of the control scheme with a HiL simulator or a laboratory-scale VSC is a normal practice for the development of a large power converter.

7. Conclusions

We propose a simulation technique that emulates the DSP-based control operation of the grid-connected converters. The key features of the proposed platform can be listed as follows.

• Switched-circuit modeling of the power circuit is simulated in the continuous-time domain with the physical unit scale.
• The discrete-time control scheme in the per-unit scale is written in a MATLAB m file function which is executed in synchronous with the switching period.
• The m-file script is then easily translated to the C code for the TMS320F28379D DSP with the same controller parameters.

The proportional-integral with multi-resonant controllers at harmonic orders 6th and 12th in the synchronous reference frame was selected in the study to attenuate the grid voltage harmonics. The proposed platform was validated with an OPAL-RT OP4510 HiL real-time simulator and with 5-kVA 3-phase LCL-filtered grid-connected VSC. The experimental results from the HiL simulator and the VSC closely agree with the simulation. The multi-resonant controllers were found to effectively suppress the grid voltage harmonic orders 5th, 7th, 11th, and 13th with the THD of 4.69%. The grid current was found to comply with the IEEE 1547 standard with the THD of 1.08%. The proposed platform requires a basic package of MATLAB/Simulink without dedicated power electronic toolboxes and real-time prototyping systems.