# Cascaded Voltage and Current Control for a Dual Active Bridge Converter with Current Filters

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Materials and Methods

#### 2.1. Modulation Scheme

#### 2.2. Current Control Loop

**The authors propose to choose the integral time of the controller**${T}_{\mathrm{I},\mathrm{req}}$

**in such a way that the decade containing the controller corner frequency**${\omega}_{\mathrm{c}}$ (Equation (28))

**is separated by at least one whole decade from the one containing the gain margin cutoff frequency**(Equation (24))

**calculated for a frequency response of the plant**${G}_{\mathrm{P}}\left(j\omega \right)$

**.**In the next paragraphs, we explain why such a tuning rule was chosen.

**Step 1:**Proportional gain of the controller is set to unity (${k}_{\mathrm{P}1}=1$) and the integral time is set to the requested value (${T}_{\mathrm{I}}={T}_{\mathrm{I},\mathrm{req}}$). For such a case the Bode plots of the open-loop frequency response ${G}_{\mathrm{OL}}\left(j\omega \right)$ are drawn. Based on that, the gain margin cutoff frequency ${\omega}_{\mathrm{gc}}$ is determined according to Equation (24) and a gain margin for the unity gain is calculated as:$${G}_{\mathrm{m},{k}_{\mathrm{P}1}}=1/\left|{G}_{\mathrm{OL}}\left(j{\omega}_{\mathrm{gc}}\right)\right|.$$**Step 2:**Based on the calculated gain margin value it can be determined how to set the controller gain in order to achieve the requested gain margin of the open-loop system as follows:$${k}_{\mathrm{P}}=\frac{{G}_{\mathrm{m},{k}_{\mathrm{P}1}}}{{G}_{\mathrm{m},\mathrm{req}}}.$$

#### 2.3. Voltage Control Loop

**Hence, for a given integral time value of the controller**${T}_{\mathrm{I},\mathrm{req}}$

**the proportional gain value**${k}_{\mathrm{P}}$

**is chosen in such a way that the phase margin calculated for the open-loop system frequency response is maximized.**

**Step 1:**Proportional gain of the controller is set to unity (${k}_{\mathrm{P}1}=1$) and the integral time is set to the requested value (${T}_{\mathrm{I}}={T}_{\mathrm{I},\mathrm{req}}$). For such a case the Bode plots of the open-loop frequency response ${G}_{\mathrm{OL}}\left(j\omega \right)$ are drawn. Based on that it is found for which frequency the phase of the drawn response is maximal:$${\omega}_{\phi \mathrm{c},\mathrm{req}}=arg\underset{\omega \in \phantom{\rule{-0.166667em}{0ex}}R}{max}\angle G\left(j\omega \right).$$**Step 2:**An aim of the algorithm is to find such a proportional gain value, that the phase margin cutoff frequency (Equation (43)) for the resulting open-loop system equals the value (Equation (45)), as it assures the possibly maximal phase margin value. In order to do so, an amplitude of the open-loop frequency response for the unity gain should be read from the drawn characteristic at the frequency (Equation (45)):$${G}_{\phi ,{k}_{\mathrm{P}1}}=\left|{G}_{\mathrm{OL}}\left(j{\omega}_{\phi \mathrm{c},\mathrm{req}}\right)\right|.$$**Step 3:**Based on that, the proportional gain value can be calculated in such a way that the frequency response gain for the requested frequency equals unity, assuring that the phase margin calculation point lies exactly at the maximum of the phase characteristic:$${k}_{\mathrm{P}}=\frac{1}{{G}_{\phi ,{k}_{\mathrm{P}1}}},$$

## 3. Results

^{TM}, which is mounted on the so-called controlCARD [21]. Both H-bridges were built based on the SiC-based MOSFET power modules CCS050M12CM2 from CREE

^{TM}[22], which are mounted on the heatsink shown in the top right of the Figure 15. The modules are supplied via gate driver boards CGD15FB45P1 from CREE

^{TM}[23], which are soldered on the top of power modules. The gate driver boards are connected with the DC-link capacitors (see ${\mathrm{C}}_{\mathrm{f}1}$ and ${\mathrm{C}}_{\mathrm{f}2}$ in Figure 1) using copper plates. The AC sides of the H-bridges are connected via transformer and auxiliary inductors, which are marked in Figure 15 as well.

^{TM}using the P5205A and TCP0030A probes. All the tests were conducted at the same input voltage value, which is regulated by the active rectifier at 670 V. Similarly, the same load value of 16 $\Omega $ was used in each test, and an amount of output current and power was changed by the setting of different voltage values at the DAB converter output. Each test lasts 400 ms and consists of the following phases:

**Phase 0: (first 40 ms)**converter is in-active and PWM signals are not generated;**Phase 1: (110 ms)**the control algorithm and PWM generation are activated in the same time, the voltage reference value is set to the final value, the load is switched off;**Phase 2: (155 ms)**the load is rapidly switched on via relay;**Phase 3: (95 ms)**the load is rapidly switched off via relay.

## 4. Discussion

- The inner current control loop proposed in [11] uses the input filter current signal as the feedback, whereas the solution presented here uses the output filter current signal instead. Usage of the output current signal has some important advantage. In both solutions the voltage controller calculates at its output the reference value for the output filter current. Hence, in [11] this reference value needs to be further converted to the corresponding reference current value at the input of the converter (since this is the actual controlled signal). This calculation facilitates the value of the so-called voltage conversion ratio, which requires a direct measurement of the DC-link voltage of the secondary-side H-bridge (see ${v}_{\mathrm{DC}2}\left(t\right)$ in Figure 1). On the other hand, the main task of the voltage control system is to regulate the voltage at the converter’s output, i.e., the signal ${v}_{\mathrm{out}}\left(t\right)$. It would then require three voltage sensors to perform this task (the third sensor is needed to measure the DC-link voltage of the primary-side H-bridge ${v}_{\mathrm{DC}1}\left(t\right)$, which is also needed for the voltage conversion ratio calculation). The author of [11] solved this problem by using the DC-link voltage signal ${v}_{\mathrm{DC}2}\left(t\right)$ as the feedback in the voltage control loop instead of the ${v}_{\mathrm{out}}\left(t\right)$. Nevertheless, these two signals are equal only during the steady-state operation, which in consequence must deteriorate the voltage control performance during transients, especially the load changes (which is the most important test case for the voltage regulatory system). The solution presented here does not posses this drawback. The measurement of the DC-link voltage of the secondary-side H-bridge ${v}_{\mathrm{DC}2}\left(t\right)$ is not needed and there is a possibility to directly measure and control the output voltage signal ${v}_{\mathrm{out}}\left(t\right)$ without increasing the number of the voltage sensors above two (the second sensor is needed to measure the DC-link voltage of the primary-side H-bridge ${v}_{\mathrm{DC}1}\left(t\right)$ for the current limitation purposes, see Equations (13)–(15) as reference);
- The solution presented in [11] does not offer any DC-bias current cancellation algorithm. As already mentioned in the introductory section, the presence of this feature is very important to achieve the industrial quality of the controlled converter. The solution presented here does offer this functionality, which is clearly an advantage;
- In [11] there are moving average filters introduced in feedback signal paths of both current and voltage control loops. It introduces a delay of 10 switching periods, which greatly deteriorates an effective bandwidth of the voltage control system. In the presented solution there is no such additional filters and the sampling rate of the controller equals the switching frequency, which increases the dynamic performance of the system;
- The presented solution facilitates the modified modulation scheme and its features were used to develop a novel modeling method for the converter’s dynamics. This method is very simple and straightforward, especially when compared to the small-signal averaging method applied in [11]. This method is one of the most important contributions of this paper;
- Thanks to the above-mentioned modeling method, it was possible to develop a linear model of the converter dynamics in the s-domain, which is valid in the whole operational range of the converter (i.e., no linearization around an operational point is needed). Based on that, it was possible to develop some straightforward tuning rules for both current and voltage control loops. In each case it was possible to reduce the tuning process of the controller parameters to a single degree of freedom. The tuning process of each controller is then reduced to a choice of the desired trade-off between the dynamics of the system responses and robustness. It has great practical importance, as no model is perfect and it is often the case that the system designed based on simulations needs to be further re-tuned, as the experimental results normally differ from the theoretical ones. This is obvious, as in a real system there are always some parameter tolerances, measurement noises, and some characteristics which could not be perfectly modeled. The presented tuning rules are very convenient to use in such situations and they are the second important contribution of this paper;
- The last important contribution is an experimental illustration of the non-linear effects, which can occur if the system is operated near its current limitation. It demonstrates that sometimes an effective control system can not be designed by simply optimizing the simulated responses, as the robustness is also a very important feature and its required level is often very hard to predict theoretically. Hence, the presented results proved an usefulness of having some one dimensional tuning rules rather than a single set of parameters, which were derived based on some performance indexes and using the simulation or analytical tools.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## Abbreviations

AC | Alternating Current |

DAB | Dual Active Bridge |

DC | Direct Current |

DPS | Dual Phase Shift (modulation) |

DRES | Dual Rising Edge Shift (algorithm) |

DSSPS | Double-Sided Single Phase Shift (modulation) |

EPS | Extended Phase Shift (modulation) |

PCB | Printed Circuit Board |

PWM | Pulse Width Modulation |

SST | Solid State Transformer |

SPS | Single Phase Shift (modulation) |

TPS | Triple Phase Shift (modulation) |

ZOH | Zero Order Hold |

## Appendix A

Name | Symbol | Value | Unit |
---|---|---|---|

Input voltage range | ${V}_{\mathrm{in}}$ | $650\dots 700$ | V |

Output voltage range | ${V}_{\mathrm{out}}$ | $80\dots 410$ | V |

Output current range | ${I}_{\mathrm{out}}$ | $-25\dots 25$ | A |

Switching frequency | ${f}_{\mathrm{sw}}$ | 40 | kHz |

Drain-source on-state resistance of MOSFETs | ${\mathrm{R}}_{\mathrm{DSon}}$ | 25 | m$\Omega $ |

Equivalent circuit inductance | ${\mathrm{L}}_{\mathrm{eq}}$ | $136.7$ | $\mu $H |

Auxiliary inductance in series with primary transformer winding | ${\mathrm{L}}_{\mathrm{aux}}$ | $117.7$ | $\mu $H |

Transformer turns ratio | ${\mathrm{N}}_{\mathrm{t}}$ | $7/4$ | − |

Transformer magnetizing inductance | ${\mathrm{L}}_{\mu}$ | $2.4$ | mH |

Leakage inductance of primary transformer winding | ${\mathrm{L}}_{\sigma 1}$ | $9.5$ | $\mu $H |

Leakage inductance of secondary transformer winding | ${\mathrm{L}}_{\sigma 2}$ | $3.1$ | $\mu $H |

Resistance of primary transformer winding | ${\mathrm{R}}_{1}$ | $21.6$ | m$\Omega $ |

Resistance of secondary transformer winding | ${\mathrm{R}}_{2}$ | $12.4$ | m$\Omega $ |

Current filters’ parameters | ${\mathrm{C}}_{\mathrm{f}1},\phantom{\rule{3.33333pt}{0ex}}{\mathrm{C}}_{\mathrm{f}2}$ | 200 | $\mu $F |

${\mathrm{R}}_{\mathrm{f}1},\phantom{\rule{3.33333pt}{0ex}}{\mathrm{R}}_{\mathrm{f}2}$ | 165 | m$\Omega $ | |

${\mathrm{L}}_{\mathrm{f}1\mathrm{a}},\phantom{\rule{3.33333pt}{0ex}}{\mathrm{L}}_{\mathrm{f}2\mathrm{a}}$ | $22.0$ | $\mu $H | |

${\mathrm{L}}_{\mathrm{f}1\mathrm{b}},\phantom{\rule{3.33333pt}{0ex}}{\mathrm{L}}_{\mathrm{f}2\mathrm{b}}$ | $2.8$ | $\mu $H | |

Capacitance of input and output capacitors | ${\mathrm{C}}_{\mathrm{in}},\phantom{\rule{3.33333pt}{0ex}}{\mathrm{C}}_{\mathrm{out}}$ | 600 | $\mu $F |

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**Figure 2.**Exemplary waveforms explaining the used modulation scheme during transition of the phase shift value: (

**a**) AC voltages when a basic Double-Sided Single Phase Shift (DSSPS) modulation is applied, (

**b**) AC voltage waveforms when the Dual Rising Edge Shift (DRES) algorithm for DC-bias cancellation is additionally applied, and (

**c**) transformer current waveforms.

**Figure 5.**Schematic of the continuous-time equivalent model for the current control loop in s domain.

**Figure 6.**The current control loop characteristics at

**constant gain margin**of ${G}_{\mathrm{m},\mathrm{req}}=2.75$ and for

**various controller integral time**${T}_{\mathrm{I}}$ values: (

**a**,

**c**) amplitude and phase Bode plots of the open-loop system frequency response, (

**b**) amplitude Bode plot of the closed-loop system frequency response, (

**d**) amplitude Bode plot of the disturbance frequency response of the system, (

**e**) response of the system on a unit step of the reference signal, (

**f**) response of the system on a unit step of the disturbance signal.

**Figure 7.**The current control loop characteristics at

**constant integral time**of ${T}_{\mathrm{I}}=1.0\times {10}^{-6}$ and for

**various gain margin**${G}_{\mathrm{m},\mathrm{req}}$ values: (

**a**,

**c**) amplitude and phase Bode plots of the open-loop system frequency response, (

**b**) amplitude Bode plot of the closed-loop system frequency response, (

**d**) amplitude Bode plot of the disturbance frequency response of the system, (

**e**) response of the system on a unit step of the reference signal, (

**f**) response of the system on a unit step of the disturbance signal.

**Figure 10.**Comparison of the Bode diagrams for the approximated and original frequency responses of the current control system: (

**a**,

**c**) amplitude and phase characteristics of the closed-loop frequency responses, (

**b**,

**d**) amplitude and phase characteristics of the disturbance frequency responses.

**Figure 11.**Block diagram of the voltage control loop: (

**a**) diagram illustrating the real signal flow in the system, (

**b**,

**c**) consecutive stages of the diagram transformation.

**Figure 12.**The voltage control loop characteristics for

**various integral time**${T}_{\mathrm{I}}$ values between $1.0\times {10}^{-3}$ s and $3.2\times {10}^{-3}$ s and for proportional gain ${k}_{\mathrm{P}}$ calculated to maximize the open-loop system phase margin: (

**a**,

**c**) amplitude and phase Bode plots of the open-loop system frequency response, (

**b**) amplitude Bode plot of the closed-loop system frequency response, (

**d**) amplitude Bode plot of the disturbance frequency response of the system, (

**e**) response of the system on a unit step of the reference signal, (

**f**) response of the system on a unit step of the disturbance signal.

**Figure 13.**Comparison of the control system responses obtained with numerical simulation model and analytical models presented in this paper: (

**a**) current control loop, step response on reference signal, (

**b**) voltage control loop, step response on reference signal, (

**c**) current control loop, step response on disturbance signal, (

**d**) voltage control loop, step response on disturbance signal.

**Figure 15.**Laboratory prototype of the Dual Active Bridge (DAB) converter with current current filters.

**Figure 16.**Experimental results for controllers tuned according to parameters (31)–(33) and (48), (49): reference voltage value for the active rectifier ${v}_{\mathrm{in},\mathrm{ref}}=670\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$,

**reference output voltage value for the DAB converter**${v}_{\mathrm{out},\mathrm{ref}}=200\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, additional current limitation ${I}_{\mathrm{spec}}=25\phantom{\rule{3.33333pt}{0ex}}\mathrm{A}$, resistive load $\mathrm{R}=16\phantom{\rule{3.33333pt}{0ex}}\Omega $.

**Figure 17.**Experimental results for controllers tuned according to parameters (Equations(Equations (31)–(33)) and Equations (48) and (49): reference voltage value for the active rectifier ${v}_{\mathrm{in},\mathrm{ref}}=670\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$,

**reference output voltage value for the DAB converter**${v}_{\mathrm{out},\mathrm{ref}}=325\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, additional current limitation ${I}_{\mathrm{spec}}=25\phantom{\rule{3.33333pt}{0ex}}\mathrm{A}$, resistive load $\mathrm{R}=16\phantom{\rule{3.33333pt}{0ex}}\Omega $.

**Figure 18.**Experimental results for controllers tuned according to parameters (Equations (31)–(33)) and Equations (48) and (49): reference voltage value for the active rectifier ${v}_{\mathrm{in},\mathrm{ref}}=670\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$,

**reference output voltage value for the DAB converter**${v}_{\mathrm{out},\mathrm{ref}}=350\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, additional current limitation ${I}_{\mathrm{spec}}=25\phantom{\rule{3.33333pt}{0ex}}\mathrm{A}$, resistive load $\mathrm{R}=16\phantom{\rule{3.33333pt}{0ex}}\Omega $.

**Figure 19.**Experimental results for

**voltage controller tuned with reduced dynamics**: reference voltage value for the active rectifier ${v}_{\mathrm{in},\mathrm{ref}}=670\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$,

**reference output voltage value for the DAB converter**${v}_{\mathrm{out},\mathrm{ref}}=350\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, additional current limitation ${I}_{\mathrm{spec}}=25\phantom{\rule{3.33333pt}{0ex}}\mathrm{A}$, resistive load $\mathrm{R}=16\phantom{\rule{3.33333pt}{0ex}}\Omega $.

**Figure 20.**Experimental results for

**voltage controller tuned with reduced dynamics**: reference voltage value for the active rectifier ${v}_{\mathrm{in},\mathrm{ref}}=670\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$,

**reference output voltage value for the DAB converter**${v}_{\mathrm{out},\mathrm{ref}}=200\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, additional current limitation ${I}_{\mathrm{spec}}=25\phantom{\rule{3.33333pt}{0ex}}\mathrm{A}$, resistive load $\mathrm{R}=16\phantom{\rule{3.33333pt}{0ex}}\Omega $.

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## Share and Cite

**MDPI and ACS Style**

Gierczynski, M.; Grzesiak, L.M.; Kaszewski, A.
Cascaded Voltage and Current Control for a Dual Active Bridge Converter with Current Filters. *Energies* **2021**, *14*, 6214.
https://doi.org/10.3390/en14196214

**AMA Style**

Gierczynski M, Grzesiak LM, Kaszewski A.
Cascaded Voltage and Current Control for a Dual Active Bridge Converter with Current Filters. *Energies*. 2021; 14(19):6214.
https://doi.org/10.3390/en14196214

**Chicago/Turabian Style**

Gierczynski, Michal, Lech M. Grzesiak, and Arkadiusz Kaszewski.
2021. "Cascaded Voltage and Current Control for a Dual Active Bridge Converter with Current Filters" *Energies* 14, no. 19: 6214.
https://doi.org/10.3390/en14196214