# Analysis of dc-Link Voltage Switching Ripple in Three-Phase PWM Inverters

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Basic Inverter Equations

#### 2.1. System Configuration

_{dc}) via a dc source impedance representing an inductive filter (L) and/or an equivalent series resistance (R). The parallel capacitor (C) is connected to the dc bus to smooth the voltage ripple. The balanced load currents i

_{1}, i

_{2}, and i

_{3}are supposed to be sinusoidal (switching ripple is now neglected) and the output phase angle φ is treated as a degree of freedom.

_{0}normalized by the dc supply voltage V; that is, m = V

_{0}/V.

_{0}and φ are the output current amplitude and the phase angle between the phase voltage and current, respectively.

#### 2.2. Inverter Input Current Components

_{dc}, which comes from the dc supply, and the high-frequency component ∆i(t) [15], which is bypassed through the dc-link capacitor. Thus, the instantaneous input current can be expressed as:

_{sw}can be obtained on the basis of the input/output power balance considering Equations (1) and (2), giving:

_{k}:

#### 2.3. Space Vector PWM

_{sw}and the volt-second balance is maintained by choosing an appropriate application time for these vectors. In the case of symmetric SV-PWM, it is enough to determine the sequence in one half of the switching period (T

_{sw}/2) since it will be symmetrically repeated in the next half.

_{0}of the null voltage vector is equally shared between the two zero switching states 000 and 111 (centered modulation). The limit of the linear modulation range is m ≤ m

_{max}= 1/$\sqrt{3}$, where m

_{max}is given by the generalized expression for k phases m

_{max}= [2 cos(π/2k)]−1, as stated in [23].

## 3. dc-Link Voltage Ripple Evaluation

#### 3.1. dc-Link Voltage Components

_{dc}and the voltage drop on the dc source resistance R:

_{pp}of the high-frequency (switching frequency) dc-link voltage ripple component can be defined as the difference between its maximum and minimum value within the switching period:

#### 3.2. Peak-to-Peak Voltage Ripple Evaluation

_{pp}, the input current switching frequency component, circulating through the dc-link capacitor C, has to be estimated first. Assuming that the capacitive reactance 1/ω

_{sw}C dominates the equivalent dc-link RL impedance (at the switching frequency ω

_{sw}= 2πf

_{sw}= 2π/T

_{sw}), the whole current component Δi circulates through the dc-link capacitor. In this case, the corresponding dc voltage excursion can be determined by integrating Δi over the specific application time interval t

_{pp}, determined by the space vector Equations (8)–(10). An effective simplification is obtained by considering Δi constant (ΔI) within the application time interval, leading to:

_{dc}, two different cases can be distinguished according to Figure 3. The actual peak-to-peak dc-link voltage ripple amplitude ∆v

_{pp}can be obtained by merging the results corresponding to these two cases.

#### 3.2.1. Case A—Evaluation in the Range i_{1} ≥ I_{dc}

_{pp}are depicted in Figure 3, together with the instantaneous input current i(t). According to Figure 3 (left) and considering the application interval t

_{pp}= t

_{0}(bold pink trace), the peak-to-peak voltage ripple can be written on the basis of Equation (14) as

#### 3.2.2. Case B—Evaluation in the Range i_{1} < I_{dc}

_{pp}= t

_{0}/2 + t

_{1}(bold pink trace), the peak-to-peak voltage ripple can be written on the basis of Equation (14) as:

#### 3.2.3. Merging Cases A and B

_{pp}is obtained by merging the results corresponding to cases A and B:

#### 3.3. Maximum Peak-to-Peak Voltage Ripple

_{pp}(ϑ) has a wide excursion, generally ranging between 0 and 0.25, with higher values corresponding to the higher load phase angles. The maximum of the normalized peak-to-peak voltage switching ripple amplitude (Equation (21)) is obtained as a function of the modulation index over the period $\vartheta $ = [0, 60°]. Different traces are depicted in Figure 5 considering different output phase angles.

## 4. Guidelines for Designing the dc-Link Capacitor

_{max}= 0.577), the following simplification is introduced:

## 5. Numerical and Experimental Results

_{sw}= 2.5 kHz. The simulation circuit parameters summarized in Table 1 are set in order to match the corresponding experimental setup parameters. For the experimental verification, two different output phase angles ($\phi $ = 0 and $\phi $ = 50°) have been obtained using two different loads.

_{pp}/2(t) (red traces) are shown together with the instantaneous dc-link voltage switching ripple ∆v(t) (blue trace) over a fundamental period (T = 20 ms). Two values of the output phase angles $\phi $ = 0 and $\phi $ =50° are considered (left and right column, respectively) and four values of the modulation index (m = 0.25, 0.33, 0.5 and 0.577; from top to bottom) to cover the whole modulation range.

_{pp}/2(t)) provided by the DSP board and displayed using DAC block with a proper voltage scaling.

## 6. Conclusions

## Author Contributions

## Conflicts of Interest

## References

- Holmes, G.D.; Lipo, T.A. Pulse Width Modulation for Power Converters: Principles and Practice; IEEE Series on Power Engineering; John Wiley and Sons: Piscataway, NJ, USA, 2003. [Google Scholar]
- Hava, A.M.; Kerkman, R.J.; Lipo, T.A. Carrier-based PWM-VSI overmodulation strategies: Analysis, comparison, and design. IEEE Trans. Power Electron.
**1998**, 13, 674–689. [Google Scholar] [CrossRef] - Broeck, H.V.D.; Skudelny, H.C.; Stanke, G.V. Analysis and Realization of a Pulsewidth Modulator Based on Voltage Space Vectors. IEEE Trans. Ind. Appl.
**1988**, 24, 142–150. [Google Scholar] [CrossRef] - Grandi, G.; Loncarski, J. Evaluation of current ripple amplitude in three-phase PWM voltage source inverters. In Proceedings of the 8th IEEE Conference on Compatibility and Power Electronics (CPE), Ljubljana, Slovenia, 5–7 June 2013. [Google Scholar]
- Grandi, G.; Loncarski, J.; Dordevic, O. Analysis and comparison of peak-to-peak current ripple in two-level and multilevel PWM inverters. IEEE Trans. Ind. Electron.
**2015**, 62, 2721–2730. [Google Scholar] [CrossRef] - Grandi, G.; Loncarski, J.; Rossi, C. Comparison of peak-to-peak current ripple amplitude in multiphase PWM voltage source inverters. In Proceedings of the 15th IEEE Conference on Power Electronics and Applications (EPE), Lille, France, 3–5 September 2013. [Google Scholar]
- Jiang, D.; Wang, F. Current-ripple prediction for three-phase PWM converters. IEEE Trans. Ind. Appl.
**2014**, 50, 531–538. [Google Scholar] [CrossRef] - Bierhoff, M.; Brandenburg, H.; Fuchs, F.W. An analysis on switching loss optimized PWM strategies for three-phase PWM voltage source converters. In Proceedings of the 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON), Taipei, Taiwan, 5–8 November 2007. [Google Scholar]
- Vujacic, M.; Srndovic, M.; Hammami, M.; Grandi, G. Evaluation of DC voltage ripple in single-phase H-bridge PWM inverters. In Proceedings of the 42nd Conference of the IEEE Industrial Electronics Society (IECON), Florence, Italy, 24–27 October 2016. [Google Scholar]
- Vujacic, M.; Hammami, M.; Srndovic, M.; Grandi, G. Theoretical and experimental investigation of switching ripple in the DC-link voltage of single-phase H-bridge PWM inverters. Energies.
**2017**, 10, 1189. [Google Scholar] [CrossRef] - Dahono, P.A.; Sato, Y.; Kataoka, T. Analysis and Minimization of ripple components of input current and voltage of PWM inverters. IEEE Trans. Ind. Appl.
**1996**, 32, 945–950. [Google Scholar] [CrossRef] - Gohil, G.; Bede, L.; Teodorescu, R.; Kerekes, T.; Blaabjerg, F. Analytical method to calculate the DC link current stress in voltage source converters. In Proceedings of the IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Mumbai, India, 16–19 December 2014. [Google Scholar]
- Kolar, J.W.; Round, S.D. Analytical calculation of the RMS current stress on the DC-link capacitor of voltage-PMW converter systems. IEE Proc. Electr. Power Appl.
**2006**, 153, 535–543. [Google Scholar] [CrossRef] - Renken, F. Analytic calculation of the DC-link capacitor current for pulsed three-phase inverters. In Proceedings of the 11th International Conference on Power Electronics and Motion Control, Riga, Latvia, 2–4 September 2004. [Google Scholar]
- Ayhan, U.; Hava, A.M. Analysis and characterization of DC bus ripple current of two-level inverters using the equivalent centered harmonic approach. In Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE), Phoenix, AZ, USA, 12–22 September 2011. [Google Scholar]
- Bierhoff, M.H.; Fuchs, F.W. DC-link harmonics of three-phase voltage source converters influenced by the pulsewidth-modulation strategy—An analysis. IEEE Trans. Ind. Electron.
**2008**, 55, 2085–2092. [Google Scholar] [CrossRef] - Pei, X.; Zhou, W.; Kang, Y. Analysis and calculation of DC-link current and voltage ripples for three-phase inverter with unbalanced load. IEEE Trans. Ind. Electron.
**2015**, 30, 5401–5412. [Google Scholar] - McGrath, B.P.; Holmes, D.G. A general analytical method for calculating inverter DC-link current harmonics. IEEE Trans. Ind. Appl.
**2009**, 45, 1851–1859. [Google Scholar] [CrossRef] - Nishizawa, K.; Nagaoka, J.I.; Odaka, A.; Toba, A.; Umida, H. Reduction of input current harmonics based on space vector modulation for three-phase VSI with varied power factor. In Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, USA, 18–22 September 2016. [Google Scholar]
- Hobraiche, J.; Vilain, J.P.; Macret, P.; Patin, N. A New PWM Strategy to Reduce the Inverter Input Current Ripples. IEEE Trans. Power Electron.
**2009**, 24, 172–180. [Google Scholar] [CrossRef] - Nguyen, T.D.; Patin, N.; Friedrich, G. Extended Double Carrier PWM Strategy Dedicated to RMS Current Reduction in DC Link Capacitors of Three-Phase Inverters. IEEE Trans. Power Electron.
**2014**, 29, 396–406. [Google Scholar] [CrossRef] - Vujacic, M.; Hammami, M.; Srndovic, M.; Grandi, G. Evaluation of DC voltage ripple in three-phase PWM voltage source inverters. In Proceedings of the 26th IEEE International Symposium on Industrial Electronics (ISIE), Edinburgh, UK, 19–21 June 2017. [Google Scholar]
- Levi, E.; Dujic, D.; Jones, M.; Grandi, G. Analytical Determination of DC-bus Utilization Limits in Multi-Phase VSI Supplied AC Drives. IEEE Trans. Ener. Convers.
**2008**, 2, 433–443. [Google Scholar] [CrossRef]

**Figure 2.**Space vector diagram of inverter output voltage emphasizing the input dc current (framed) for each inverter state (S

_{1}S

_{2}S

_{3}).

**Figure 3.**dc-link current and voltage ripple in one switching period: (

**a**) Case A (0 ≤ $\vartheta $ ≤ π/3, i

_{1}≥ I

_{dc}), (

**b**) Case B (0 ≤ $\vartheta $≤ π/3, i

_{1}< I

_{dc}).

**Figure 4.**Normalized peak-to-peak dc-link voltage ripple amplitude r

_{pp}($\vartheta $) over the period [0, 60°] for different modulation indices, m = 1/4, 1/3, 1/2 and 1/$\sqrt{3}$, and output phase angles (

**a**) $\phi $ = 0° and (

**b**) 50°.

**Figure 5.**Maximum of normalized peak-to-peak voltage ripple amplitude vs. modulation index for different output phase angles.

**Figure 8.**dc-link voltage switching ripple: simulation results (blue trace) and calculated peak-to- peak envelope (red trace) over a fundamental period for $\phi $ = 0 (left) and $\phi $ = 50° (right), with different modulation indicies: (

**a**,

**b**) m = 0.25; (

**c**,

**d**) m = 0.33; (

**e**,

**f**) m = 0.50; (

**g**,

**h**) m = 0.577.

**Figure 9.**Experimental results for $\phi $ = 0° (left) and $\phi $ = 50° (right). Upper half: output voltage and current. Lower half: calculated peak-to-peak envelope and measured dc-link voltage switching ripple with different modulation indices: (

**a**,

**b**) m = 0.25; (

**c**,

**d**) m = 0.33; (

**e**,

**f**) m = 0.50; (

**g**,

**h**) m = 0.577.

Label | Description | Parameters |
---|---|---|

V_{dc} | dc voltage supply | 90 V |

R | dc source resistance | 5 Ω |

L | dc source inductance | 10.15 mH |

C | dc-link capacitance | 100 μF |

f | Fundamental frequency | 50 Hz |

f_{sw} | Switching frequency | 2.5 kHz |

Load | φ = 0 | φ = 50° |
---|---|---|

R_{L} | 3.16 Ω | 26.8 Ω |

L_{L} | 20.1 mH | 103 mH |

R_{o} | 20 Ω | 0 |

C_{o} | 58 μF | 0 |

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Vujacic, M.; Hammami, M.; Srndovic, M.; Grandi, G.
Analysis of dc-Link Voltage Switching Ripple in Three-Phase PWM Inverters. *Energies* **2018**, *11*, 471.
https://doi.org/10.3390/en11020471

**AMA Style**

Vujacic M, Hammami M, Srndovic M, Grandi G.
Analysis of dc-Link Voltage Switching Ripple in Three-Phase PWM Inverters. *Energies*. 2018; 11(2):471.
https://doi.org/10.3390/en11020471

**Chicago/Turabian Style**

Vujacic, Marija, Manel Hammami, Milan Srndovic, and Gabriele Grandi.
2018. "Analysis of dc-Link Voltage Switching Ripple in Three-Phase PWM Inverters" *Energies* 11, no. 2: 471.
https://doi.org/10.3390/en11020471