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Enhancing Sensor Network Security with Improved Internal Hardware Design

1,2, 1 and 1,2,3,*
1
School of Computer & Communication Engineering, Changsha University of Science & Technology, Changsha 410114, China
2
Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation, Changsha University of Science & Technology, Changsha 410114, China
3
School of Information Science and Engineering, Fujian University of Technology, Fuzhou 350118, China
*
Author to whom correspondence should be addressed.
Sensors 2019, 19(8), 1752; https://doi.org/10.3390/s19081752
Received: 5 March 2019 / Revised: 8 April 2019 / Accepted: 10 April 2019 / Published: 12 April 2019
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PDF [1221 KB, uploaded 12 April 2019]
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Abstract

With the rapid development of the Internet-of-Things (IoT), sensors are being widely applied in industry and human life. Sensor networks based on IoT have strong Information transmission and processing capabilities. The security of sensor networks is progressively crucial. Cryptographic algorithms are widely used in sensor networks to guarantee security. Hardware implementations are preferred, since software implementations offer lower throughout and require more computational resources. Cryptographic chips should be tested in a manufacturing process and in the field to ensure their quality. As a widely used design-for-testability (DFT) technique, scan design can enhance the testability of the chips by improving the controllability and observability of the internal flip-flops. However, it may become a backdoor to leaking sensitive information related to the cipher key, and thus, threaten the security of a cryptographic chip. In this paper, a secure scan test architecture was proposed to resist scan-based noninvasive attacks on cryptographic chips with boundary scan design. Firstly, the proposed DFT architecture provides the scan chain reset mechanism by gating a mode-switching detection signal into reset input of scan cells. The contents of scan chains will be erased when the working mode is switched between test mode and functional mode, and thus, it can deter mode-switching based noninvasive attacks. Secondly, loading the secret key into scan chains of cryptographic chips is prohibited in the test mode. As a result, the test-mode-only scan attack can also be thwarted. On the other hand, shift operation under functional mode is disabled to overcome scan attack in the functional mode. The proposed secure scheme ensures the security of cryptographic chips for sensor networks with extremely low area penalty. View Full-Text
Keywords: sensors; Internet-of-Things; sensor networks; information security; cryptographic chips sensors; Internet-of-Things; sensor networks; information security; cryptographic chips
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Wang, W.; Deng, Z.; Wang, J. Enhancing Sensor Network Security with Improved Internal Hardware Design. Sensors 2019, 19, 1752.

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