Search Results (699)

To prevent the collapse of strip waveguides caused by complete undercut during hydrofluoric acid (HF) release in SOI-based cavity optomechanical accelerometers, we propose using rib waveguides as the on-chip optical transmission medium. Based on a 250-nm-thick SOI wafer, we systematically analyze the photonic crystal (PhC) microcavity, rib waveguide transmission, edge coupling, mode conversion to the PhC waveguide, and evanescent coupling. The PhC microcavity has a quality factor of 2.26 × 10⁵ at 1549.15 nm. The optimized rib waveguide (rib width 500 nm, rib height 220 nm) shows a transmission loss of 0.16 dB over 5000 μm. The rib-to-PhC waveguide coupling efficiency is 94.3% (0.25 dB loss), and a 90-μm-long tapered edge coupler achieves 65% efficiency (1.9 dB loss). The total optical path loss (including two edge couplers, rib waveguide transmission, and rib-to-PhC taper) is 4.21 dB. While maintaining optical performance comparable to strip waveguides, the rib waveguide design significantly improves post-release structural integrity at the design level. This work provides a viable optical circuit design foundation for reliable monolithically integrated cavity optomechanical accelerometers, with device fabrication and full system-level characterization planned as future work. Full article

An integrated spray-coated bi-layer lift-off process using the same positive photoresist is investigated for thick Ti patterning on structured MEMS wafers. Compared with conventional spin coating, spray coating provides more conformal photoresist coverage on wafers with 30–50 µm surface topography and reduces the local top–bottom thickness variation from approximately 30% to below 5%. By combining spray coating, heated-chuck drying, and flood exposure of the first resist layer, the integrated process improves thickness retention of the bi-layer resist and enables controlled lateral dissolution during development. After optimizing the development time, a lateral undercut of approximately 3.5 µm was obtained, which is consistent with the expected “T-shaped” resist profile. Representative 600 nm thick Ti patterns were fabricated on structured silicon wafers using this process. The results indicate that the proposed process is a feasible route for local thick-metal patterning on structured MEMS substrates under the present experimental conditions. Full article

Single-crystal diamond is regarded as one of the most promising semiconductor materials for next-generation high-power electronic devices, quantum technologies, and extreme environmental applications, owing to its ultra-wide bandgap, exceptionally high carrier mobility, ultra-high breakdown electric field, and excellent thermal conductivity. However, the lateral dimensions of both natural and synthetic single-crystal diamond are limited, which severely restricts their large-scale industrial application. Mosaic growth, in which multiple small single-crystal seeds are laterally arranged and fused at the interfaces through homoepitaxial growth, offers a promising approach to overcoming the size limitation of seed crystals and producing inch-scale single-crystal wafers. This review systematically covers the entire mosaic growth process, including seed crystal preparation, geometric design, growth parameter optimization, and innovative processing methods. Particular emphasis is placed on the mechanisms of interfacial stress generation, along with characterization techniques and stress control strategies. Finally, future perspectives on the fabrication of large-size, low-stress single-crystal diamond wafers are outlined. Full article

Accurate identification and enumeration of microscopic particles are important for microfluidic analysis, electrokinetic studies, and microscopy-based characterization of microfabricated systems. This study presents an optimized Hough Circle Transform (HCT) workflow for automated particle detection, sizing, and counting. Gold interdigitated electrode arrays (IDEAs) were fabricated on wafer substrates to generate electroosmotic flow, and 3 μm and 5 μm polystyrene microbeads were used as model particles. The final workflow incorporates parallelized multicore parameter optimization and composite statistical metrics based on detection accuracy and frame-to-frame standard deviation, enabling a small manually counted calibration set to be converted into locked detection parameters. In the final validation workflow, 10 manually counted calibration frames were used to optimize HCT parameters for each of four scenarios, and the locked parameters were then validated on 50 new frames per scenario (200 validation frames total) with two independent annotators. Mean validation success rates were 85.1% for 3 μm beads, 90.0% for 5 μm beads, 86.1% for 3 μm beads in mixed suspensions, and 87.2% for 5 μm beads in mixed suspensions, corresponding to object-level error rates of 17.9%, 10.9%, 19.9%, and 13.7%, respectively. Compared with the historical Generation I serial workflow, the optimized workflow reduced parameter-selection time from 24–48 h to 1–2 h, and the runtime image-processing time was approximately 45 ms per frame during offline analysis. These results show that parameter optimization is essential for robust HCT-based particle enumeration and that the workflow provides a practical analytical tool for microfluidic device characterization and electrokinetic experiments. Full article

Quartz is widely employed in optoelectronic and sensing applications owing to its excellent mechanical and chemical properties. However, its intrinsic transparency up to 5 μm limits its direct use as a photodetection substrate across the near- and mid-infrared spectral regions. Laser surface texturing for the fabrication of the so-called black quartz represents a promising strategy to overcome this limitation. In this work, different femtosecond (fs) laser texturing strategies were investigated on a 1 mm thick α-quartz wafer, namely uniform milling, grid-patterned grooves, and localized arrays of ablated craters. The fs-laser-treated quartz samples showed a transmittance reduction of up to 60% within the quartz transparency window in the infrared range, with crater matrices providing the most effective blackening performance. The enhanced absorption was attributed to light-trapping effects induced by the tapered crater geometry, which promotes multiple internal reflections and increased optical confinement within the substrate. The proposed strategy demonstrates a reliable, maskless, and chemical-free surface functionalization strategy for the fabrication of quartz-based substrates for broadband infrared photodetection in sensing applications. Full article

Scanning acoustic microscopy is a useful non-destructive imaging technique for semiconductor inspection, providing acoustic contrast without physical sectioning. However, the selection of an ultrasound transducer for high-quality imaging is not determined by the operating center frequency alone. The focusing condition, represented by the F-number, also plays a critical role in determining the lateral resolution. In this study, the combined effects of the center frequency and F-number on lateral resolution were investigated using wafer-based test samples. Focused ultrasound transducers with different center frequencies were used to image a striped resolution target for quantitative lateral resolution analysis. In addition, a custom-fabricated silicon wafer containing void-mimicking patterns was also imaged for qualitative evaluation. The results show that a higher frequency does not necessarily guarantee better lateral resolution. In fact, a lower-frequency transducer with tighter focusing showed greater image quality compared to a higher-frequency transducer with a larger F-number. These findings indicate that both frequency and F-number should be jointly considered when selecting ultrasound transducers for semiconductor inspection. This wafer-based evaluation provides practical guidance for optimizing imaging conditions in scanning acoustic microscopy, according to target feature size and inspection requirements. Full article

This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain K_VCO of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset. Full article

A two-step growth process was developed to fabricate a 3-inch homogeneously {100}-textured free-standing diamond wafer by microwave plasma enhanced chemical vapor deposition (MPCVD). The sequential growth process is based on a change in the growth parameter α, which is given by the growth rates on {100} and {111} facets, α = $\sqrt{3}$·(V₁₀₀/V₁₁₁). Initial growth was executed with nitrogen addition, yielding an α value close to 3 for evolutionary selection of the (100) face, followed by cessation of nitrogen addition to yield a lower α value. A homogeneously grown {100}-textured diamond over an area of ca. 175 cm² with a thickness ≥ 0.8 mm was obtained after 196 h growth. The diamond growth rate was 4.0–5.5 µm/h, which is four times higher than the conventional growth of oriented diamond. This was substantiated by optical microscopy, Raman spectroscopy, and XRD analysis. The large crystal size of 210 ± 60 µm has been assigned to the second growth step, where growth is preferentially in the <111> direction. The homogeneous {100} texture and the large crystal size are conducive to achieving high thermal conductivity, as the in-plane thermal conductivity of the polycrystalline diamond wafer was increased from ca. 850 W/(mK) to 1125 W/(mK). Full article

The emergence of three-dimensional heterogeneous integration (3D HI) has pushed forward the development of chip-to-wafer (C2W) hybrid bonding technology. To mitigate stress concentration during thermal annealing and wafer thinning processes of C2W bonding, a direct ink writing (DIW)-based 3D printing approach was proposed to fill the channel between two adjacent chips on the bonded wafer (i.e., wafer channels). A composite slurry consisting of polyimide (PI) as base material and aluminum nitride (AlN) nanoparticles as fillers was prepared. Through surface chemical modification and ultrasonic treatment, the slurry featured uniform filler dispersion (with particle size less than 1 μm) and adequate viscosity (3327 mPa·s), which fits the 3D printing process. The cured film demonstrated superior thermal stability and mechanical properties compared with pure PI, with a coefficient of thermal expansion (CTE) of 4.97 ppm/K, which matched that of silicon-based materials and exhibited excellent bonding. This approach provides a cost-effective and efficient alternative to chemical vapor deposition (CVD) techniques for filling wafer channels. Full article

This paper presents a 140 GHz two-channel transmitter in 40 nm bulk CMOS technology for D-band wireless communication systems. The transmitter employs a direct upconversion architecture with IQ Gilbert cell mixers and a shared ×9 frequency multiplier for local oscillator (LO) generation. The Lange coupler generates quadrature LO signals for I and Q paths, while the two-way four-stage differential power amplifier with cascade topology provides high output power. On-wafer measurement at 140 GHz LO frequency demonstrates a 9.9 dB conversion gain with a 5.5–6.1 GHz 3 dB bandwidth. The measured saturated output power is 10.1 dBm with an output 1 dB compression point of 6.5 dBm. The IQ imbalance remains within 2 dB across the 3 dB bandwidth. The fabricated transmitter occupies a chip area of 1.68 mm² and consumes 435 mW from a 1 V supply. The power density of 6.09 mW/mm² is the highest among reported CMOS-based D-band transmitters. The dual-channel architecture with shared LO generation enables MIMO transmission, spatial multiplexing, and diversity techniques while maintaining compact size and competitive power efficiency for high data rate wireless applications in the D-band frequency range. Full article

We present a monolithically integrated wavelength meter fabricated on an indium phosphide (InP) platform, suitable for seamless integration with active photonic components such as lasers and optical amplifiers. The device architecture incorporates multiple ring resonators and was realized through a commercial multi-project wafer (MPW) process. Experimental characterization over a 1 nm spectral window using a tunable laser demonstrates the feasibility of the approach and validates the operating principle. Full article

Silicon micromachining serves as the foundational enabling technology for high-precision MEMS inertial sensors. However, the relentless pursuit of enhanced sensitivity and multi-functionality in emerging applications encounters a fundamental bottleneck when confined to two-dimensional scaling. The evolution toward complex three-dimensional (3D) stacking architectures is an inevitable trajectory for devices including MEMS inertial sensors, yet performance is constrained by the limitations of conventional processes in fabricating and integrating intricate 3D hollow structures. Specifically, uniformity in large-area deep silicon etching, structural integrity of convex corners in wet etching, and residual stress induced by multi-layer wafer bonding have emerged as critical, shared challenges. To address these issues, this paper proposes a triple-layer wafer-level stacking scheme that synergistically combines wet/dry hybrid etching with low-temperature adhesive bonding. This stacking scheme incorporates an innovative linear compensation model for wet-etched convex corners, enabling high-precision fabrication of complex corner structures under deep etching conditions. Furthermore, a collaborative strategy involving temporary bonding and plasma flow-field optimization improves the uniformity and integrity of dry etching for large perforated structures. A low-temperature triple-layer wafer-level stacking process is developed, encompassing precise adhesive dispensing, optical alignment, and a stepped low-temperature curing profile, thereby achieving highly symmetric 3D integration with controlled adhesive distribution. The efficacy of this stacking scheme is validated through the fabrication of a symmetrically stacked triple-layer MOEMS accelerometer sensing element. Test results demonstrate a noise floor as low as 0.40 µg/√Hz and a bias instability of 1.81 µg over 10 min. Compared with a double-layer counterpart, improved performance is obtained. The wafer-level stacking scheme established in this work not only provides a viable pathway for pushing the manufacturing limits of high-precision inertial devices but also offers a generic methodology for tackling complex hollow structure formation and low-temperature integration, holding referential value for broader applications in high-precision 3D microsystems. Full article

Ultra-precision machining of ferrous alloys remains challenging because conventional diamond tools suffer severe thermochemical wear, whereas ultrasonic vibration-assisted cutting requires complex and costly equipment. This study investigates single-crystal sapphire as an alternative cutting-tool material for ultra-precision machining of both non-ferrous and ferrous metals. A sapphire tool was fabricated from a polished wafer, laser-shaped into an equilateral triangular insert, vacuum-brazed onto a tungsten carbide carrier, and finished by ultra-fine grinding to yield a well-defined cutting edge. Ultra-precision turning experiments were conducted on copper and 420 stainless steel using a Moore Nanotech 350FG lathe, and the performance of the sapphire tool was benchmarked against conventional diamond (copper) and cubic boron nitride (CBN) tools (stainless steel) under comparable cutting conditions. Surface roughness (Ra) and topography were characterized using an optical surface profiler, while scanning electron microscopy and atomic force microscopy were employed to assess tool wear and cutting-edge geometry. The sapphire tool produced mirror-like surfaces with average surface roughness (Ra) values of 6.4 nm on copper and 39.1 nm on 420 stainless steel, compared with 1.3 nm for diamond on copper and 92.9 nm for CBN on stainless steel. Across both materials, sapphire generated regular, stable tool marks and exhibited minimal wear, with no catastrophic edge degradation or clear evidence of severe chemical interaction with the steel workpiece. These results demonstrate that sapphire is a viable tool material for extending diamond turning-level surface quality to stainless steel without ultrasonic assistance. Full article

Few-layer hexagonal boron nitride (hBN) is a promising two-dimensional dielectric for electronic and neuromorphic devices. However, its practical deployment is often hindered by the thickness nonuniformity of as-grown samples and by defects introduced during the transfer-stacking process of assembled samples. In particular, the influence of the initial hBN quality on the final stacked-film quality remains insufficiently understood. Here, we report a wafer-scale strategy for fabricating high-quality few-layer hBN based on ultraflat single-crystal hBN (USC-hBN) monolayers. Compared with transfer-stacked hBN grown on Cu foil (rough hBN), stacked few-layer USC-hBN shows a much lower surface roughness and a drastically reduced wrinkle density, indicating superior flatness and interfacial cleanliness. Furthermore, memristors fabricated from six-layer USC-hBN exhibit clearer resistive-switching behavior and a higher ON/OFF ratio than those based on rough hBN, owing to the more uniform surface/interface. These results demonstrate that source-material flatness is a critical determinant of transfer-stacked hBN quality and device performance. This work provides an effective route toward reliable integration of high-quality two-dimensional dielectric films. Full article

Reconfigurable radio frequency (RF) attenuators are critical passive components for 5G-Advanced and emerging 6G wireless systems. Conventional tunable attenuators rely on solid-state switches combined with fixed resistor networks, which suffer from unavoidable static power consumption and severe parasitic degradation at high frequencies. Here, we systematically demonstrate HfO₂-based non-volatile memristors as RF switches with tunable ON-state resistance (R_ON), enabling a switching-attenuation-integrated multistate attenuator. The fabricated Au/HfO₂/Ag devices exhibit stable bipolar resistive switching with an ON/OFF ratio exceeding 10⁹, reliable retention of 10⁵ s, and programmable R_ON continuously tuned from 5.8 Ω to 197.5 Ω. On-wafer RF characterizations from 10 MHz to 43.5 GHz reveal low insertion loss (−0.53 dB), high isolation (−26.8 dB), and clear scaling laws governing the effects of device geometry and R_ON on RF performance. Leveraging these unique characteristics, we propose a symmetric π-type programmable all-memristor attenuator architecture with a cascaded 2-unit configuration. The design achieves 12 discrete attenuation levels from 2 dB to 24 dB, a return loss better than 10 dB across the full band, and zero static power consumption without additional passive components or bias networks. This work establishes the fundamental material-device-RF performance relationship in HfO₂-based RF switches and provides a compact, low-power, and highly integrable solution for next-generation reconfigurable RF front-ends. Full article