A 140 GHz Two-Channel Transmitter in 40 nm Bulk CMOS

Abstract

This paper presents a 140 GHz two-channel transmitter in 40 nm bulk CMOS technology for D-band wireless communication systems. The transmitter employs a direct upconversion architecture with IQ Gilbert cell mixers and a shared ×9 frequency multiplier for local oscillator (LO) generation. The Lange coupler generates quadrature LO signals for I and Q paths, while the two-way four-stage differential power amplifier with cascade topology provides high output power. On-wafer measurement at 140 GHz LO frequency demonstrates a 9.9 dB conversion gain with a 5.5–6.1 GHz 3 dB bandwidth. The measured saturated output power is 10.1 dBm with an output 1 dB compression point of 6.5 dBm. The IQ imbalance remains within 2 dB across the 3 dB bandwidth. The fabricated transmitter occupies a chip area of 1.68 mm² and consumes 435 mW from a 1 V supply. The power density of 6.09 mW/mm² is the highest among reported CMOS-based D-band transmitters. The dual-channel architecture with shared LO generation enables MIMO transmission, spatial multiplexing, and diversity techniques while maintaining compact size and competitive power efficiency for high data rate wireless applications in the D-band frequency range.

1. Introduction

The exponential growth in wireless data traffic and the emergence of bandwidth-intensive applications, such as ultra-high-definition video streaming, extended reality, and wireless backhaul, are driving the exploration of new frequency bands for next-generation wireless networks. The sub-terahertz and terahertz bands, particularly the D-band (110–170 GHz), have emerged as promising candidates for sixth-generation (6G) wireless communications due to the availability of a large unused spectrum and the potential for multi-gigabit data rates [1,2].

Despite the attractive bandwidth availability, D-band wireless systems face significant implementation challenges. The high free-space path loss at these frequencies necessitates transmitters with high output power and efficient power amplifiers to maintain an adequate link budget [3]. Additionally, the design of wideband transmitters with sufficient conversion gain becomes increasingly difficult as operating frequencies approach the transit frequency (f_T) and maximum oscillation frequency (f_max) of CMOS transistors [4]. Advanced silicon technologies, particularly bulk CMOS and silicon-on-insulator (SOI) processes, have demonstrated the feasibility of D-band transceiver implementation, offering advantages in terms of integration density and cost compared to III-V semiconductor technologies [5].

Recent research efforts have focused on developing D-band transmitters in CMOS technology with various architectures. Direct upconversion transmitters employing Gilbert cell mixers and frequency multipliers have been widely adopted for their compact size and ability to support quadrature modulation [6,7,8]. However, most reported D-band CMOS transmitters implement single-channel architectures, which limit the potential for multiple-input multiple-output (MIMO) systems, spatial multiplexing, and diversity transmission techniques essential for enhancing system capacity and reliability in high-frequency wireless communications.

Several multi-channel and MIMO D-band transceiver designs have been reported in the recent literature. Simsek et al. [5] demonstrated a 140 GHz four-channel MIMO transceiver in 45 nm SOI CMOS, achieving a conversion gain of 18 dB with a Psat of 5 dBm per channel. While the four-channel architecture offers greater spatial multiplexing capability, the per-channel output power remains relatively modest, and the use of the SOI process limits cost-effectiveness compared to the bulk CMOS implementations. Farid et al. [7] presented a broadband direct-conversion transmitter and receiver in 22 nm FDSOI CMOS at D-band, achieving a conversion gain of 18 dB with a 3 dB bandwidth of 8 GHz, though the reported Psat of 2.8 dBm is significantly lower than the proposed work. Fu et al. [8] reported a D-band 32-QAM transceiver in 40 nm CMOS with a Psat of 1.3 dBm and a 3 dB bandwidth of 3 GHz. In contrast, the proposed two-channel transmitter achieves a Psat of 10.1 dBm with a power density of 6.09 mW/mm², the highest among reported CMOS-based D-band transmitters, while supporting dual-channel operation for MIMO applications in a compact bulk CMOS implementation.

The proposed shared LO architecture offers a distinct structural advantage for MIMO scaling at D-band frequencies. At D-band frequencies, the free-space wavelength is approximately 2.1 mm, which imposes a strict constraint on the antenna element spacing (typically λ/2 ≈ 1.05 mm) in a MIMO array. To integrate multiple transmitter channels within this spacing, each channel must occupy a sufficiently small chip area, making power density a critical design objective. In a per-channel LO scheme, each channel requires its own frequency multiplier chain, which includes intermediate stages operating at progressively higher frequencies. The passive components in these lower-frequency stages, such as inductors and matching network transformers, require larger physical dimensions compared to those operating at the D-band, making the multiplier chain one of the most area-intensive blocks in the transmitter. By sharing a single LO generation block across both channels, the proposed architecture eliminates the duplication of these area-intensive components, enabling a more compact dual-channel implementation. This structural advantage is directly reflected in the achieved power density of 6.09 mW/mm², the highest among reported CMOS-based D-band transmitters, demonstrating that the shared LO architecture is a deliberate architectural choice that enables efficient MIMO scaling at the D-band.

This paper presents a 140 GHz two-channel transmitter in 40 nm bulk CMOS technology featuring IQ modulation capability for D-band wireless communication systems. The transmitter employs a direct upconversion architecture with shared local oscillator (LO) generation to minimize chip area and power consumption. The main contributions of this work are: (1) a compact two-channel architecture achieving high output power density through shared LO generation and optimized power amplifier design, (2) wideband operation with a 5.5–6.1 GHz 3 dB bandwidth supporting high data rate modulation, and (3) comprehensive characterization demonstrating a saturated output power of 10.1 dBm with a conversion gain of 9.9 dB at the D-band.

2. Two-Channel Transmitter Architecture

The proposed two-channel transmitter architecture is illustrated in Figure 1. Each channel consists of an IQ modulator and a power amplifier (PA). The baseband IQ signals (BB_I and BB_Q) are upconverted to the D-band frequency using IQ Gilbert cell mixers. The LO signal is generated by a ×9 frequency multiplier and distributed to both channels. The upconverted signals are then amplified by the PA to deliver the output power.

2.1. LO Generation

The LO generation circuit is shown in Figure 2. The input reference signal is converted to differential signals by a passive balun. The differential signals are then fed to a two-stage inverter (Figure 2a), which converts the sinusoidal signal to a square-wave signal. The square wave is rich in odd-order harmonics, enhancing the third-harmonic extraction efficiency in the tripler stages.

As shown in Figure 2b, the ×9 frequency multiplier consists of two ×3 triplers cascaded with a buffer amplifier in between. The square-wave signal from the inverter drives the first tripler, which upconverts the frequency by a factor of three. The buffer amplifier compensates for the conversion loss and provides sufficient signal swing for the second tripler stage. The second tripler further multiplies the frequency by three, generating the D-band LO signal.

2.2. LO Distribution and Quadrature Generation

The Lange coupler and LO driver schematic is shown in Figure 3. Quadrature LO signals with 90-degree phase difference are generated for the I and Q paths, producing four differential outputs: LO_I+/− and LO_Q+/−P. Each output is followed by a three-stage buffer amplifier to provide sufficient LO drive for the mixers while maintaining amplitude and phase balance between the I and Q channels [9].

The Lange coupler is employed for quadrature LO signal generation, offering a wider bandwidth and more compact footprint compared to branch-line and rat-race couplers [10]. Figure 4a shows the metal stack-up of the 40 nm CMOS process and the 3D layout of the fabricated Lange coupler. In this process, M10 (UTM, ultra-thick metal) exhibits lower resistive loss than the AP layer; however, its larger parasitic capacitance results in a significantly lower characteristic impedance. As shown in Figure 4b, the characteristic impedance using M10 is approximately 20 Ω, whereas it is approximately 35 Ω using AP across the D-band. As a result, AP was selected as the signal routing layer, with M1–M2 used as the ground plane to provide a well-defined reference and minimize substrate coupling. As shown in Figure 4c, the simulated insertion loss is within 0.7 dB of the ideal 3 dB split, and the phase difference between the through and coupled ports remains within 2.7° of the ideal 90° quadrature across 80–180 GHz, confirming a wideband amplitude and phase balance suitable for IQ modulation.

2.3. IQ Modulator

The upconversion mixer, based on the Gilbert cell topology, is shown in Figure 5. A double-balanced architecture is employed for port-to-port isolation and LO leakage suppression. The differential baseband I signal (BB_I) is upconverted by the in-phase LO signal (LO_I), while the Q signal (BB_Q) is upconverted by the quadrature LO signal (LO_Q). The outputs of the I and Q mixers are combined through current summing at the PA input, generating the modulated D-band signal.

2.4. Power Amplifier

The schematic and transformer layouts of the four-stage differential power amplifier are presented in Figure 6. The PA employs a common-source topology with progressive transistor sizing M1 (1 μm × 16), M2 (1 μm × 32), and M3 (1 μm × 64) across the four stages. The first two stages use M1 to provide sufficient small-signal gain, and the transistor width is doubled at each subsequent stage to provide sufficient drive capability for the next stage while handling the progressively increasing signal swing, keeping the interstage matching tractable across the D-band. Transformer-based interstage matching networks (TF1–TF3) are used to optimize power transfer between stages, and the output transformer performs differential-to-single-ended conversion simultaneously with output matching. Each channel employs two-way power combining at the output stage to increase the output power delivered.

The layout of the 1 μm × 16 unit transistor is shown in Figure 7. Cross-coupled neutralization capacitors (Cneu) are placed between the drain and gate of each differential transistor pair to cancel the gate–drain capacitance (Cgd), thereby enhancing gain and ensuring unconditional stability at the D-band frequencies.

The simulated maximum available gain (Gmax) and stability factor (μ) of the driver stage transistors as a function of Cneu at 140 GHz are shown in Figure 8, for gate widths of 16 μm and 32 μm. Without neutralization, both transistors exhibit μ < 1, indicating potential instability. As Cneu increases, stability improves while Gmax initially rises and then degrades. The neutralization capacitance for each driver stage was selected at the point where unconditional stability (μ > 1) is satisfied while Gmax is maximized, yielding Cneu = 4.9 fF for the 16 μm stage and Cneu = 9.8 fF for the 32 μm stage.

The simulated Gmax, output power (Pout), power-added efficiency (PAE), and stability factor (μ) of the output power stage as a function of Cneu at 140 GHz are shown in Figure 9. The neutralization capacitance was selected at Cneu = 19.2 fF, where unconditional stability is achieved, and the PAE is maximized, with the resulting Pout only 0.3 dB below the peak value.

The output matching network design is presented in Figure 10. The output transformer serves dual purposes: impedance matching from the optimal load impedance to 50 Ω and differential-to-single-ended (balun) conversion, along with two-way power combining. The simulated load trajectory on the Smith chart is shown in Figure 10a. Starting from the 100 Ω differential port impedance with the pad parasitics included (96.2 − j105 Ω), the impedance is transformed through the combiner (27.1 − j64.4 Ω) and the balun (2.82 + j9.07 Ω), converging close to the optimal load impedance Zopt = 2.69 + j7.89 Ω. The simulated optimal output power at Zopt is 9.8 dBm. The layout of the output balun and power combiner is shown in Figure 10b, illustrating the three impedance transformation nodes corresponding to the Smith chart trajectory. The simulated passive loss of the output matching network across the D-band is shown in Figure 10c, which remains below 1.5 dB across the entire band, confirming a low-loss power delivery to the output port.

3. Measurement Results

The two-channel transmitter was fabricated in 40 nm bulk CMOS technology. The measurement module and chip photograph are shown in the photograph in Figure 11. Figure 11a shows the fabricated PCB module with the mounted chip and SMA connectors. The baseband IQ signals and the LO reference signal are provided through the SMA connectors on the module, while the RF outputs are accessed through on-wafer probing. The microphotograph of the fabricated two-channel transmitter is shown in Figure 11b. The chip size is 1.68 mm², including the probing pads.

The measurement setup for the fabricated transmitter is shown in Figure 12. The fabricated transmitter was characterized through on-wafer testing. A 200-μm pitch GSG probe from GGB Industries was used for the RF signal probing. During the measurement, both channels were biased. For single-channel characterization, one of the differential baseband inputs was terminated with 50 Ω, while the other was driven by the baseband signal. The D-band output was measured using a WR 6.5 SAX signal analyzer extender from VDI connected to an N9010A signal analyzer from Keysight Technologies. All signal generators and the spectrum analyzer were synchronized with a 10 MHz reference clock.

3.1. Conversion Gain Measurement

3.1.1. Conversion Gain vs. Baseband Frequency

The measured IQ imbalance at 140 GHz LO frequency is shown in Figure 13. To characterize the IQ balance, the conversion gain was measured separately for the in-phase and quadrature paths by applying the baseband signal to each port while terminating the other with 50 Ω.

As shown in Figure 13a, with the baseband signal applied to the in-phase port, at 140 GHz LO frequency, the peak conversion gains for the in-phase port are 9.8 dB and 9.9 dB for USB, and 9.2 dB and 9.5 dB for LSB for Channel 1 and Channel 2, respectively. For Channel 1, the measured 3 dB bandwidth is 5.8 GHz for both USB and LSB. For Channel 2, the measured 3 dB bandwidths are 5.6 GHz and 5.5 GHz for USB and LSB, respectively.

With the baseband signal applied to the quadrature port (Figure 13b), the peak conversion gains at 140 GHz LO frequency are 8.2 dB and 8.3 dB for USB, and 7.6 dB and 7.9 dB for LSB for Channel 1 and Channel 2, respectively. For Channel 1, the measured 3 dB bandwidth is 5.8 GHz for both USB and LSB. For Channel 2, the measured 3 dB bandwidths are 6.1 GHz and 5.9 GHz for USB and LSB, respectively. Both measured and simulated results are shown for comparison.

The IQ difference, calculated as the conversion gain difference between the in-phase and quadrature paths for both USB and LSB, is shown in Figure 13c. For both Channel 1 and Channel 2, the IQ imbalance is within 2 dB across the 3 dB bandwidth.

3.1.2. Conversion Gain vs. LO Frequency

The measured IQ balance as a function of LO frequency is presented in Figure 14. The baseband frequency was fixed at 1 GHz, while the LO frequency was swept from 129 GHz to 144 GHz. The conversion gain was measured separately for the in-phase and quadrature paths to characterize the IQ balance.

Figure 14a and Figure 14b show the measured conversion gain for the in-phase and quadrature ports, respectively. The peak conversion gains occur at 135–137 GHz for both channels and both ports. For the in-phase port, Channel 1 and Channel 2 achieve peak conversion gains of 10.4 dB and 10.7 dB for USB, and 9.8 dB and 10 dB for LSB, respectively. For the quadrature port, the peak conversion gains are 9.6 dB and 10.1 dB for USB, and 8.8 dB and 9.2 dB for LSB, respectively. The conversion gain remains above 7 dB from 132 GHz to 141 GHz for both channels and both ports.

As shown in Figure 14c, the IQ difference between the in-phase and quadrature paths is a function of LO frequency. The IQ imbalance is less than 1 dB from 129 GHz to 137 GHz for both channels. At higher LO frequencies beyond 140 GHz, the IQ imbalance increases to approximately 3 dB at 144 GHz.

3.2. Output Power Measurement

The output power measurement setup is presented in Figure 15. A photograph of the setup is shown in Figure 15a, and the corresponding block diagram using a PM5B power meter is shown in Figure 15b. The probe loss was determined by performing 10 repeated measurements of a 175-μm pitch on-wafer through standard, with the average insertion loss divided by two to obtain the loss of a single probe. For the PM5B power meter, a sufficient warm-up time was allowed after power-on, followed by zeroing the sensor prior to measurement to minimize the effect of thermal drift on the power reading. The reported Psat and OP1dB values are de-embedded from both the probe loss and the waveguide path loss. The measured output power versus input power at 137 GHz and 140 GHz LO frequencies is shown in Figure 15c, with the baseband frequency fixed at 1 GHz. The measured results are compared with the simulation.

At 137 GHz LO frequency, the saturated output powers are 8.6 dBm and 10.1 dBm for Channel 1 and Channel 2, respectively. The output 1 dB compression points (OP1dB) are 5.5 dBm and 6.5 dBm for Channel 1 and Channel 2, respectively. At 140 GHz LO frequency, the saturated output powers are 6.8 dBm and 8.7 dBm for Channel 1 and Channel 2, respectively, with OP1dB of 3.9 dBm and 5.2 dBm. During the measurement, the total DC power consumption is 435 mW from a 1 V supply.

To characterize the inter-channel isolation of the dual-channel transmitter, the measurement setup shown in Figure 12 was used. A baseband signal was applied to one channel, and the RF output leakage at the other channel was measured under the same operating conditions. The inter-channel isolation was calculated from the difference between the de-embedded RF output power of the driven channel and that of the leakage channel.

As shown in Figure 16a, the measured isolation remains above approximately 42 dB over the input power range from −20 dBm to 4 dBm at a fixed baseband frequency of 1 GHz. This confirms that the two channels maintain a high isolation level over the measured input power range.

Figure 16b shows the isolation as a function of baseband frequency at a fixed input power of −6 dBm, which was selected as a representative power level near the measured input 1 dB compression point. Within the 3 dB bandwidth, the measured isolation remains above 40 dB in both leakage directions. Overall, the results verify that the dual-channel transmitter maintains high inter-channel isolation in both leakage directions.

The discrepancy between the measured and simulated results is attributed to several factors. First, modeling inaccuracies of passive components such as transformers and transmission lines at the D-band frequencies introduce errors in the simulated gain and matching conditions. Second, the parasitic effects of the progressively sized PA stage transistors are difficult to model accurately, particularly for large gate-width devices operating near the transistor frequency limits. Third, the asymmetric placement of the mixer and LO bias pads, which was adopted to maximize layout area efficiency, introduces slight differences in the bias routing between the two channels that were not fully captured in the pre-layout simulation. Finally, local process variations across the chip area, including transistor threshold voltage and metal layer thickness variations, may further contribute to the observed discrepancy between simulation and measurement.

3.3. Modulation Signal Measurement

The EVM measurement setup is shown in Figure 17. Baseband IQ signals are generated by a Keysight M8195A arbitrary waveform generator (AWG) and directly applied to the DUT baseband inputs, which upconverts the signal to 140 GHz. The DUT output is downconverted to an IF of 10 GHz using a WR 6.5 SAX, and the EVM analysis is performed by a Tektronix MSO 73304DX oscilloscope. During the measurement, the DUT was operated at a peak output power below the OP1dB compression point (6.5 dBm). The measured constellation diagrams for 16QAM and 32QAM are shown in Figure 18a and Figure 18b, respectively. For a 16QAM signal at 6 GBaud (24 Gb/s), an EVMrms of 8.15% was measured at an average output power of 0.6 dBm. For a 32QAM signal at 6 GBaud (30 Gb/s), an EVMrms of 7.73% was measured at an average output power of −0.7 dBm. The measured EVMrms versus baud rate for both modulation schemes is shown in Figure 18c.

Table 1. Performance comparison with state-of-the-art CMOS D-band transmitters.

	This Work		[5]	[6]	[7]	[8]	[11]	[12]
Process	40 nm CMOS		45 nm SOI	40 nm CMOS	22 nm CMOS	40 nm CMOS	65 nm CMOS	65 nm CMOS
Frequency [GHz]	140		140	118	135	137	152	165
Number of Channels	2		4	1	1	1	1	1
Conversion Gain [dB]	9.9		18	13.5	18	16.7	N.A.	N.A.
Psat [dBm]	10.1		5	N.A.	2.8	1.3	3	0.7
OP1dB [dBm]	6.5		4.3	4.5	* 0.5	N.A.	N.A.	N.A.
3 dB Bandwidth [GHz]	5.5–6.1		12	14	8	3	N.A.	N.A.
Pdc [mW]	435		463	271	196	327	55	12
Modulation Type	IQ		IQ	IQ	IQ	IQ	OOK	OOK
Area [mm2]	1.68		2.94	1.51	1.44	1.02	0.39	0.45
** Power Density [mW/mm2]	6.09		1.08	1.87	1.32	1.32	5.11	2.61
Modulation Scheme	16QAM	32QAM	QPSK	N.A.	N.A.	32QAM	OOK	OOK
Data rate [Gbps]	24 @8.15%	30 @7.73%	0.8	N.A.	N.A.	15 @7.6%	10	9

* graphically estimated, ** power density = Psat[mW]/Area[mm²], N.A.: not applicable.

summarizes the performance of the proposed transmitter and compares it with state-of-the-art D-band transmitters in CMOS technology. Most prior works implement single-channel transmitters, while this work demonstrates a two-channel architecture with shared LO generation. The proposed transmitter achieves the highest saturated output power of 10.1 dBm among CMOS-based transmitters operating above 100 GHz, while simultaneously supporting dual-channel operation. The 3 dB bandwidth of 5.5–6.1 GHz is sufficient to support high data rate modulation, as demonstrated by the EVM measurements. The proposed transmitter also achieves the highest saturated output power among the compared works for the D-band IQ transmitters.

The power density of 6.09 mW/mm² is the highest among the compared works, demonstrating an efficient use of chip area. This high-power density is achieved through the compact two-channel architecture with shared LO generation circuitry and optimized PA design. The dual-channel implementation enables spatial multiplexing or diversity transmission without a proportional increase in chip area and power consumption compared to single-channel designs. The conversion gain of 9.9 dB and OP1dB of 6.5 dBm provide sufficient signal amplification for practical communication systems. The DC power consumption of 435 mW represents a competitive power efficiency considering the dual-channel operation and high output power.

4. Conclusions

This paper presents a 140 GHz two-channel transmitter with IQ modulation capability for D-band wireless communication systems. The transmitter employs a direct upconversion architecture with Gilbert cell mixers and a shared ×9 frequency multiplier for LO generation. The fabricated transmitter is characterized through on-wafer measurements at a 140 GHz LO frequency. The measured conversion gain is 9.9 dB with a saturated output power of 10.1 dBm and OP1dB of 6.5 dBm. The modulation capability is validated through EVM measurements, demonstrating 24 Gb/s 16-QAM and 30 Gb/s 32-QAM transmission at 140 GHz. The IQ imbalance is within 2 dB across the 3 dB bandwidth. The transmitter is fabricated in 40 nm bulk CMOS technology, achieving a chip area of 1.68 mm² and a total DC power consumption of 435 mW from a 1 V supply. The power density of 6.09 mW/mm² is the highest among the reported CMOS-based D-band transmitters. The proposed two-channel transmitter can be utilized for high data rate wireless communication systems in the D-band frequency range, enabling MIMO transmission and diversity techniques for enhanced system capacity.