Search Results (25)

The heterogeneous integration of ferroelectric thin films on silicon- or silicon nitride-based platforms for photonic integrated circuits plays a crucial role in the development of nanophotonic thin film modulators. For this purpose, an ultrathin seed film was recently introduced as an integration method for ferroelectric thin films such as BaTiO₃ and Pb(Zr,Ti)O₃. One issue with this self-orienting seed film is that for non-planarized circuits, it fails to act as a template film for the thin films. To circumvent this problem, we propose a method of planarization without the need for wafer-scale chemical mechanical polishing by using hydrogen silsesquioxane as a precursor to forming amorphous silica, in order to create an oxide cladding similar to the thermal oxide often present on silicon-based platforms. Additionally, this oxide cladding is compatible with the high annealing temperatures usually required for the deposition of these novel ferroelectric thin films (600–800 °C). The thickness of this silica film can be controlled through a dry etch process, giving rise to a versatile platform for integrating nanophotonic thin film modulators on a wider variety of substrates. Using this method, we successfully demonstrate a hybrid BaTiO₃-Si ring modulator with a high Pockels coefficient of $r_{wg}=155.57\pm 10.91$ pm V⁻¹ and a half-wave voltage-length product of $V_{\pi }L=2.638\pm 0.084$ V cm, confirming the integration of ferroelectric thin films on an initially non-planar substrate. Full article

Epitaxial layers of water-soluble Sr₃Al₂O₆ were fabricated as sacrificial layers on SrTiO₃ (100) single-crystal substrates using the Pulsed Laser Deposition technique. This approach envisages the possibility of developing a new generation of micro-Solid Oxide Fuel Cells and micro-Solid Oxide Electrochemical Cells for portable energy conversion and storage devices. The sacrificial layer technique offers a pathway to engineering free-standing membranes of electrolytes, cathodes, and anodes with total thicknesses on the order of a few nanometers. Furthermore, the ability to etch the SAO sacrificial layer and transfer ultra-thin oxide films from single-crystal substrates to silicon-based circuits opens possibilities for creating a novel class of mixed electronic and ionic devices with unexplored potential. In this work, we report the growth mechanism and structural characterization of the SAO sacrificial layer. Epitaxial samarium-doped ceria films, grown on SrTiO3 substrates using Sr₃Al₂O₆ as a buffer layer, were successfully transferred onto silicon wafers. This demonstration highlights the potential of the sacrificial layer method for integrating high-quality oxide thin films into advanced device architectures, bridging the gap between oxide materials and silicon-based technologies. Full article

Front surface texturing is a common method used to improve the optical performance of photovoltaic devices. However, traditional texturing techniques may be challenging in some cases, such as when dealing with ultra-thin substrates. Textured polymer films on such devices would be an alternative approach. This paper reports a study of NOA81 thin films with a bionic lotus leaf surface structure on monocrystalline silicon solar cells. Inspired by the surface structure of natural lotus leaves, we successfully prepared a bionic lotus leaf microstructure film on the surface of solar cells based on NOA81 using polydimethylsiloxane (PDMS) polymer and nanoimprinting methods. Scanning electron microscopy (SEM) images showed that the surface structure of the NOA81 thin film was the same as that of natural lotus leaves. A UV-Vis spectrophotometer with an integrating sphere was used to measure the reflectance of the textured NOA81 film on the silicon wafer. Results showed that the textured NOA81 film could effectively reduce the reflectance of the silicon wafer surface. We also used finite-difference time-domain (FDTD) simulation to verify this conclusion further. Finally, the I-V characteristics of the prepared solar cells with the textured NOA81 film were investigated, and the highest photovoltaic efficiency was measured to be about 16.07%, effectively improving the photoelectric conversion efficiency. In addition, the film with textured NOA81 can be used as a protective film for monocrystalline silicon solar cells. Full article

We demonstrate two distinct experimental processes involving the large-area growth of ordered and disordered silicon nanowire arrays (SiNWs) on a p-type silicon substrate using the metal-assisted chemical etching method. The two processes are based on the etching of monocrystalline silicon wafers by randomly distributed Ag films and ultra-thin Au films with ordered nano-mesh arrays, respectively, wherein the growth of SiNWs is implemented using a specific proportion of a HF-containing solution at room temperature. In this study, the microstructural change mechanisms for the two morphologically different arrays before and after annealing were investigated using Raman spectra. The effects of various mechanisms on the observed Raman scattering peak’s deviation from symmetry, redshift and broadening were analyzed. The evolution of the unstable amorphous structures of nanoscale materials during the high-temperature annealing process was observed via high-resolution scanning electron microscope (SEM) observations. The scattering peak parameters determined from the Raman spectra led to conclusions concerning the various mechanisms by which high-temperature annealing influences the microstructures of the two morphologically different SiNWs fabricated on the p-type silicon substrate. Therefore, the deviation of SiNWs from the monocrystalline silicon scattering peak at 520.05 cm⁻¹ when changing the diameter of the nanowire columns was calculated to further analyze the effect of thermal annealing on Raman characteristics. Full article

This communication shows the recipe for plasma-enhanced atomic layer deposition (PEALD) Al₂O₃ ultra-thin films with thicknesses below 40 nm. Al₂O₃ ultra-thin films were deposited by PEALD to improve the rubidium optically pumped atomic magnetometers’ (OPMs) cell lifetime. This requirement is due to the consumption of the alkali metal (rubidium) inside the vapor cells. Moreover, as a silicon wafer was used, an on-chip photodiode was already integrated into the fabrication of the OPM. The ALD parameters were achieved with a GPC close to 1.2 Å/cycle and the ALD window threshold at 250 °C. The PEALD Al₂O₃ ultra-thin films showed a refractive index of 1.55 at 795 nm (tuned to the D1 transition of rubidium for spin-polarization of the atoms). The EDS chemical elemental analysis showed an atomic percentage of 58.65% for oxygen (O) and 41.35% for aluminum (Al), with a mass percentage of 45.69% for O and 54.31% for Al. A sensitive XPS surface elemental composition confirmed the formation of the PEALD Al₂O₃ ultra-thin film with an Al 2s peak at 119.2 eV, Al 2p peak at 74.4 eV, and was oxygen rich. The SEM analysis presented a non-uniformity of around 3%. Finally, the rubidium consumption in the coated OPM was monitored. Therefore, PEALD Al₂O₃ ultra-thin films were deposited while controlling their optical refractive index, crystalline properties, void fraction, surface roughness and thickness uniformity (on OPM volume 1 mm × 1 mm × 0.180 mm cavity etched by RIE), as well as the chemical composition for improving the rubidium OPM lifetime. Full article

This paper presents a piezoresistive differential pressure sensor based on a silicon-on-insulator (SOI) structure for low pressure detection from 0 to 30 kPa. In the design phase, the stress distribution on the sensing membrane surface is simulated, and the doping concentration and geometry of the piezoresistor are evaluated. By optimizing the process, the realization of the pressure sensing diaphragm with a controllable thickness is achieved, and good ohmic contact is ensured. To obtain higher sensitivity and high temperature stability, an SOI structure with a 1.5 µm ultra-thin monocrystalline silicon layer is used in device manufacturing. The device diaphragm size is 700 µm × 700 µm × 2.1 µm. The experimental results show that the fabricated piezoresistive pressure sensor has a high sensitivity of 2.255 mV/V/kPa and a sensing resolution of less than 100 Pa at room temperature. The sensor has a temperature coefficient of sensitivity (TCS) of −0.221 %FS/°C and a temperature coefficient of offset (TCO) of −0.209 %FS/°C at operating temperatures ranging from 20 °C to 160 °C. The reported piezoresistive microelectromechanical systems (MEMS) pressure sensors are fabricated on 8-inch wafers using standard CMOS-compatible processes, which provides a volume solution for embedded integrated precision detection applications of air pressure, offering better insights for high-temperature and miniaturized low-pressure sensor research. Full article

In this study, an innovative fabrication method called rolling-slitting forming, which forms ultra-thin diamond blades, was presented for the first time. Furthermore, the feasibility of the rolling-slitting forming method when applied to silicon carbide wafer dicing blades was investigated; moreover, the cold-pressing blade samples were manufactured through the conventional process under the same sintering conditions to compare and analyze the manufacturing efficiency, organization and performance. The results show that the new method achieves high-precision and low-thickness dicing blades through continuous production without molds—with the thinnest blades being 0.048 mm thick. Furthermore, the rolling-slitting blade has a unique multiporous heat-conductive matrix structure and in-situ generated amorphous pyrolytic carbon, which can reduce the dicing resistance and contribute to a better cutting quality. In addition, the effects of the dicing parameters on SiC were investigated by using indications of spindle current, dicing chipping size and kerf width during the high dicing process. For a dicing depth of 0.2 mm, the ideal performance of dicing SiC with an ultra-thin blade was achieved at a spindle speed of 22,000 rpm and a feed rate of 5 mm/s. This research provides a new idea for the manufacturing of dicing blades, which can satisfy the demand for ultra-narrow dicing streets of high integration of ICs. Full article

For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the $0.7$ nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology. Full article

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube. Full article

Silicon avalanche photodetector (APD) plays a very important role in near-infrared light detection due to its linear controllable gain and attractive manufacturing cost. In this paper, a silicon APD with punch-through structure is designed and fabricated by standard 0.5 μm complementary metal oxide semiconductor (CMOS) technology. The proposed structure eliminates the requirements for wafer-thinning and the double-side metallization process by most commercial Si APD products. The fabricated device shows very low level dark current of several tens Picoamperes and ultra-high multiplication gain of ~4600 at near-infrared wavelength. The ultra-low extracted temperature coefficient of the breakdown voltage is 0.077 V/K. The high performance provides a promising solution for near-infrared weak light detection. Full article

The development of field-emission scanning electron microscopes for high-resolution imaging at very low acceleration voltages and equipped with highly sensitive detectors of backscattered electrons (BSE) has enabled transmission electron microscopy (TEM)-like imaging of the cut surfaces of tissue blocks, which are impermeable to the electron beam, or tissue sections mounted on the solid substrates. This has resulted in the development of methods that simplify and accelerate ultrastructural studies of large areas and volumes of biological samples. This article provides an overview of these methods, including their advantages and disadvantages. The imaging of large sample areas can be performed using two methods based on the detection of transmitted electrons or BSE. Effective imaging using BSE requires special fixation and en bloc contrasting of samples. BSE imaging has resulted in the development of volume imaging techniques, including array tomography (AT) and serial block-face imaging (SBF-SEM). In AT, serial ultrathin sections are collected manually on a solid substrate such as a glass and silicon wafer or automatically on a tape using a special ultramicrotome. The imaging of serial sections is used to obtain three-dimensional (3D) information. SBF-SEM is based on removing the top layer of a resin-embedded sample using an ultramicrotome inside the SEM specimen chamber and then imaging the exposed surface with a BSE detector. The steps of cutting and imaging the resin block are repeated hundreds or thousands of times to obtain a z-stack for 3D analyses. Full article

Nowadays, the Fabry–Perot etalon (F–P) has been widely utilized in the optical parametric oscillator (OPO) to improve the filtering performance. In this paper, we reported an F–P etalon composed of two ultra-thin silicon wafers spaced with the air. The linewidth of the signal laser and the threshold are 0.03 nm and 0.6 W, respectively when the proposed etalon is employed to a OPO system based on the MgO-doped LiNbO₃ (MgO: PPLN). A stabilized output at 1492.4 nm is obtained, and a tunable, high-precision filtering performance can be achieved by varying the gap distance of the F–P etalon arbitrarily due to its ultra-thin thickness. In addition, the F–P etalon can work on a very wide bandwidth due to its weak absorption during the infrared and terahertz waveband. The high-precision tuning capability and wide-band function of proposed etalon may benefit many applications, including spectroscopy, filtering, and optical communication. Full article

Intelligent structural colors have received extensive attention in recent years due to their diverse applications. However, the large-area, uniform, and cost-effective fabrication of ultra-thin structural color films is still challenging. Here, for the first time, we design and employ an ultrasonic spray-coating technique with non-toxic, green nano-silica and polyvinylpyrrolidone as raw materials, to prepare structural color films on silicon wafers. Due to the addition of polyvinylpyrrolidone, the coffee-ring effect during droplet drying is suppressed and uniform composite films are formed. We further perform a detailed study of the influence of various processing parameters including silica/polyvinylpyrrolidone concentration, substrate temperature, nozzle-to-substrate distance, and number of spray-passes on film roughness and thickness. By increasing the number of spray-passes from 10 to 30, the film thickness from 120 to 340 nm is modulated, resulting in different colors, and large-area and uniform colors on commercial round silicon wafers with 15 cm diameter are achieved. The silica/polyvinylpyrrolidone composite films show strong hydrophilicity and are sensitive to humidity changes, leading to quickly tunable and reversible structural colors. Quartz crystal microbalance with dissipation demonstrates water vapor adsorption and condensation on the nanofilm when increasing environmental humidity. Thereby, ultrasonic spray-coating as a novel film fabrication technique provides a feasible scheme for large-area preparation of intelligent structural colors. Full article

Current research in the field of aviation considers actively controlled high-lift structures for future civil airplanes. Therefore, pressure data must be acquired from the airfoil surface without influencing the flow due to sensor application. For experiments in the wind and water tunnel, as well as for the actual application, the requirements for the quality of the airfoil surface are demanding. Consequently, a new class of sensors is required, which can be flush-integrated into the airfoil surface, may be used under wet conditions—even under water—and should withstand the harsh environment of a high-lift scenario. A new miniature silicon on insulator (SOI)-based MEMS pressure sensor, which allows integration into airfoils in a flip-chip configuration, is presented. An internal, highly doped silicon wiring with “butterfly” geometry combined with through glass via (TGV) technology enables a watertight and application-suitable chip-scale-package (CSP). The chips were produced by reliable batch microfabrication including femtosecond laser processes at the wafer-level. Sensor characterization demonstrates a high resolution of 38 mVV⁻¹ bar⁻¹. The stepless ultra-smooth and electrically passivated sensor surface can be coated with thin surface protection layers to further enhance robustness against harsh environments. Accordingly, protective coatings of amorphous hydrogenated silicon nitride (a-SiN:H) and amorphous hydrogenated silicon carbide (a-SiC:H) were investigated in experiments simulating environments with high-velocity impacting particles. Topographic damage quantification demonstrates the superior robustness of a-SiC:H coatings and validates their applicability to future sensors. Full article

A procedure based on energy-dispersive X-ray spectroscopy in a scanning electron microscope (SEM-EDXS) is proposed to measure ultra-thin oxide layer thicknesses to atomic scale precision in top-down instead of cross-sectional geometry. The approach is based on modelling the variation of the electron beam penetration depth and hence the depth of X-ray generation in the sample as a function of the acceleration voltage. This has been tested for the simple case of silica on silicon (SiO₂/Si) which can serve as a model system to study gate oxides in metal-on-semiconductor field-effect transistors (MOS-FETs). Two possible implementations exist both of which rely on pairs of measurements to be made: in method A, the wafer piece of interest and a reference sample (here: ultra-clean fused quartz glass for calibration of the effective k-factors of X-ray lines from elements O and Si) are analysed at the same acceleration voltage. In method B, two measurements of the apparent O/Si ratio of the same wafer sample need to be made at different acceleration voltages and from their comparison to simulations the SiO₂ layer thickness of the sample can be inferred. The precision attainable is ultimately shown to be limited by surface contamination during the experiments, as very thin carbonaceous surface layers can alter the results at very low acceleration voltages, while the sensitivity to ultra-thin surface oxides is much reduced at higher acceleration voltages. The optimal operation voltage is estimated to lie in the range of 3–15 kV. Method A has been experimentally verified to work well for test structures of thin oxides on Si-Ge/Si. Full article