Search Results (39)

A single-phase multilevel inverter with a switched-capacitor multilevel (SC-MLI) configuration is developed to provide 13-level output voltages. An improved genetic algorithm (GA) with adaptive mutation and crossover rates is employed to achieve robust harmonic mitigation by avoiding local optima and ensuring optimal performance. The topology introduces an SC-MLI that generates AC output voltage at desired levels using only two capacitors, two asymmetrical DC sources, one diode, and 11 switches. This allows the inverter to use fewer gate drivers and, hence, increases the power density of the converter. A significant challenge in the normal operation of SC-MLI circuits relates to the self-voltage balance of the capacitors, which easily becomes unstable, particularly at low modulation indices. The proposed design addresses this issue without the need for ancillary devices or complex control schemes, ensuring stable self-balanced operation across the entire spectrum of the modulation index. In this context, the harmonic mitigation technique optimized through GA applied in this inverter ensures low harmonic distortion, achieving a total harmonic distortion (THD) of 6.73%, thereby enhancing power quality even at low modulation indices. The performance of this SC-MLI is modeled under various loading scenarios using MATLAB/Simulink^® 2023b with validation performed through an Opal-RT real-time emulator. Additionally, the inverter’s overall power losses and individual switch losses, along with the efficiency, are analyzed using the simulation tool PLEXIM-PLECS. Efficiency is found to be 96.62%. Full article

High-efficiency non-isolated converters play a predominant role in electric vehicle on-board chargers to enhance the sustainability of EV charging stations. A novel single-switch configuration connected in a new parallel structure offering a higher efficiency than recently reported topologies is introduced in this article. A PV source powered single switch–switched capacitor–single inductor (SS–SC–SL) arrangement employing an intelligent, robust controller (MPC) is proposed to build a sustainable framework for electric vehicles. Notable features of this topology include improved voltage regulation, a high output gain, and maintaining a ripple-free continuous load current at a nominal duty cycle range which is commonly applicable for electric vehicle on-board chargers. In addition, several factors are included, as follows: design considerations, theoretical analysis, converter performance in CCM, and comparison with existing configurations. The converter simulation results are executed using the MATLAB software 2022a, and to verify the system performance, an experimental setup of 150 W is built and tested. The hardware results of a higher efficiency at 96.9% and a ripple-less continuous load current are achieved and validated in the laboratory. Full article

Photovoltaic (PV) modules are often connected in series to achieve the desired voltage level in practical applications. A common issue with this setup is module mismatch, which can be either permanent or temporary and is caused by various factors. The differential power processing (DPP) concept has emerged as a prominent solution to address this problem. However, a significant drawback of current DPP topologies is their reduced performance under certain conditions, particularly in cases of permanent mismatch. As a result, applications involving the DPP concept for permanent mismatches remain underexplored. In this context, the goal of this work is to develop and implement a novel DPP topology capable of increasing energy harvesting in PV systems under permanent mismatch. The proposed hybrid architecture combines features from both bidirectional buck–boost (BBB) and resonant switched capacitor (ReSC) converters. The ReSC converter operates under soft-switching conditions, minimizing undesirable losses. Key advantages of the proposed converter include fewer switches, lower voltage stress, and soft-switching operation, making it suitable for PV systems with mismatched modules. Experimental tests showed an energy harvesting improvement under the assessed conditions. Full article

Theoretical and experimental work for a novel topology of DC-DC boost switching capacitor converter is introduced in this paper. This new design is an adjustment for boost series and parallel topology developed by Makowski. Thus, a comparison between the two designs presented in this paper aims to highlight the improvement in the conversion rate of the boost converter’s output voltage while using the same number and size of capacitors. Converter analyses for both with and without load are presented. Also, a boost converter with a nonlinear ferroelectric capacitor is presented to further increase the boost converter conversion rate using advantages of the ferroelectric capacitors, such as their big dielectric constant and polarization reversal. Full article

This article presents a power-efficient DC-DC converter based on a switched-capacitor (SC) cell in power management systems supplied for fully integrated photovoltaic (PV) modules. These modules shall provide high-performance point-of-load voltage regulation. The primary objective of this study is to better utilize capacitance and switches by selecting a proper SC topology in order to improve the power efficiency of SC converters. A general steady-state performance model is investigated to optimize and compare a variety of SC DC-DC topologies. The investigation method relies on a charge-multiplier approach and considers the impact of area constraint on capacitors. To identify the most suitable topology for a given conversion ratio, the performance-limit metrics of SC converters are calculated. The analysis provides framework to determine optimum switch size and switching frequency for a two-phase 3:1 series–parallel converter for a target load current of 10 mA implemented on a 22 nm process technology. The results shows that a minimum of 250 MHz switching frequency is desirable for achieving a target efficiency greater than 85% while maintaining the minimum output voltage of 0.34 V. The analysis results are verified through MATLAB and PSpice-based simulations. Full article

Reliability is an essential factor for the operation of the Switched Reluctance Motor (SRM) drive. Electric vehicles operate in harsh environments, which may degrade the operation of power converters. These failure modes include transistor open- and short-circuits, freewheeling diode open- and short-circuits, and DC-link capacitor failures. This work presents a performance analysis of an in-wheel SRM for an electric vehicle under short-circuit (SC) and open-circuit (OC) faults of a modified Neutral-Point-Clamped Asymmetric Half-Bridge (NPC-AHB) Converter. The SRM is modeled as an in-wheel electric vehicle. A separate vehicle model attached to the motor is also developed for validation and performance of the NPC-AHB under different faulty scenarios. The performance of the modified NPC-AHB is also compared with that of a conventional AHB under faulty conditions for an in-wheel 8/6 SRM. The performance indicators such as torque, speed, current, and flux are presented from MATLAB/Simulink 2023b numerical simulations. Full article

Photovoltaic (PV), battery, and fuel cell (FC) technologies are emerging forms of renewable energy gaining popularity. However, one of the key limitations is their production of direct current (DC) voltage, which hinders the connectivity and integration with the electrical grid. To address this issue, various DC/DC boost converters have been introduced. This study presents an innovative Luo converter with a switched-inductor–capacitor (SLC) cell at the input and a switched-capacitor (SC) cell at the output. The SLC cell not only increases the input voltage, but also enhances the source’s lifespan and reliability. The SC cell further amplifies the voltage, especially for high-gain applications. The proposed converter simplifies control processes by using a single power switch, significantly boosting the input voltage by 21 times with a duty ratio of 0.8. This surpasses the gains achieved by conventional boost converters by over fourfold and Luo converters by sevenfold. The second challenge when a converter is connected to these voltage sources is the potential reduction in the lifespan of the sources and the overall system due to large input current ripples. The proposed converter addresses this issue by incorporating a switched-capacitor cell on the input side. This cell charges the inductors in parallel and discharges them in series, reducing the magnitude of the input current. Another advantage of the proposed converter is its simplicity, as it employs only one power switch, minimizing the complexity of the controller system. Additionally, the distribution of the output voltage passing through the diodes between the switch and output capacitor helps mitigate voltage stress for all semiconductor devices and capacitors. The study includes thorough mathematical analyses, simulations, and laboratory tests to validate the research’s theoretical foundations. Full article

In order to meet the demands of desirable efficiency, transformerless DC/DC equipment with great voltage step-down are inevitable needed. This research offers a unique type of high-frequency, high-voltage-gain DC/DC converter, which comprises a switched capacitor (SC) converter and a buck converter. Thanks to the transformation of a two-stage converter to a single-stage converter, it has a considerable ratio of step-down voltage transformation and a reasonable duty cycle. In addition, it can permit low voltage stress on the switches. The simple control method and easy driving circuit implementation makes it scalable for high-power-level devices. Low cost can be realized as fewer components are needed. Under all operational circumstances, total soft-charging and low equipment voltage stresses are accomplished. Compared to those classic high-voltage-gain converters, the proposed converter exhibits merits of higher efficiency, higher flexibility, lower ripples, and lower costs. A comprehensive analysis is carried out for the converter’s steady-state operations. With a 1 MHz switching frequency, a 900 W prototype of a 20-time converter is constructed, with a peak efficiency of 92.5%. Simulations and experiments verify the effectiveness of the theoretical investigation of the converter’s operation. Full article

In this paper, a new control scheme for buck converters was proposed. The buck converter utilizes the dual control loop to improve transient response and has the constant switching frequency. The control scheme is mainly as follows: (a) The switch-ON time is regulated by the constant frequency mechanism. (b) The switch-OFF time is regulated by the output voltage. The spec/features of the proposed converter are listed as: (1) The buck converter has an output of 1.0–2.5 V for the input of 3.0–3.6 V. The load current ranges from 100 mA to 500 mA. (2) The actual current sensor is not required. (3) The simulation results show that the recovery time is less than 1.6 μs during load changes. (4) The variation in switching frequency is smaller than 1.05% over the output range of 1.0–2.5 V. (5) This circuit can be fabricated in future by UMC 0.18 μm 1P6M CMOS processes. This paper depicts the control scheme, theoretical analysis, and implementation. Full article

This article presents a single-stage five-level boost inverter (5L-SBI) topology with reduced power components. The proposed topology falls under the self-balanced switch-capacitors (SCs) type and combines both a DC/DC boost converter and inverter with a switched-capacitor cell. The advantages of proposed topologies include the following: the number of switch counts is reduced, the maximum voltage gain is two times higher than the input voltage, and the capacitor’s charging current is suppressed. Further, the proposed topology cascaded, and three-phase extensions are presented. To attest, the advantages of the proposed topology are thoroughly compared with other recent SCI topologies. The proposed topology is verified under dynamic loading conditions, and the results are presented, considering a 600 W laboratory prototype model. Full article

We present a high-power conversion efficiency (PCE) on-chip switched-capacitor (SC) DC–DC step-up converter for a fully implantable neural interface operating with less than a few tens µW from energy harvesting. To improve the PCE in such light loads and wide variations of voltage-conversion ratio (VCR), which is a typical scenario for ultra-low-power fully implantable systems depending on energy harvesting, a phase-reduced soft-charging technique has been implemented in a step-up converter, thereby achieving very low VCR-sensitive PCE variation compared with other state-of-the-art works. The proposed DC–DC converter has been fabricated in a standard 180 nm CMOS 1P6M process. It exhibits high PCE (~80%) for wide input and output ranges from 0.5 V to 1.2 V and from 1.2 V to 1.8 V, respectively, with switching frequencies of 0.3–2 MHz, achieving a peak efficiency of 82.6% at 54 µW loads. Full article

The increasing interest in renewable energy sources has brought attention to large voltage-gain dc–dc converters; among the different available solutions to perform a large voltage-gain conversion, this article presents an overview of non-isolated dc–dc converter topologies that utilize switched-capacitor circuits, i.e., diode-capacitors voltage multipliers. The review includes combinations of a traditional power stage with a diode-capacitor-based voltage multiplier, such as the multilevel boost converter. This article starts by reviewing switched-capacitor (SC) circuits, different topologies, and different types of charge exchange; it provides a straightforward analysis to understand the discharging losses. It then covers the multilevel boost converter and other topologies recently introduced to the state-of-the-art. Special attention is put on SC circuits with resonant charge interchange that have recently been probed to achieve very good efficiency. An additional contribution of the article is new proof of the discharging losses in resonant switched-capacitor circuits focused on the initial and final stored energy in capacitors, and this proof explains the relatively large efficiency obtained with SC resonant converters. Full article

Electrostatic vibration energy transducers have a relatively high output impedance (R_ET) and open-circuit voltage (V_IN), so that voltage-down conversion is required for sensor/RF ICs. Switched-capacitor converters are the best candidate to create small-form-factor technology and are a low-cost solution because of their capability to fully integrate into sensor/RF ICs. To design switched-capacitor voltage-down converters (SC-VDCs) with a minimum circuit area for electrostatic vibration energy transducers, two steps are required. The first step requires an optimum design of DC-DC SC-VDCs driven by high R_ET with a minimum circuit area, and the second step requires an optimum design of AC-DC SC-VDCs based on the first step, to minimize the converter circuit area. This paper discusses circuit analysis and design optimization aimed at the first step. Switching frequency, the number of stages and the capacitance per stage were determined as a function of R_ET, V_IN and the output voltage (Vo) and current (Io) to the load, to achieve a minimum circuit area. The relationship between Io and the power conversion efficiency was studied as well. The performance was validated by SPICE simulation in 250 nm BCD technology. An optimum design flow was proposed to design DC-DC SC-VDCs driven by high R_ET with a minimum circuit area under conditions where R_ET, V_IN, Vo and Io were given. The second design step remains as future work. Full article

This paper presents a novel concept of the DC-AC system with the input voltage boost ability, seven-level output voltage modulation, and the input AC current reduction at the double frequency of the output voltage. The system integrates the NPC full-bridge inverter which is composed of four-level legs and an active input voltage balancer (AIVB). The DC-link is composed of three capacitors connected in a series. The source of the energy is connected directly to the middle capacitor while the upper and lower capacitors of the DC-link are charged by the AIVB. The operation of the AIVB leads to balancing of the DC-link voltage and a three-fold boosting of the input voltage. The AIVB utilizes a novel switched-capacitor (SC) topology and can be designed as a low-volume quasi-magneticless converter with a simple open-loop control. One of the proposed methods of the control of the AIVB allows for a double frequency reduction in the input current. The application of the AIVB allows for the use of a seven-level NPC full-bridge (FB) inverter with a simple classic carrier-based PWM which is not applicable in the typical DC-link configurations. This paper presents the converter’s concept, its operation, control methods, and the results of simulations and experiments. Full article

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm² and is packaged in a QFN−88 of 10 × 10 mm². Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μV_rms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded. Full article