Search Results (22)

This paper investigates 6.5 kV SiC trench gate p-channel IGBTs using Sentaurus TCAD simulations. The proposed superjunction structure is compared to conventional designs to highlight its advantages. The p-IGBT, fabricated on an n-type substrate, offers notable commercial advantages over n-IGBTs on p-type substrates. The n-shield can effectively protect the trench gate oxide in the corners of SiC. The n-shield and n-pillar can be either floating or grounded, with the floating shield condition significantly enhancing injection and improving forward conduction performance. The superjunction floating shield p-IGBT (SJFS-p-IGBT) improves forward conduction voltage (V_F) by 47% and 15% compared to conventional planar gate p-IGBT (CP-p-IGBT) and grounded shield p-IGBT (CGS-p-IGBT), respectively. For switching characteristics, the superjunction grounded shield p-IGBT (SJGS-p-IGBT) improves turn-off time (t_off) by 15% compared to the conventional floating shield p-IGBT (CFS-p-IGBT). The trade-off between V_F and turn-off energy (E_off) is analyzed, showing that the SJFS-p-IGBT offers a better trade-off. A negative temperature coefficient is observed at high buffer layer doping concentration and elevated temperatures, leading to an increase in V_F. This provides design guidance for devices operating in parallel at high temperatures. These results demonstrate the SJ’s potential to enhance efficiency and performance for ultra-high voltage applications. Full article

High efficiency and high power density are key targets in modern power conversion. Operating power converters at high switching frequencies enables the use of smaller passive components, which, in turn, facilitate achieving high power density. However, the concurrent increase in switching frequency and power density leads to efficiency and overheating issues. Soft switching techniques are typically employed to minimize switching losses and significantly improve efficiency by reducing power losses. However, the hysteresis behavior of the power electronics devices’ output capacitance, C_OSS, is the cause of regrettable losses in Super-Junction (SJ) MOSFETs, SiC MOSFETs, and GaN HEMTs, which are usually adopted in soft switching-based conversion schemes. This paper reviews the techniques for measuring hysteresis traces and power losses, as well as the understanding of the phenomenon to identify current research trends and open problems. A few studies have reported that GaN HEMTs tend to exhibit the lowest hysteresis losses, while Si superjunction (SJ) MOSFETs often show the highest. However, this conclusion cannot be generalized by comparing the results from different works because they are typically made across devices with different (when the information is reported) breakdown voltages, on-state resistances, die sizes, and test conditions. Moreover, some recent investigations using advanced TCAD simulations have demonstrated that newer Si-SJ MOSFETs employing trench-filling epitaxial growth can achieve significantly reduced hysteresis losses. Similarly, while multiple studies confirm that hysteresis losses increase with increasing dv/dt and decreasing temperature, the extent of this dependence varies significantly with device structure and test methodology. This difficulty in obtaining a general conclusion is due to the lack of proper figures of merit that account for hysteresis losses, making it problematic to evaluate the suitability of different devices in resonant converters. This problem highlights the primary current challenge, which is the development of a standard and automated method for characterizing C_OSS hysteresis. Consequently, significant research effort must be invested in addressing this main challenge and the other challenges described in this study to enable power electronics researchers and practitioners to develop resonant converters properly. Full article

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (R_DS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in R_DS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in R_DS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs. Full article

This study proposes an AlGaN/GaN current aperture vertical electron transistor (CAVET) featuring a double superjunction (SJ) to enhance breakdown voltage (BV) and investigates its electrical characteristics via technology computer-aided design (TCAD) Silvaco Atlas simulation. An additional p-pillar was formed beneath the gate current blocking layer to create a lateral depletion region that provided a high off-state breakdown voltage. To address the tradeoff between the drain current and off-state breakdown voltage, the key design parameters were carefully optimized. The proposed device exhibited a higher off-state breakdown voltage (2933 V) than the device with a single SJ (2786 V), although the specific on-resistance of the proposed method (1.29 mΩ·cm⁻²) was slightly higher than that of the single SJ device (1.17 mΩ·cm⁻²). In addition, the reverse transfer capacitance was improved by 15.6% in the proposed device. Full article

In recent years, high-voltage analog switches have been widely used in various fields. To handle complex use scenarios, high-voltage analog switches need to achieve the goals of low on-resistance, high isolation performance, high response speed, and high voltage withstand range. Traditional high-voltage analog switches have issues such as low integration, large area, and slow response speed. This paper uses a super junction MOSFET (SJ-MOS) with a 0.18 μm SOI process and a solid-state relay (SSR) structure to implement a high-voltage analog switch. A gate drive circuit suitable for low gate-source breakdown voltage is proposed to maintain the gate-source voltage, achieving a low on-resistance of 24 Ω and high isolation. Compared with traditional high-voltage analog switches, it achieves higher performance with a smaller area. Full article

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV²/R_on,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively. Full article

This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (R_ON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV²/R_ON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-R_ON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results. Full article

This paper explores the operation mechanism of the superjunction structure in RC-IGBTs based on carrier distribution and analyzes the advantages and challenges associated with its application in RC-IGBTs for the first time. A Partial Schottky Collector Superjunction Reverse Conduction IGBT (PSC-SJ-RC-IGBT) is proposed to address these issues. The new structure eliminates the snapback phenomenon. Furthermore, by leveraging the unipolar conduction of the Schottky diode and its fast turn-off characteristics, the proposed device significantly reduces the turn-off power consumption and reverse recovery charge. With medium pillar doping concentration, the turn-off loss of the PSC-SJ-RC-IGBT decreases by 54.1% compared to conventional superjunction RC-IGBT, while the reverse recovery charge is reduced by 52.6%. Full article

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t_sc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (R_on,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Q_gd) and gate-drain capacitance (C_gd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process. Full article

This paper proposes and simulates research on the reverse recovery characteristics of two novel superjunction (SJ) MOSFETs by adjusting the doping profile. In the manufacturing process of the SJ MOSFET using multilayer epitaxial deposition (MED), the position and concentration of each Boron bubble can be adjusted by designing different doping profiles to adjust the resistance of the upper half P-pillar. A higher P-pillar resistance can slow down the sweep out speed of hole carriers when the body diode is turned off, thus resulting in a smoother reverse recovery current and reducing the current recovery rate (d${}_{ir}$/d${}_t$) from a peak to zero. The simulation results show that the reverse recovery peak current (I${}_{rrm}$) of the two proposed devices decreased by 5% and 3%, respectively, compared to the conventional SJ. Additionally, the softness factor (S) increased by 64% and 55%, respectively. Furthermore, this study also demonstrates a trade-off relationship between static and reverse recovery characteristics with the adjustable doping profile, thus providing a guideline for actual application scenarios. Full article

A thin Silicon-On-Insulator (SOI) LDMOS with ultralow Specific On-Resistance (R_on,sp) is proposed, and the physical mechanism is investigated by Sentaurus. It features a FIN gate and an extended superjunction trench gate to obtain a Bulk Electron Accumulation (BEA) effect. The BEA consists of two p-regions and two integrated back-to-back diodes, then the gate potential V_GS is extended through the whole p-region. Additionally, the gate oxide W_oxide is inserted between the extended superjunction trench gate and N-drift. In the on-state, the 3D electron channel is produced at the P-well by the FIN gate, and the high-density electron accumulation layer formed in the drift region surface provides an extremely low-resistance current path, which dramatically decreases the R_on,sp and eases the dependence of R_on,sp on the drift doping concentration (N_drift). In the off-state, the two p-regions and N-drift deplete from each other through the gate oxide W_oxide like the conventional SJ. Meanwhile, the Extended Drain (ED) increases the interface charge and reduces the R_on,sp. The 3D simulation results show that the BV and R_on,sp are 314 V and 1.84 mΩ∙cm⁻², respectively. Consequently, the FOM is high, reaching up to 53.49 MW/cm², which breaks through the silicon limit of the RESURF. Full article

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage V_DS of 300 V and LET = 120 MeV·cm²/mg, respectively. The total charges of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ−, CT−, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage V_DS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm²/mg to 120 MeV·cm²/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are approximately 100 MeV·cm²/mg, 15 MeV·cm²/mg, 15 MeV·cm²/mg, and 60 MeV·cm²/mg, respectively, while the value of V_DS = 1100 V. Full article

A novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation. In the SJ-RC-IGBT, the parasitic P/N/P/N structure as thyristor or Shockley diode demonstrates large conductivity due to an overabundance of carriers for reverse conduction. By preventing electrons from leaking across the N+ region at the collector side, the extra electron-blocking (EB) layer introduced in the SJ-RC-IGBT can dramatically enhance electron–hole pairs in the N/P-pillars. Hence, the SJ-RC-IGBT demonstrates a low on-state voltage (V_on). In addition, snapback-free characteristics and a large safe operating area (SOA) are also achieved in the SJ-RC-IGBT. During the turn-off process, a significant amount of electrons are extracted by parasitic MOS across the EB layer at the collector side to decrease the turn-off loss (E_off). According to the optimized results, the SJ-RC-IGBT with EB layer obtains an ultralow E_off of 3.9 mJ/cm² at V_on = 1.38 V with 88% and 81% decreases, respectively, compared with the conventional reverse-conducting IGBT (CRC-IGBT) and superjunction IGBT (SJ-IGBT). Full article

In this paper, a novel silicon super-junction (SJ) MOSFET embedded with a soft reverse recovery body diode is proposed and studied by numerical simulation. The device introduces an n⁺-buffer layer between the n⁻-buffer layer and the n⁺-substrate to improve the reverse recovery behaviour of its body diode. The n⁺-buffer layer provides residual carriers during the reverse recovery process, reduces the overshoot voltage, and suppresses oscillation. Simulated results demonstrate that the increment of the on-resistance and the drain-to-source overshoot voltage can be respectively kept below 5% and 20 V, if a 10 μm n⁺-buffer layer whose impurity concentration ranges from 4 × 10¹⁵ cm⁻³ to 6 × 10¹⁶ cm⁻³ is used. In addition, the fabrication process is the same as that of the conventional SJ-MOSFET. These features make the proposed SJ-MOSFET suitable for inverter applications. Full article

This work presents a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology. For this, a database with 91 power MOSFETs from different manufacturers was built. MOSFET losses are related to individual characteristics of the technology: drain-source on-state resistance, input capacitance, Miller capacitance and internal gate resistance. The total losses are evaluated considering a drain-source voltage of 400 V, power levels from 1 kW to 16 kW (1 A–40 A) and frequencies from 1 kHz to 500 kHz. A methodology for selecting power MOSFETs in power electronics applications is also presented. Full article