Integrating a Soft Body Diode in the Super-Junction MOSFET by Using an n−/n+-Buffer Layer

In this paper, a novel silicon super-junction (SJ) MOSFET embedded with a soft reverse recovery body diode is proposed and studied by numerical simulation. The device introduces an n+-buffer layer between the n−-buffer layer and the n+-substrate to improve the reverse recovery behaviour of its body diode. The n+-buffer layer provides residual carriers during the reverse recovery process, reduces the overshoot voltage, and suppresses oscillation. Simulated results demonstrate that the increment of the on-resistance and the drain-to-source overshoot voltage can be respectively kept below 5% and 20 V, if a 10 μm n+-buffer layer whose impurity concentration ranges from 4 × 1015 cm−3 to 6 × 1016 cm−3 is used. In addition, the fabrication process is the same as that of the conventional SJ-MOSFET. These features make the proposed SJ-MOSFET suitable for inverter applications.


Introduction
The performance of the traditional silicon-based power MOSFET is limited by the contradictory relationship between its specific on-resistance and breakdown voltage, which is known as the silicon limit [1]. In order to overcome this limitation, new semiconductor materials are adopted and novel device structures are developed. Power MOSFETs made from the third-generation semiconductors, such as the SiC MOSEFT and GaN HEMT, have demonstrated their superior performance over their silicon-based counterparts [2,3]. On the other hand, the super-junction (SJ) MOSFET breaks the silicon limit by using alternative highly doped n-pillars and p-pillars in its drift region [1,[4][5][6]. The most attractive advantage is that its specific on-resistance is less than one fifth of that of the conventional power MOSFET with the same rated voltage. As a result, the device area and parasitic capacitors are reduced. These features make it suitable for high-frequency circuits. Therefore, it is now widely used in modem power converters [7]. One of its disadvantages is the poor reverse recovery behaviour of its body diode, which can be used as the free-wheeling diode in power inverters [8]. In inverter circuits with an inductance load, free-wheeling diodes are necessary to conduct load currents when power devices are switched off. There are two main problems with its body diodes: the reverse recovery charge is large, and the reverse recovery current is snappy [9]. The former causes high energy loss and reduces power efficiency. The latter causes overshoot voltage and oscillation. The reverse recovery problem of the body diode is a key scientific problem toward super-junction MOSFETs. It limits their applications in power inverters. Many solutions have been proposed to reduce the reverse recovery charge, such as lifetime killing techniques using irradiation by electrons, protons, helium ion and heavy metal doping by gold, platinum [10,11]. Some researchers suggest integrated unipolar diodes [12,13]. Little attention has been paid to the snappy reverse recovery current. Modern SJ-MOSFETs usually use a lightly doped n − -buffer layer to improve the softness of the reverse recovery current [14]. The thicker the n − -buffer layer, the softer the reverse recovery current [15]. However, a thick n − -buffer layer increases the on-resistance of the SJ-MOSFET.
In this study, we propose a practical solution to integrate a soft body diode in the SJ-MOSFET without compromising its on-resistance. It uses an additional n + -buffer layer to reduce the overshoot voltage and suppress oscillation during the reverse recovery process of the body diode. The device structure and mechanism are shown in Section 2. Section 3 summarizes the optimised results. The conclusion is in Section 4. Figure 1 shows the schematic cross-sections of the conventional SJ-MOSFET and the proposed SJ-MOSFET, which both have a symmetrical interdigitated layout. The difference lies in the buffer region. As shown in Figure 1b, an n + -buffer layer is added between the n − -buffer layer and the n + -substrate in the proposed structure. Its impurity concentration is much lower than that of the n + -substrate but much higher than that of the n − -buffer layer. It is used to improve the softness of the body diode. As explained before [9], the reverse recovery current of the conventional SJ-MOSEFT is snappy because there are not enough carriers when it reaches its negative peak value. Since the n + -substrate is heavily doped and the net recombination rate in the semiconductor is proportional to the carrier density [16], the holes' density in the n + -substrate is tiny. Once the pillars are depleted, only a few carriers exist in the n − -buffer layer. Then, the reverse recovery current drops sharply. In the proposed SJ-MOSEFT, since the n + -buffer layer has a much lower impurity concentration than the n + -substrate, some nonequilibrium carriers accumulate in this region when the body diode is forward biased. Then, during the reverse recovery process, these carriers keep the current continuous after the pillars are depleted. On the other hand, the n + -buffer layer introduces the series resistance. To reduce its impact on the on-resistance and the breakdown voltage, its impurity concentration should be higher than those of pillars and the n − -buffer layer.

Device Structure and Mechanism
Micromachines 2022, 13, x FOR PEER REVIEW 2 of 9 attention has been paid to the snappy reverse recovery current. Modern SJ-MOSFETs usually use a lightly doped n − -buffer layer to improve the softness of the reverse recovery current [14]. The thicker the n − -buffer layer, the softer the reverse recovery current [15]. However, a thick n − -buffer layer increases the on-resistance of the SJ-MOSFET.
In this study, we propose a practical solution to integrate a soft body diode in the SJ-MOSFET without compromising its on-resistance. It uses an additional n + -buffer layer to reduce the overshoot voltage and suppress oscillation during the reverse recovery process of the body diode. The device structure and mechanism are shown in Section II. Section III summarizes the optimised results. The conclusion is in Section IV. Figure 1 shows the schematic cross-sections of the conventional SJ-MOSFET and the proposed SJ-MOSFET, which both have a symmetrical interdigitated layout. The difference lies in the buffer region. As shown in Figure 1b, an n + -buffer layer is added between the n − -buffer layer and the n + -substrate in the proposed structure. Its impurity concentration is much lower than that of the n + -substrate but much higher than that of the n − -buffer layer. It is used to improve the softness of the body diode. As explained before [9], the reverse recovery current of the conventional SJ-MOSEFT is snappy because there are not enough carriers when it reaches its negative peak value. Since the n + -substrate is heavily doped and the net recombination rate in the semiconductor is proportional to the carrier density [16], the holes' density in the n + -substrate is tiny. Once the pillars are depleted, only a few carriers exist in the n − -buffer layer. Then, the reverse recovery current drops sharply. In the proposed SJ-MOSEFT, since the n + -buffer layer has a much lower impurity concentration than the n + -substrate, some nonequilibrium carriers accumulate in this region when the body diode is forward biased. Then, during the reverse recovery process, these carriers keep the current continuous after the pillars are depleted. On the other hand, the n + -buffer layer introduces the series resistance. To reduce its impact on the on-resistance and the breakdown voltage, its impurity concentration should be higher than those of pillars and the n − -buffer layer.

Device Structure and Mechanism
(a) (b) Figure 1. Schematic cross-sections and doping profiles along the n-pillar center of (a) the conventional SJ-MOSFET and (b) the proposed SJ-MOSFET. An n + -buffer layer is introduced in the proposed SJ-MOSFET. Its impurity concentration is much lower than that of the n + -substrate but much higher than that of the n − -buffer layer.
In the following simulations, 650 V-rated silicon SJ-MOSFEFTs with a half cell pitch of b = 6 μm are used. The pillar thickness TSJ is 40 μm. For simplicity, SJ pillars are uniformly doped. The p-pillar concentration Np and the n-pillar concentration Nn are both set to 4 × 10 15 cm −3 . The thickness of the n − -buffer layer TBn-is 10 μm. Its impurity concentration TBn-is 1 × 10 15 cm −3 . The thickness and the impurity concentration of the n + -buffer layer, namely TBn+ and NBn+, are respectively chosen as 10 μm and 4 × 10 16 cm −3 , unless otherwise An n + -buffer layer is introduced in the proposed SJ-MOSFET. Its impurity concentration is much lower than that of the n + -substrate but much higher than that of the n − -buffer layer.
In the following simulations, 650 V-rated silicon SJ-MOSFEFTs with a half cell pitch of b = 6 µm are used. The pillar thickness T SJ is 40 µm. For simplicity, SJ pillars are uniformly doped. The p-pillar concentration N p and the n-pillar concentration N n are both set to 4 × 10 15 cm −3 . The thickness of the n − -buffer layer T Bn-is 10 µm. Its impurity concentration T Bn-is 1 × 10 15 cm −3 . The thickness and the impurity concentration of the n + -buffer layer, namely T Bn+ and N Bn+ , are respectively chosen as 10 µm and 4 × 10 16 cm −3 , unless otherwise specified. Each device has an area of 10 mm 2 . The Sentaurus Device simulator [17] is used to analyse the electrical performances of devices. Employed mobility models include the DopingDenpendnce model, the HighFieldSturation model, and the Enormal model. The Shockley-Read-Hall recombination model and the Auger recombination model are also used. The Okuto avalanche model is used in blocking characteristics' analysis. The electron lifetime and the hole lifetime are, respectively, 3 µs and 1 µs.
To explore the reverse recovery behaviour of body diodes, the double pulse test is carried out in mix-mode simulations. It uses the circuit shown in Figure 2. The Device Under Test (DUT) and the switching transistor M0 are both constructed with finite element models. The DUT is marked in red. To close the channel, its gate electrode and source electrode are connected. Then, its body diode serves as the free-wheeling diode. Other components are constructed with compact models. L D and L S are the load inductor and the parasitic inductor, respectively. R G is the gate resistor. It controls the commutation velocity di/dt during the reverse recovery process. V D is bus voltage source. V G drives M0 with a double pulse signal.
Micromachines 2022, 13, x FOR PEER REVIEW 3 of 9 specified. Each device has an area of 10 mm 2 . The Sentaurus Device simulator [17] is used to analyse the electrical performances of devices. Employed mobility models include the DopingDenpendnce model, the HighFieldSturation model, and the Enormal model. The Shockley-Read-Hall recombination model and the Auger recombination model are also used. The Okuto avalanche model is used in blocking characteristics' analysis. The electron lifetime and the hole lifetime are, respectively, 3 μs and 1 μs.
To explore the reverse recovery behaviour of body diodes, the double pulse test is carried out in mix-mode simulations. It uses the circuit shown in Figure 2. The Device Under Test (DUT) and the switching transistor M0 are both constructed with finite element models. The DUT is marked in red. To close the channel, its gate electrode and source electrode are connected. Then, its body diode serves as the free-wheeling diode. Other components are constructed with compact models. LD and LS are the load inductor and the parasitic inductor, respectively. RG is the gate resistor. It controls the commutation velocity di/dt during the reverse recovery process. VD is bus voltage source. VG drives M0 with a double pulse signal.   Figure 3b,c show respective equipotential lines at VDS = 650 V. The extracted breakdown voltage of the conventional SJ-MOSFET is 979.5 V, while that of the proposed device is 979.6 V. Their blocking characteristics are almost the same, because their voltage-sustaining layers, namely the pillars and the n − -buffer layer, are the same. The n + -buffer layer is hardly contributed to the breakdown voltage due to its high impurity concentration. As shown in Figure 3c, the depletion region in the n + -buffer layer is negligible.   Figure 3b,c show respective equipotential lines at V DS = 650 V. The extracted breakdown voltage of the conventional SJ-MOSFET is 979.5 V, while that of the proposed device is 979.6 V. Their blocking characteristics are almost the same, because their voltage-sustaining layers, namely the pillars and the n − -buffer layer, are the same. The n + -buffer layer is hardly contributed to the breakdown voltage due to its high impurity concentration. As shown in Figure 3c, the depletion region in the n + -buffer layer is negligible. Figure 4 compares output characteristics of the two SJ-MOSFETs. It is demonstrated that the on-state current of the proposed SJ-MOSFET is a little smaller than that of the conventional device. The on-resistance, R ON , of the proposed SJ-MOSFET and conventional SJ-MOSFET, extracted at V GS = 10 V, are 207.7 mΩ and 209.3 mΩ, respectively. The increment of on-resistance, ∆R ON , is 1%. ∆R ON is defined as the percentage increase in on-resistance with respect to the conventional device

Results and Discussion
where R ON, proposal and R ON, convention are on-resistances of the proposed SJ-MOSEFT and the conventional SJ-MOSEFT, respectively. This increment comes from the series resistance of the n + -buffer layer R Bn+ , as illustrated in Figure 1b. Since the impurity concentration of the n + -buffer layer is lower than that of the n + -substrate, its series resistance is also larger. R Bn+ can be simply calculated as where q is electron charge, µ n is the electron mobility, and A is the area of the device. Hence, R Bn+ , as well as ∆R ON , increases with T Bn+ and decreases with N Bn+ .
where RON, proposal and RON, convention are on-resistances of the proposed SJ-MOSEFT and t conventional SJ-MOSEFT, respectively. This increment comes from the series resistan of the n + -buffer layer RBn+, as illustrated in Figure 1b. Since the impurity concentration the n + -buffer layer is lower than that of the n + -substrate, its series resistance is also larg RBn+ can be simply calculated as where q is electron charge, μn is the electron mobility, and A is the area of the devi Hence, RBn+, as well as ΔRON, increases with TBn+ and decreases with NBn+.
where RON, proposal and RON, convention are on-resistances of the proposed SJ-MOSEFT and the conventional SJ-MOSEFT, respectively. This increment comes from the series resistance of the n + -buffer layer RBn+, as illustrated in Figure 1b. Since the impurity concentration of the n + -buffer layer is lower than that of the n + -substrate, its series resistance is also larger. RBn+ can be simply calculated as where q is electron charge, μn is the electron mobility, and A is the area of the device. Hence, RBn+, as well as ΔRON, increases with TBn+ and decreases with NBn+.     Figure 5b. For the conventional device, since both the SJ pillars and the n − -buffer layer are lightly doped, a large amount of non-equilibrium carriers accumulated. The injected holes vanish quickly in the n + -substrate because the recombination rate is very high in this heavily doped region. For the proposed device, since the n + -buffer layer is not heavily doped, the recombination rate is much smaller than that in the n + -substrate. Thus, many non-equilibrium carriers also accumulate there. These additional carriers help to the improve the reverse recovery behaviour of its body diode. ventional device, since both the SJ pillars and the n − -buffer layer are lightly doped, a large amount of non-equilibrium carriers accumulated. The injected holes vanish quickly in the n + -substrate because the recombination rate is very high in this heavily doped region. For the proposed device, since the n + -buffer layer is not heavily doped, the recombination rate is much smaller than that in the n + -substrate. Thus, many non-equilibrium carriers also accumulate there. These additional carriers help to the improve the reverse recovery behaviour of its body diode.  Figure 6a shows reverse recovery waveforms with di/dt = 200 A/μs and LS = 10 nH, at 300 K. VD is 400 V. It is obvious that the reverse recovery current of the proposed device is softer than that of the conventional device. During the reverse recovery period, the maximum commutation velocity di/dtmax decreases by 62.9%, from 2.4 × 10 10 A/s to 8.9 × 10 9 A/s. As a result, the drain-to-source overshoot voltage ΔVDS decreases from 220.4 V to 11.5 V. Figure 6b,c show hole density distributions at select points. Once the space charge region reaches the n − -buffer region at t2(t2′), the reverse recovery current reaches its negative peak value. After that, the reverse recovery current decreases gradually. For the conventional device, only a few holes exit in the SJ pillars and the n − -buffer layer. Then, its reverse recovery current decays steeply, which causes a large voltage spike. On the other hand, for the proposed device, there are still plenty of holes in the n − /n + -buffer layer. Therefore, the reverse recovery current decays slowly and the voltage spike is suppressed. Of course, it takes some time to extract these residual holes. Thus, the reverse recovery charges increase. The reverse recovery behaviour of the proposed device can be improved further by increasing the thickness, or decreasing the impurity concentration of the n + -buffer layer.  Figure 6a shows reverse recovery waveforms with di/dt = 200 A/µs and L S = 10 nH, at 300 K. V D is 400 V. It is obvious that the reverse recovery current of the proposed device is softer than that of the conventional device. During the reverse recovery period, the maximum commutation velocity di/dt max decreases by 62.9%, from 2.4 × 10 10 A/s to 8.9 × 10 9 A/s. As a result, the drain-to-source overshoot voltage ∆V DS decreases from 220.4 V to 11.5 V. Figure 6b,c show hole density distributions at select points. Once the space charge region reaches the n − -buffer region at t 2 (t 2 ), the reverse recovery current reaches its negative peak value. After that, the reverse recovery current decreases gradually. For the conventional device, only a few holes exit in the SJ pillars and the n − -buffer layer. Then, its reverse recovery current decays steeply, which causes a large voltage spike. On the other hand, for the proposed device, there are still plenty of holes in the n − /n + -buffer layer. Therefore, the reverse recovery current decays slowly and the voltage spike is suppressed. Of course, it takes some time to extract these residual holes. Thus, the reverse recovery charges increase. The reverse recovery behaviour of the proposed device can be improved further by increasing the thickness, or decreasing the impurity concentration of the n + -buffer layer. Table 1 summarizes performances of the above two SJ-MOSFETs. The transfer characteristics of the two SJ-MOSEFT are not exhibited. Their threshold voltages are equal because they have the same MOS channel structure. The most affected parameters are R ON and ∆V DS (or di/dt max ). They are contradictory. Increasing T Bn+ or decreasing N Bn+ introduces more non-equilibrium carriers in the n + -buffer layer. Then, both di/dt max and ∆V DS are reduced. However, R ON also increases, as Equation (2) demonstrates. For example, ∆V DS can be reduced to 9.9 V by increasing T Bn-from 10 µm to 15 µm, as listed in Table 1. However, R ON increases to 229.4 mΩ. The increment exceeds 10%. Table 1 also includes a SJ-MOSEFT with reduced Q RR ; but, its V F and ∆V DS increases. In the rest of this section, we discuss the influence of N Bn+ and T Bn+ on ∆V DS and ∆R ON . Figure 7a shows reverse recovery waveforms of devices with T Bn+ = 10 µm and N Bn+ ranges from 1 × 10 19 cm −3 to 1 × 10 15 cm −3 . N Bn+ = 1 × 10 19 cm −3 represents the conventional SJ-MOSFET. As N Bn+ decreases, the reverse recovery current becomes smoother. Both di/dt max and ∆V DS decreases. Oscillation is also gradually suppressed. This is because the net recombination rate in the semiconductor is proportional to the carrier density. If N Bn+ decreases, the net recombination rate also decreases. Then, more holes accumulate in the n + -buffer layer when the body diode is forward biased. During the reverse recovery process, they make the reverse recovery current smoother. Figure 7b shows reverse recovery waveforms of devices with N Bn+ = 4 × 10 16 cm −3 and T Bn+ ranges from 0 µm to 40 µm. T Bn+ = 0 µm represents the conventional SJ-MOSFET. As T Bn+ increases, the reverse recovery current becomes smoother. Both di/dt max and ∆V DS decreases. Oscillation is also gradually suppressed. This is because more holes accumulate in the n + buffer layer Micromachines 2022, 13, 2193 6 of 8 when the body diode is forward biased if T Bn+ increases. During the reverse recovery process, they make the reverse recovery current smoother. The improvement becomes insignificant once T Bn+ exceeds 20 µm. The reason is that holes deep into the n + buffer layer recombine with electrons during the reverse recovery process. Their contribution to the reverse recovery current is negligible.  Table 1 summarizes performances of the above two SJ-MOSFETs. The transfer characteristics of the two SJ-MOSEFT are not exhibited. Their threshold voltages are equal because they have the same MOS channel structure. The most affected parameters are RON and ΔVDS (or di/dtmax). They are contradictory. Increasing TBn+ or decreasing NBn+ introduces more non-equilibrium carriers in the n + -buffer layer. Then, both di/dtmax and ΔVDS are reduced. However, RON also increases, as Equation (2) demonstrates. For example, ΔVDS can be reduced to 9.9 V by increasing TBn-from 10 μm to 15 μm, as listed in Table 1. However, RON increases to 229.4 mΩ. The increment exceeds 10%. Table 1 also includes a SJ-MOSEFT with reduced QRR; but, its VF and ΔVDS increases. In the rest of this section, we discuss the influence of NBn+ and TBn+ on ΔVDS and ΔRON.

Device BV (V) RON (mΩ) VF (V) di/dtmax (A/s) ΔVDS (V) QRR (μC)
Convention  Figure 7a shows reverse recovery waveforms of devices with TBn+ = 10 μm and NBn+ ranges from 1 × 10 19 cm −3 to 1 × 10 15 cm −3 . NBn+ = 1 × 10 19 cm −3 represents the conventional SJ-MOSFET. As NBn+ decreases, the reverse recovery current becomes smoother. Both di/dtmax and ΔVDS decreases. Oscillation is also gradually suppressed. This is because the net recombination rate in the semiconductor is proportional to the carrier density. If NBn+ decreases, the net recombination rate also decreases. Then, more holes accumulate in the n + -buffer layer when the body diode is forward biased. During the reverse recovery process, they make the reverse recovery current smoother. Figure 7b shows reverse recovery waveforms of devices with NBn+ = 4 × 10 16 cm −3 and TBn+ ranges from 0 μm to 40 μm. TBn+ = 0 μm represents the conventional SJ-MOSFET. As TBn+ increases, the reverse recovery current becomes smoother. Both di/dtmax and ΔVDS decreases. Oscillation is also gradually   Figure 8 summarizes the influence of N Bn+ and T Bn+ on ∆V DS and ∆R ON . T Bn+ increases from 5 µm to 40 µm. For each T Bn+ , N Bn+ ranges from 1 × 10 15 cm −3 to 1 × 10 19 cm −3 . If N Bn+ = 1 × 10 19 cm −3 , the n + -buffer layer merges with the n + -substrate. Then, all samples are the same with the conventional SJ-MOSFET. If N Bn+ = 1 × 10 15 cm −3 , the n + -buffer layer merges with the n − -buffer layer. Increasing T Bn+ is equivalent to increasing the thickness of the n − -buffer layer. This is the usual method used in conventional SJ-MOSFETs. Without a doubt, ∆R ON increases rapidly. For the proposed SJ-MOSFET with the same T Bn+ , ∆V DS increases, and ∆R ON decreases with N Bn+ . When N Bn+ is below 2 × 10 16 cm −3 , ∆V DS is ignorable but ∆R ON is remarkable. The overshoot voltage is almost eliminated. When N Bn+ is above 1 × 10 17 cm −3 , ∆R ON is ignorable but ∆V DS is remarkable. For the same N Bn+ , ∆V DS decreases, and ∆R ON increases with T Bn+ . Figure 8 also shows that N Bn+ plays a more effective role in reducing ∆V DS than T Bn+ , especially when T Bn+ exceeds 10 µm. It means that a thick n + -buffer layer is not necessary. For T Bn+ = 10 µm, the optimal range of N Bn+ is 4 × 10 15 cm −3 to 6 × 10 16 cm −3 . In this range, ∆R ON is within 5% and ∆V DS is within 20 V. Even T Bn+ increases to 40 µm, ∆R ON is within 20% and ∆V DS is within 4 V. the reverse recovery current smoother. The improvement becomes insignificant once TBn+ exceeds 20 μm. The reason is that holes deep into the n + buffer layer recombine with electrons during the reverse recovery process. Their contribution to the reverse recovery current is negligible.  For each TBn+, NBn+ ranges from 1 × 10 15 cm −3 to 1 × 10 19 cm −3 . If NBn+ = 1 × 10 19 cm −3 , the n + -buffer layer merges with the n + -substrate. Then, all samples are the same with the conventional SJ-MOSFET. If NBn+ = 1 × 10 15 cm −3 , the n + -buffer layer merges with the n − -buffer layer. Increasing TBn+ is equivalent to increasing the thickness of the n −buffer layer. This is the usual method used in conventional SJ-MOSFETs. Without a doubt, ΔRON increases rapidly. For the proposed SJ-MOSFET with the same TBn+, ΔVDS increases, and ΔRON decreases with NBn+. When NBn+ is below 2 × 10 16 cm −3 , ΔVDS is ignorable but ΔRON is remarkable. The overshoot voltage is almost eliminated. When NBn+ is above 1 × 10 17 cm −3 , ΔRON is ignorable but ΔVDS is remarkable. For the same NBn+, ΔVDS decreases, and ΔRON increases with TBn+. Figure 8 also shows that NBn+ plays a more effective role in reducing ΔVDS than TBn+, especially when TBn+ exceeds 10 μm. It means that a thick n + -buffer layer is not necessary. For TBn+ = 10 μm, the optimal range of NBn+ is 4 × 10 15 cm −3 to 6 × 10 16 cm −3 . In this range, ΔRON is within 5% and ΔVDS is within 20 V. Even TBn+ increases to 40 μm, ΔRON is within 20% and ΔVDS is within 4 V.

Conclusions
This study demonstrates that a soft reverse recovery body diode can be integrated into the SJ-MOSFET by adding an n + -buffer layer between the n − -buffer layer and the n +substrate. During the reverse recovery process, the drain-to-source overshoot voltage ΔVDS can be greatly reduced and oscillation can be eliminated. Compared with the conventional device that uses a thick n − -buffer layer, the proposal solution does not compromise the on-resistance too much. According to the simulated results, the increment of RON and the overshoot voltage can be, respectively, kept below 5% and 20 V, if a 10 μm n +buffer layer whose impurity concentration ranges from 4 × 10 15 cm −3 to 6 × 10 16 cm −3 is used. Moreover, the fabrication process is the same as that of the conventional SJ-MOSFET.

Conclusions
This study demonstrates that a soft reverse recovery body diode can be integrated into the SJ-MOSFET by adding an n + -buffer layer between the n − -buffer layer and the n +substrate. During the reverse recovery process, the drain-to-source overshoot voltage ∆V DS can be greatly reduced and oscillation can be eliminated. Compared with the conventional device that uses a thick n − -buffer layer, the proposal solution does not compromise the