Search Results (59)

Magnetic nanowires with domain walls (DWs) play a crucial role in the advancement of next-generation memory and spintronic devices. Understanding the thermal effects on domain wall behavior is essential for optimizing performance and stability. This study investigates the thermal chirality-dependent dynamics and pinning of transverse domain walls (TDWs) in Z-junction nanowires using micromagnetic simulations. The analysis focuses on head-to-head (HHW) and tail-to-tail (TTW) domain walls with up and down chirality under varying thermal conditions. The results indicate that higher temperatures reduce the pinning strength and depinning current density, leading to enhanced domain wall velocity. At 200 K, the HHW_down domain wall depins at a critical current density of 1.2 × 10¹¹ A/m², while HHW_up requires a higher depinning temperature, indicating stronger pinning effects. Similarly, the depinning temperature (T_d) increases with Z-junction depth (d), reaching 300 K at d = 50 nm, while increasing Z-junction (λ) weakens pinning, reducing T_d to 150 K at λ = 50 nm. Additionally, the influence of Z-junction geometry and magnetic properties, such as saturation magnetization (M_s) and anisotropy constant (K_u), is examined to determine their effects on thermal pinning and depinning. These findings highlight the critical role of chirality and thermal activation in domain wall motion, offering insights into the design of energy-efficient, high-speed nanowire-based memory devices. Full article

With the rise of the Internet of Things (IoT), smart sensors are increasingly being deployed as compact edge processing units, necessitating continuously writable memory with low power consumption and fast access times. Magnetic random-access memory (MRAM) has emerged as a promising non-volatile alternative to conventional DRAM and SDRAM, offering advantages such as faster access speeds, reduced power consumption, and enhanced endurance. However, MRAM is subject to challenges including process variations and thermal fluctuations, which can induce random bit errors and result in imbalanced probabilities of 0 and 1 bits. To address these issues, we propose a novel sparse coding scheme characterized by a minimum Hamming distance of three. During the encoding process, three check bits are appended to the user data and processed using a generator matrix. If the resulting codeword fails to satisfy the sparsity constraint, it is inverted to comply with the coding requirement. This method is based on the error characteristics inherent in MRAM to facilitate effective error correction. Furthermore, we introduce a dynamic threshold detection technique that updates bit probability estimates in real time during data transmission. Simulation results demonstrate substantial improvements in both error resilience and decoding accuracy, particularly as MRAM density increases. Full article

This paper presents a novel transposed MRAM architecture (WinEdge) specifically optimized for Winograd convolution acceleration in edge computing devices. Leveraging Magnetic Tunnel Junctions (MTJs) with Spin Hall Effect (SHE)-assisted Spin-Transfer Torque (STT) writing, the proposed design enables a single SHE current to simultaneously write data to four MTJs, substantially reducing power consumption. Additionally, the integration of stacked MTJs significantly improves storage density. The proposed WinEdge efficiently supports both standard and transposed data access modes regardless of bit-width, achieving up to 36% lower power, 47% reduced energy consumption, and 28% faster processing speed compared to existing designs. Simulations conducted in 45 nm CMOS technology validate its superiority over conventional SRAM-based solutions for convolutional neural network (CNN) acceleration in resource-constrained edge environments. Full article

This study investigates the thermal pinning and depinning behaviors of vortex domain walls (VWs) in constricted magnetic nanowires, focusing on the influence of intrinsic magnetic properties on VW stability under thermal stress. Using micromagnetic simulations, we analyze the roles of saturation magnetization (Ms), uniaxial magnetic anisotropy (Ku), and nanowire geometry in determining VW thermal stability. The modeled nanowire has dimensions of 200 nm (width), 30 nm (thickness), and a 50 nm constriction length, chosen based on the dependence of VW formation on nanowire geometry. Our results show that increasing Ms and K_u enhances VW pinning, while thermal fluctuations at higher temperatures promote VW depinning. We demonstrate that temperature and magnetic parameters significantly impact VW structural stability, offering insights for designing high-reliability nanowire-based memory devices. These findings contribute to optimizing nanowire designs for thermally stable, energy-efficient spintronic memory systems. Full article

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures. Full article

Current-induced field-free magnetic switching using spin–orbit torque has been an important topic for decades due to both academic and industrial interest. Most research has focused on introducing symmetry breakers, such as geometrical and compositional variation, pinned layers, and symmetry-broken crystal structures, which add complexity to the magnetic structure and fabrication process. We designed a relatively simple magnetic structure, composed of a [Co/Pt] multilayer and a Co layer with perpendicular and in-plane magnetic anisotropy, respectively, with a Cu layer between them. Current-induced deterministic magnetic switching was observed in this magnetic system. The system is advantageous due to its easy control of the parameters to achieve the optimal condition for magnetic switching. The balance between magnetic anisotropic strength and interlayer coupling strength is found to provide the optimal condition. This simple design and easy adjustability open various possibilities for magnetic structures in spin-based electronics applications using spin–orbit torque. Full article

In this study, we investigate the thermal pinning and depinning behaviors of vortex domain walls (VDWs) in constricted magnetic nanowires, with a focus on potential applications in storage memory nanodevices. Using micromagnetic simulations and spin transfer torque, we examine the impacts of device temperature on VDW transformation into a transverse domain wall (TDW), mobility, and thermal strength pinning at the constricted area. We explore how thermal fluctuations influence the stability and mobility of domain walls within stepped nanowires. The thermal structural stability of VDWs and their pinning were investigated considering the effects of the stepped area depth (d) and its length (λ). Our findings indicate that the thermal stability of VDWs in magnetic stepped nanowires increases with decreasing the depth of the stepped area (d) and increasing nanowire thickness (th). For th ≥ 50 nm, the stability is maintained at temperatures ≥ 1200 K. In the stepped area, VDW thermal pinning strength increases with increasing d and decreasing λ. For values of d ≥ 100 nm, VDWs depin from the stepped area at temperatures ≥ 1000 K. Our results reveal that thermal effects significantly influence the pinning strength at constricted sites, impacting the overall performance and reliability of magnetic memory devices. These insights are crucial for optimizing the design and functionality of next-generation nanodevices. The stepped design offers numerous advantages, including simple fabrication using a single electron beam lithography exposure step on the resist. Additionally, adjusting λ and d allows for precise control over the pinning strength by modifying the dimensions of the stepped areas. Full article

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area. Full article

In the future, DW memory will replace conventional storage memories with high storage capacity and fast read/write speeds. The only failure in DW memory arises from DW thermal fluctuations at pinning sites. This work examines, through calculations, the parameters that might help control DW thermal stability at the pinning sites. It is proposed to design a new scheme using a stepped area of a certain depth (d) and length (λ). The study reveals that DW thermal stability is highly dependent on the geometry of the pinning area (d and λ), magnetic properties such as saturation magnetization (Ms) and magnetic anisotropy energy (Ku), and the dimensions of the nanowires. For certain values of d and λ, DWs remain stable at temperatures over 500 K, which is beneficial for memory applications. Higher DW thermal stability is also achieved by decreasing nanowire thickness to less than 10 nm, making DW memories stable below 800 K. Finally, our results help to construct DW memory nanodevices with nanodimensions less than a 40 nm width and less than a 10 nm thickness with high DW thermal stability. Full article

Spintronics, utilizing both the charge and spin of electrons, benefits from the nonvolatility, low switching energy, and collective behavior of magnetization. These properties allow the development of magnetoresistive random access memories, with magnetic tunnel junctions (MTJs) playing a central role. Various spin logic concepts are also extensively explored. Among these, spin logic devices based on the motion of magnetic domain walls (DWs) enable the implementation of compact and energy-efficient logic circuits. In these devices, DW motion within a magnetic track enables spin information processing, while MTJs at the input and output serve as electrical writing and reading elements. DW logic holds promise for simplifying logic circuit complexity by performing multiple functions within a single device. Nevertheless, the demonstration of DW logic circuits with electrical writing and reading at the nanoscale is still needed to unveil their practical application potential. In this review, we discuss material advancements for high-speed DW motion, progress in DW logic devices, groundbreaking demonstrations of current-driven DW logic, and its potential for practical applications. Additionally, we discuss alternative approaches for current-free information propagation, along with challenges and prospects for the development of DW logic. Full article

Current-induced domain wall motion (CIDWM) in magnetic wires can be driven by spin transfer torque (STT) originating from transferring angular momentums of spin-polarized conducting electrons to the magnetic DW and can be driven by spin orbit torque (SOT) originating from the spin Hall effect (SHE) in a heavy metal layer and Dzyaloshinsky Moriya (DMI) generated at an interface between a heavy metal layer and a magnetic layer. In this work, we carried out a comparative study of CIDWM driven by STT and by SOT in ferrimagnetic GdFeCo wires with magnetic perpendicular anisotropy based on structures of SiN (10 nm)/GdFeCo (8 nm)/SiN (10 nm) and Pt (5 nm)/GdFeCo (8 nm)/SiN (10 nm). We found that CIDWM driven by SOT exhibited a much lower critical current density (J_C), and much higher DW mobility (µ_DW). Our work might be useful for the realization and the development of low-power and high-speed memory devices. Full article

In advancing the study of magnetization dynamics in STT-MRAM devices, we employ the spin drift–diffusion model to address the back-hopping effect. This issue manifests as unwanted switching either in the composite free layer or in the reference layer in synthetic antiferromagnets—a challenge that becomes more pronounced with device miniaturization. Although this miniaturization aims to enhance memory density, it inadvertently compromises data integrity. Parallel to this examination, our investigation of the interface exchange coupling within multilayer structures unveils critical insights into the efficacy and dependability of spintronic devices. We particularly scrutinize how exchange coupling, mediated by non-magnetic layers, influences the magnetic interplay between adjacent ferromagnetic layers, thereby affecting their magnetic stability and domain wall movements. This investigation is crucial for understanding the switching behavior in multi-layered structures. Our integrated methodology, which uses both charge and spin currents, demonstrates a comprehensive understanding of MRAM dynamics. It emphasizes the strategic optimization of exchange coupling to improve the performance of multi-layered spintronic devices. Such enhancements are anticipated to encourage improvements in data retention and the write/read speeds of memory devices. This research, thus, marks a significant leap forward in the refinement of high-capacity, high-performance memory technologies. Full article

This study focuses on the tire–road friction estimation for the predictive control strategy of electronically limited slip differential (ELSD) to improve the handling and acceleration performance of front-wheel drive cars, which typically suffer from excessive understeer and inner drive wheel spin during acceleration while turning due to reduced vertical load on the wheel. To mitigate this, we propose a control logic for ELSD that enhances course followability and acceleration by pre-transferring the driving torque from the inside to the outside wheel, considering the estimated traction potential for rapid response. It is essential to improve the control accuracy of wheel spin prediction by predicting the friction coefficient of the road surface. Furthermore, this study extends to the analysis of vehicle dynamics during lane-change maneuvers on low-friction surfaces, emphasizing the role of accurate tire–road friction estimation in vehicle safety. A CarSim 2023-based simulation study was conducted to investigate the vehicle response on snowy roads with low friction coefficients (μ = 0.2) and low temperatures (−5 °C). The results demonstrated that even minimal steering input could result in significant side-slip angles, highlighting the nonlinear vehicle behavior and the critical need for robust traction estimation in such challenging conditions of general racing tracks. The proposed friction-estimation method was evaluated through vehicle testing and has been substantiated by patents for its originality in control and friction-estimation approaches. The outcomes of these combined methodologies underline the critical importance of tire–road friction coefficient estimation in both the effectiveness of the ELSD system and the broader context of active safety systems. Full article

Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows promising properties, such as non-volatility, speed, and unlimited endurance. One of the important merits of STT-MRAM is its radiation hardness, thanks to its core component, a magnetic tunnel junction (MTJ), being capable of good function in an irradiated environment. This property makes MRAM attractive for space and nuclear technology applications. In this paper, a novel radiation-hardened triple modular redundancy (TMR) design for anti-radiation reinforcement is proposed based on the utilization of STT-MTJ devices. Simulation results demonstrate the radiation-hardened performance of the design. This shows improvements in the design’s robustness against ionizing radiation. Full article

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively. Full article