Search Results (34)

This article presents an interaction-aware motion planning framework that integrates a graph neural network (GNN) based multi-modal trajectory predictor with a model predictive control (MPC) based planner. Unlike past studies that predict a single future trajectory per agent, our algorithm outputs three distinct trajectories for each surrounding road user, capturing different interaction scenarios (e.g., yielding, non-yielding, and aggressive driving behaviors). We design a GNN-based predictor with bi-directional gated recurrent unit (Bi-GRU) encoders for agent histories, VectorNet-based lane encoding for map context, an interaction-aware attention mechanism, and multi-head decoders to predict trajectories for each mode. The MPC-based planner employs a bicycle model and solves a constrained optimal control problem using CasADi and IPOPT (Interior Point OPTimizer). All three predicted trajectories per agent are fed to the planner; the primary prediction is thus enforced as a hard safety constraint, while the alternative trajectories are treated as soft constraints via penalty slack variables. The designed motion planning algorithm is examined in real-world intersection scenarios from the INTERACTION dataset. Results show that the multi-modal trajectory predictor covers possible interaction outcomes, and the planner produces smoother and safer trajectories compared to a single-trajectory baseline. In high-conflict situations, the multi-modal trajectory predictor anticipates potential aggressive behaviors of other drivers, reducing harsh braking and maintaining safe distances. The innovative method by integrating the GNN-based multi-modal trajectory predictor with the MPC-based planner is the backbone of the effective motion planning algorithm for robust, safe, and comfortable autonomous driving in complex intersections. Full article

A new control system implemented with a single-stage DC-DC controller to power an LED headlamp for automotive applications is presented in this work. Daytime running light (DRL), low beam (LB), high beam (HB) and adaptive driving beam (ADB) are typical functions requiring a dedicated LED driver solution to fulfill car maker requirements for front-light applications. Single-stage drivers often exhibit a significant overshoot in LED current during transitions from driving a higher number of LEDs to a lower number. To maintain LED reliability, this current overshoot must remain below the maximum current rating of the LEDs. If the overshoot overcomes this limit, it can cause permanent damage to the LEDs or reduce their lifespan. To preserve LED reliability, a comprehensive system has been proposed to minimize the peak of LED current overshoots, especially during transitions between different operating modes or LED string configurations. A key feature of the proposed system is the implementation of a parallel discharging path to be activated only when the current flowing in the LEDs is higher than a predefined threshold. A prototype incorporating an integrated test chip has been developed to validate this approach. Measurement results and comparison with state-of-the-art solutions available in the market are shown. Furthermore, a critical aspect to be considered is the proper dimensioning of the discharging path. It requires careful considerations about the gate driver capabilities, the discharging resistor values, and the thermal management of the dumping element. For this purpose, an extensive study on how to size the relative components is also presented. Full article

This study provides a comprehensive characterization of various isolated single and half-bridge gate drivers over the entire temperature range from room temperature down to −194 °C. Unlike previous studies, which primarily focused on electrical output parameters such as rise/fall times and propagation delays, this paper also explores critical functionalities like undervoltage lockout (UVLO) and common-mode transient immunity (CMTI). The first comprehensive characterization of the power-up and power-down behavior of gate drivers identified critical operating states for practical use. In addition, CMTI testing revealed the premature functional failures of some drivers at low temperatures. Full article

In medium- and high-power-density applications, silicon carbide (SiC) metal-oxide semiconductor field effect transistors (MOSFETs) are often connected in parallel increasing the current capability. However, the current sharing of paralleled SiC MOSFETs is affected by the mismatched technical parameters of devices and the deviated power circuit parasitic inductances, even if power devices are controlled by a single gate driver. This leads to unevenly distributed power losses causing different stress between SiC MOSFETs. As a result, unbalanced current sharing increases the probability of severe power switch(es) and system failures. For over a decade, the current imbalance issue between parallel-connected SiC MOSFETs has concerned the scientific community, and many methods and techniques have been proposed. However, most of these solutions are impossible to realize without the necessity of screening power devices to measure their technical parameters. Consequently, system costs significantly increase due to the expensive equipment for screening SiC MOSFETs. Also, transient current imbalance is the main concern of most papers, without addressing static imbalance. In this paper, an innovative approach is proposed, capable of suppressing both static and transient current imbalance between paralleled SiC MOSFETs, under both symmetrical and asymmetrical layouts, through an improved active gate driver and without the requirement for any power device screening process. Additionally, the proposed solution employs a self-sustaining algorithmic approach utilizing current sensors and a field-programmable gate array (FPGA). The functionality of the proposed solution is verified through experimental tests, achieving current imbalance suppression between two paralleled SiC MOSFETs, actively and autonomously. Full article

This work explores the principle of utilizing gallium nitride devices as a gate driver for silicon carbide power devices. As silicon has long reached its performance limits, Wide Bandgap semiconductors such as gallium nitride and silicon carbide have emerged as promising alternatives due to their superior characteristics. However, few publications suggest using a gallium nitride-based gate driver for silicon carbide, high-voltage power devices. Unlike standard voltage source gate drivers, this paper proposes a novel bi-polar current source resonant gate driver topology using gallium nitride transistors as a gate drive circuit for silicon carbide power switching. The driver receives a single input supply and pulsed width modulation signal, producing a high current bi-polar gate driving signal. The gate driver is validated by employing the proposed gate driver to a high-power silicon carbide transistor in a resonant boost converter. The experimental results show that the new gate driver recovers the gate charge wasted energy and provides high performances in varying high voltage loads at a 2.5 MHz switching frequency while reducing the gate losses by 26%. Full article

A single-phase multilevel inverter with a switched-capacitor multilevel (SC-MLI) configuration is developed to provide 13-level output voltages. An improved genetic algorithm (GA) with adaptive mutation and crossover rates is employed to achieve robust harmonic mitigation by avoiding local optima and ensuring optimal performance. The topology introduces an SC-MLI that generates AC output voltage at desired levels using only two capacitors, two asymmetrical DC sources, one diode, and 11 switches. This allows the inverter to use fewer gate drivers and, hence, increases the power density of the converter. A significant challenge in the normal operation of SC-MLI circuits relates to the self-voltage balance of the capacitors, which easily becomes unstable, particularly at low modulation indices. The proposed design addresses this issue without the need for ancillary devices or complex control schemes, ensuring stable self-balanced operation across the entire spectrum of the modulation index. In this context, the harmonic mitigation technique optimized through GA applied in this inverter ensures low harmonic distortion, achieving a total harmonic distortion (THD) of 6.73%, thereby enhancing power quality even at low modulation indices. The performance of this SC-MLI is modeled under various loading scenarios using MATLAB/Simulink^® 2023b with validation performed through an Opal-RT real-time emulator. Additionally, the inverter’s overall power losses and individual switch losses, along with the efficiency, are analyzed using the simulation tool PLEXIM-PLECS. Efficiency is found to be 96.62%. Full article

The pulse laser emission circuit plays a crucial role as the emission unit of time-of-flight (TOF) LiDAR. This paper proposes a nanosecond-level pulse laser diode array drive circuit for LiDAR, primarily aimed at addressing the issue of high-speed scanning drive for the laser diode array at the emission end of solid-state LiDAR. Based on the single pulse laser diode drive circuit, this paper innovatively designs a circuit that includes modules such as a boost circuit, linear power supply, high-speed gate driver, GaN field-effect transistor, and pulse narrowing circuit, realizing an 8-channel laser diode array drive circuit. This circuit can achieve a pulse laser array drive with a single channel operating frequency of greater than 100 kHz, an output pulse width of less than 5 ns, a peak power greater than 75 W, and a channel switching time that does not exceed 1 μs. A field programmable gate array (FPGA) is used to control the operation of this circuit and perform a series of performance tests. Experimental results show that this circuit has a high repetition rate, large output power, a narrow pulse width, and fast switching speeds, making it highly suitable for use in the optical emission module of solid-state LiDAR. Full article

According to the International Electrotechnical Commission, medium voltage ranges from 1 kV to 36 kV. In this voltage range, the field of power electronics has been focusing on developing power converters with high efficiency. Converters for such applications include solid-state transformers, energy storage systems for vehicle charging, electric aircraft, etc. Power ranges could reach tens to hundreds of kilowatts at relatively high frequency (10–50 kHz). Currently, there are no high-frequency power semiconductors capable of switching these voltage levels. Instead of using a single power switch, a string of power switches is used. The upper switches in the string require special attention because they need the highest isolation capabilities and a floating control signal and power supply for the gate driver. Many techniques have been proposed to accomplish this, but they commonly use separate circuits for the control signal and the power supply, increasing the cost, size, and complexity of the gate driver. This paper presents a gate driver for medium voltage with high-voltage isolation capabilities in a single structure for the control signal and the power supply. The proposed gate driver uses a resonant converter that transmits power within the gate driver information. A demodulator separates the gate driver information from the power signal, obtaining the power supply and the control signal for the switch. The paper includes simulation and experimental results that demonstrate the viability of the proposal. The experimental results show the principal features of the gate driver, achieving improvements in complexity, isolation capabilities, and both rise and fall times for large input capacitances of power semiconductor switches. The proposed gate driver presents a rise time of 44 ns and a fall time of 46 ns for the gate input capacitance of currently available SiC MOSFETs. The isolation barrier uses a 25 mm air gap, achieving an isolation capability of approximately 68.2 kV, which exceeds the requirements for MV applications. Full article

This research paper introduces a new topology for multilevel inverters, emphasizing the reduction of harmonic distortion and the optimization of the component count. The complexity of an inverter is determined by the number of power switches, which is significantly reduced in the presented topology, as fewer switches require fewer driver circuits. In this proposed topology, a new single-phase generalized multilevel inverter is analyzed with an equal magnitude of voltage supply. A 9-level, 11-level, or 13-level symmetrical inverter with RL load is analyzed in MATLAB/Simulink 2019b and then experimentally validated using the dSPACE-1103 controller. The experimental verification of the load voltage and current with different modulation indices is also presented. The analysis of the proposed topology concludes that the total required number of components is lower than that necessary for the classical inverter topologies, as well as for some new proposed multilevel inverters that are also compared with the proposed topology in terms of gate driver circuits, power switches, and DC sources, which thereby enhances the goodness of the proposed topology. Thus, a comparison of this inverter with the other topologies validates its acceptance. Full article

Taxis and Transportation Network Companies (TNCs) are important components of the urban transportation system. An accurate short-term forecast of passenger demand can help operators better allocate taxi or TNC services to achieve supply–demand balance in real time. As a result, drivers can improve the efficiency of passenger pick-ups, thereby reducing traffic congestion and contributing to the overall sustainability of the program. Previous research has proposed sophisticated machine learning and neural-network-based models to predict the short-term demand for taxi or TNC services. However, few of them jointly consider both modes, even though the short-term demand for taxis and TNCs is closely related. By enabling information sharing between the two modes, it is possible to reduce the prediction errors for both. To improve the prediction accuracy for both modes, this study proposes a multi-task learning (MTL) model that jointly predicts the short-term demand for taxis and TNCs. The model adopts a gating mechanism that selectively shares information between the two modes to avoid negative transfer. Additionally, the model captures the second-order spatial dependency of demand by applying a graph convolutional network. To test the effectiveness of the technique, this study uses taxi and TNC demand data from Manhattan, New York, as a case study. The prediction accuracy of single-task learning and multi-task learning models are compared, and the results show that the multi-task learning approach outperforms single-task learning and benchmark models. Full article

Two types of asymmetric switched-capacitor five-level single-phase DC-AC inverters are presented based on the clamping half-bridge circuit and the output half-bridge circuit. Furthermore, the switches of the two proposed circuits can be driven by half-bridge gate drivers and can be modularized. Moreover, the detailed analysis of the operation principle, design of clamping capacitor and output filter of these two inverters are presented. Finally, the feasibility and validity of the proposed structures are verified by PSIM-simulated results and experimental results using FPGA as the control kernel, respectively. Full article

Flat panel displays are electronic displays that are thin and lightweight, making them ideal for use in a wide range of applications, from televisions and computer monitors to mobile devices and digital signage. The Thin-Film Transistor (TFT) layer is responsible for controlling the amount of light that passes through each pixel and is located behind the liquid crystal layer, enabling precise image control and high-quality display. As one of the important parameters to evaluate the display performance, the faster response time provides more frames in a second, which benefits many high-end applications, such as applications for playing games and watching movies. To further improve the response time, the single-pixel charging efficiency is investigated in this paper by optimizing the TFT dimensions in gate driver circuits in active-matrix liquid crystal displays. The accurate circuit simulation model is developed to minimize the signal’s fall time ($T_f$) by optimizing the TFT width-to-length ratio. Our results show that using a driving TFT width of 6790 $\mathsf{\mu }\mathrm{m}$ and a reset TFT width of 640 $\mathsf{\mu }\mathrm{m}$ resulted in a minimum $T_f$ of 2.6572 $\mathsf{\mu }\mathrm{s}$, corresponding to a maximum pixel charging ratio of 90.61275%. These findings demonstrate the effectiveness of our optimization strategy in enhancing pixel charging efficiency and improving display performance. Full article

The detection and evaluation of fatigue levels in drivers play a crucial role in reducing traffic accidents and improving the overall quality of life. However, existing studies in this domain often focus on fatigue detection alone, with limited research on fatigue level evaluation. These limitations include the use of single evaluation methods and relatively low accuracy rates. To address these issues, this paper introduces an innovative approach for determining fatigue driving levels. We employ the Dlib library and fatigue state detection algorithms to develop a novel method specifically designed to assess fatigue levels. Unlike conventional approaches, our method adopts a multi-feature fusion strategy, integrating fatigue features from the eyes, mouth, and head pose. By combining these features, we achieve a more precise evaluation of the driver’s fatigue state level. Additionally, we propose a comprehensive evaluation method based on the analytic hierarchy process (AHP) and fuzzy comprehensive evaluation, combined with situational prediction. This approach effectively evaluates the fatigue state level of drivers at specific moments or stages and provides accurate predictions. Furthermore, we optimize the gated recurrent unit (GRU) network using an enhanced marine predator algorithm (MAP), which results in significant improvements in predicting fatigue levels during situational prediction. Experimental results demonstrate a classification accuracy of 92% across various scenarios while maintaining real-time performance. In summary, this paper introduces a novel approach for determining fatigue driving levels through multi-feature fusion. We also incorporate AHP-fuzzy comprehensive evaluation and situational prediction techniques, enhancing the accuracy and reliability of fatigue level evaluation. This research holds both theoretical and practical significance in the field of fatigue driving. Full article

For low-power applications, this paper presents the development and design of a compact and ultra-highly efficient half-bridge LLC resonant converter. By using Galium Nitride (GaN) devices and high-efficient magnetics, the efficiency and power density of resonant converters can be improved. Compared to Silicon MOSFETs, GaN high-electron-mobility transistors (GaN HEMT) have a lower output capacitance and gate charge, resulting in lower driving loss and shorter dead times. Consequently, the proposed LLC converter based on GaN devices has excellent performance characteristics such as ultra-high efficiency, low switching losses, compact size, high voltage endurance, high operating temperature and high operating frequency. Furthermore, the proposed resonant converter features soft switching properties that ensure that the switches and diodes on the primary side are always switched at zero voltage and current. By doing so, LLC resonant converter switching losses are significantly reduced by up to 3.1%, and an overall efficiency of 98.5% is achieved. The LLC resonant converter design with GaN HEMT has great advantages over Si MOSFET solution regarding efficiency, overall losses, switching loose and power factor correction. A 240 W, 240 V to 60 V half-bridge GaN HEMT LLC resonant converter is simulated with a switching frequency of 75 KHz, along with the comparative analysis of the Si metal oxide semiconductor field effect transistor (MOSFET) solution. Moreover, the design and analysis of highly efficient magnetics with a power factor of 0.99 at full load is presented. A 240-Watt single stage LED driver with power factor correction is also designed to verify and compare the performance of proposed LLC resonant converter. Full article

In floating gate compute-in-memory (CIM) chips, due to the gate equivalent capacitance of the large-scale array and the parasitic capacitance of the long-distance transmission wire, it is difficult to balance the switching speed and area of the word line driver circuit (WLDC). The difference among multiple voltage domains required for floating gate CIM devices has also far exceeded the withstand voltage range of a single transistor in the WLDC. This paper proposes a novel WLDC based on the working principle of the CIM array. A multi-level pre-processing voltage control method is adopted to carry out an optional hierarchical transmission of multiple high voltages, significantly reducing the propagation delay. The proposed WLDC is based on the Wilson current mirror structure, which substantially reduces the physical design area. The simulation results show that the circuit can convert a 1.2 V low-voltage domain input signal with a frequency of 10 MHz into a high-voltage domain output voltage, and the output voltage range of a single WLDC can reach −10 V to 10 V. With a capacitive load within 5 pF, the transmission delay is less than 10 ns. The layout area is 594.88 µm², which is suitable for a large-scale CIM array. Full article