Two Types of Asymmetric Switched-Capacitor Five-Level Single-Phase DC-AC Inverters for Renewable Energy Applications

Abstract

Two types of asymmetric switched-capacitor five-level single-phase DC-AC inverters are presented based on the clamping half-bridge circuit and the output half-bridge circuit. Furthermore, the switches of the two proposed circuits can be driven by half-bridge gate drivers and can be modularized. Moreover, the detailed analysis of the operation principle, design of clamping capacitor and output filter of these two inverters are presented. Finally, the feasibility and validity of the proposed structures are verified by PSIM-simulated results and experimental results using FPGA as the control kernel, respectively.

1. Introduction

1.1. Motivations

Renewable energy sources, including solar [1,2], wind [3,4], hydro [5,6], geothermal [7,8], tidal [9,10], biomass [11,12], and hydrogen [13,14], are considered to be environmentally friendly because they are continuous, sustainable, and do not emit harmful emissions. In recent years, global awareness of environmental protection has increased, and more and more renewable energy sources have been encouraged to be integrated into the power grid for power generation or energy storage systems [15,16,17,18,19].

Renewable energy can facilitate decentralization of energy and electricity and enhance the security and reliability of energy supply [2,3,17,18,19]. However, the development of renewable energy still faces a number of challenges, such as energy storage and transmission technologies, energy policies and market uncertainties, and so on [20]. Consequently, in the process of facilitating the development of renewable energy, it is necessary to strengthen technological research and market development, and actively formulate and implement policies and regulations favorable to the development of renewable energy. However, harmonics content in voltage and/or current wave will cause distortions and make it non-sinusoidal. Hence, it is needed to reduce harmonics so as to improve the total harmonic distortion (THD) and efficiency of the system.

The American Institute of Electrical and Electronics Engineers (IEEE) develops the IEEE 1547 standard [21], which is an interconnection standard for distributed energy resources, including solar photovoltaic systems, wind turbines, fuel cells, etc. The standard contains many aspects, including many requirements such as AC power control, frequency and voltage control, protection and safety, fault and failure mode management, etc. The IEEE 519 standard [22] is proposed to protect the equipment in the power system from the adverse effects of harmonics, and to protect the harmonic content in the system from exceeding the safe and acceptable limits. In addition, recommendations are provided on the limitation and control of harmonic voltages and currents in power systems. In Europe, the International Electrotechnical Commission (IEC) has issued the IEC 60038 standard [23], which defines the range of voltages and frequencies to be supplied to power systems used at fixed frequencies to ensure compatibility between different electrical equipment and stability and reliability under different environmental conditions. At the same time, a series of IEC 61000 standards has been promulgated under the title of Electromagnetic Compatibility (EMC), belonging to the IEC 61000-3-X part, which covers output and input noise limitations for electrical and electronic equipment in power systems, including limitations on harmonics and abnormal voltages, etc. The IEC 61000-3-2 [24] aims to limit the effect of electrical equipment (e.g., household appliances, industrial equipment, etc.) on the harmonic currents in public low-voltage power systems, whereas the IEC 61000-3-3 [25] aims to determine the limits of the input noises of electronic equipment in low-voltage power systems in order to ensure the compatibility of the various types of electronic equipment and to minimize disturbances and damage in the power grid. In addition, the IEC 62109-1 standard [26] has been developed for the specifications of safety performance requirements for inverters in solar power systems.

Currently, the electricity provided by renewable energy can be divided into alternating current (AC) voltage from hydroelectric power and wind power through rotating motors, and direct current (DC) voltage from solar power and fuel cells through semiconductor physical and chemical energy conversion. In order to cope with the AC utility power system, AC-DC rectifiers are combined with DC-AC inverters or DC-AC inverters are used to further convert green energy into AC power. Therefore, the DC-AC inverter is one of the most important components used for power transmission.

Nowadays, DC-AC inverters are developing towards high efficiency and low harmonic components. Therefore, the development trend of multilevel inverters is towards achieving a large number of levels with a small number of power components, reducing component losses and developing multilevel inverters (MLIs). The principle of MLIs is to utilize several capacitors and power switches to change the conduction path, so as to clamp and create voltages of several levels to make the output voltage be presented on several levels.

Typical multilevel inverters include the neutral point clamped (NPC) inverter, the flying capacitor (FC) inverter, and the cascaded H-bridge (CHB) inverter [27]. In terms of the circuit structure, it can be further categorized into symmetric MLIs and asymmetric MLIs [28]. Although symmetric MLIs have the advantages of simple control and modular replacement over asymmetric MLIs, they use more power-switching components than asymmetric MLIs, thereby leading to higher costs and larger size and weight. On the other hand, the more levels there are, the more the output voltage can be reduced without the need for external inductors or filters to decrease the harmonic components of the output waveform, and the output voltage can be close to the sinusoidal waveform. In addition, the voltages across some power switches can be clamped by the level voltages to reduce the switch voltage stresses and improve the overall conversion efficiency [27,28]. Based on the foregoing reasons, the five-level DC-AC inverter is rather popular in practice applications.

1.2. Statement of the Related Works

Figure 1 shows typical five-level asymmetric inverters, including the diode neutral-point-clamped inverter [29], the T-type neutral-point-clamped inverter [30], and the flywheel capacitor inverter [31]. The main half-bridge circuit is operated based on the positive and negative half-cycles of the output voltage, and the multilevel inverter achieves the unipolar PWM-switching strategy by using control force alignment compensation. Since the switched-capacitor circuit consists of one or more capacitors and one or more power switches and is often used to maintain the voltages across the capacitors at several times the input DC voltage, the output voltage of the circuit is controlled by switching the capacitors to charge and discharge through the active components to achieve the output voltage at a relatively high number of voltage levels [32,33].

There are many other existing papers presented on the asymmetric five-level single-phase DC-AC inverters [2,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50] with voltage gain and circuit structure considered, to be summarized in

Table 1. Asymmetric 5-level single-phase inverters.

Reference Number	Voltage Gain	Circuit Features
		Main	Additional
[2]	0.75	T-Type	Diode Clamp plus Bidirectional Switches
[34]	0.5	T-type	Active Clamp plus Flywheeling Capacitor
[35]	2.0	T-Type	Front-End Buck-Boost Converter
[36]	1.0	NPC	Floating Capacitor
[37]	0.5	Multi-Switches	Floating Capacitor
[38]	2.0	Cascade-HB	3 DC Sources
[39]	2.0	Multi-Switches	2 DC Sources
[40]	1.0	T-Type	H-Bridge
[41]	2.0	SC	T-Type
[42]	2.0	T-Type	2 DC Sources plus Bidirectional Switches
[43]	2.0	HB	Cascaded-HB
[31]	0.5	FC	Active Clamp
[44]	10.0	Multi-Switches	Boost Converter plus Floating Capacitor
[45]	2.0	Multi-Switches	Flywheeling Capacitor
[46]	1.0	HB	Multi-Switches
[47]	2.0	NPC	HB
[48]	1.0	FC	HB
[49]	0.5	T-type	T-type

.

1.3. Contributions

In this paper, two types of asymmetric switched-capacitor five-level single-phase DC-AC inverters are presented based on the clamping half-bridge circuit and the output half-bridge circuit. Furthermore, the switches of the two proposed circuits can be driven by half-bridge gate drivers and can be modularized. Not only can the sinusoidal output voltage with high efficiency and low harmonic distribution (THD) be obtained for the AC power source, but also analysis can be carried out on the operation principle, clamping capacitor, and output filter design of these two inverters in detail. In addition, the feasibility and effectiveness of the proposed structures are demonstrated by PSIM simulation software (9.11 version), and an FPGA chip is used as a digital control kernel to implement the inverters to stabilize the sinusoidal output voltages.

The contents of the paper are outlined as follows. Section 2 illustrates the proposed MLI, including circuit descriptions, switching patterns, and operating principles. Section 3 describes how to design power components. Section 4 displays simulated and experimental results along with discussions. Finally, Section 5 makes some conclusions.

2. Operating Principles of the Proposed Inverters

The proposed two types of asymmetric capacitor-switched five-level DC-AC inverters are constructed and shown in Figure 2 and Figure 3. From these two circuits, the output of the half-bridge circuit, connected to the load, is called an output half bridge; similarly, the double-voltage clamping circuit is composed of a half-bridge circuit, diodes, capacitors, and power switches, and accordingly the function of this half-bridge circuit is called a clamping half bridge.

2.1. Symbol Definitions and Circuit Assumptions

Prior to analyzing the operating principles of the proposed circuits, the associated symbols and required assumptions are given:

(1)

V_in is the input voltage, v_o is the output voltage, N is the reference point of zero potential, and R_o is the output resistance;

(2)

L_o1 and L_o2 are filter inductors, C_o is a filter capacitor, and C₁ to C₄ are clamping capacitors;

(3)

i_L is the current flowing through inductors L_o1 and L_o2, i_Co is the current flowing through capacitor C_o, and i_o is the output current;

(4)

S₁ to S₈ are switches and D₁ to D₄ are diodes;

(5)

Assuming that the values of the clamping capacitors are large enough, the voltages across them can be reviewed as constant values;

(6)

All components are assumed to be ideal.

2.2. Operating Principles for Two Proposed Types of Circuits

2.2.1. Type-1 Circuit

Figure 4 shows the waveforms of the switching signals for the proposed type-1 circuit, where the switches S₁ and S₂ are removed. There are six states of the circuit operation behavior, from state I to state VI.

When the output voltage operates in the positive half-cycle, the switch S₃ always remains on. The inverter works between states I and II mainly by PWM-switching of S₅ to establish the first voltage level, and the switch S₇ is driven by the complementary signal of S₅, whereas the inverter works between states II and III mainly by PWM-switching of S₅ to establish the second voltage level, and at this time the switch S₇ remains off.

When the output voltage operates in the negative half-cycle, the switch S₃ always remains off. The inverter works between states IV and V mainly by PWM-switching of S₇ to establish the first voltage level, and the switch S₅ is driven by the complementary signal of S₇, whereas the inverter works between states V and VI mainly by PWM-switching of S₅ to establish the second voltage level, and at this time the switch S₇ remains on.

In addition, the PWM gate driving signals of the switches S₄, S₆, and S₈ are complementary to the gate driving signals of the switches S₃, S₅, and S₇, respectively.

As shown in Figure 5, when the output voltage operates in the positive half-cycle, the control force v_ctrl performs LS-PWM with triangular waves u₃ and u₄. When the control force v_ctrl locates between zero and triangular wave u₃, the inverter enters into state I. When the control force v_ctrl locates between triangular waves u₃ and u₄, the inverter enters into state II. When the control force v_ctrl is greater than triangular wave u₄, the inverter enters into state III.

In addition, the gate driving signals of switches S₄, S₆, and S₈ are complementary to the gate driving signals of switches S₃, S₅, and S₇, respectively.

Furthermore, as shown in Figure 5, the output voltage of the type-1 circuit works in the positive half-cycle with two switching modes. By comparing the control force v_ctrl with the triangular wave u₃, the inverter is switched between states I and II, and the duty cycle in state II is controlled as D_a; by comparing the control force v_ctrl with the triangular wave u₄, the inverter is switched between states II and III, and the duty cycle in state III is controlled as D_b. The duty cycles D_a and D_b are shown in (1) and (2), respectively:

$$D_a=\frac{v_{ctrl}}{V_m}, 0<v_{ctrl}<V_m$$

(1)

$$D_b=\frac{v_{ctrl}}{V_m}-1, V_m<v_{ctrl}<2V_m$$

(2)

where V_m is the peak-to-peak value of the triangular waves u₃ and u₄.

State I [0 < v_ctrl < u₃]: As shown in Figure 6a, the switches S₃, S₆, and S₇ are on, and the switches S₄, S₅, and S₈ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₃, S₆, and S₇, and the diode D₁ to form a loop. Therefore, the voltage between the terminals A and B is zero, namely, v_AB = 0.

State II [u₃ < v_ctrl < u₄]: As shown in Figure 6b, the switches S₃, S₅, and S₈ are on, and the switches S₄, S₆, and S₇ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₃ and S₈ and the diodes D₁ and D₄ to form a loop. Therefore, the voltage between the terminals A and B is V_in, namely, v_AB = V_in.

State III [u₄ < v_ctrl]: As shown in Figure 6c, the switches S₃, S₆, and S₈ are on, and the switches S₄, S₅, and S₇ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₃, S₆, and S₈ and the diode D₁ to form a loop, and therefore, the voltage between the terminals A and B is 2 V_in, namely, v_AB = 2 V_in.

As shown in Figure 7, when the output voltage operates in the negative half-cycle, the control force v_ctrl performs LS-PWM with triangular waves u₁ and u₂. When the control force v_ctrl locates between zero and triangular wave u₁, the inverter enters into state IV. When the control force v_ctrl locates between triangular waves u₁ and u₂, the inverter enters into state V. When the control force v_ctrl is smaller than triangular wave u₄, the inverter enters into state VI.

In addition, the gate driving signals of switches S₃, S₅, and S₇ are complementary to the gate driving signals of switches S₄, S₆, and S₈, respectively.

As shown in Figure 7, the output voltage of the type-1 circuit works in the negative half-cycle with two switching modes. By comparing the control force v_ctrl with the triangular wave u₂, the inverter is switched between states IV and V, and the duty cycle in state V is controlled as D_c; by comparing the control force v_ctrl with the triangular wave u₁, the inverter is switched between states V and VI, and the duty cycle in state VI is controlled as D_d. The duty cycles D_c and D_b are shown in (3) and (4), respectively:

$$D_c=-\frac{v_{ctrl}}{V_m},-V_m<v_{ctrl}<0$$

(3)

$$D_d=-\frac{v_{ctrl}}{V_m}-1,-2V_m<v_{ctrl}<-V_m$$

(4)

where V_m is the peak-to-peak value of the triangular waves u₁ and u₂.

State IV [u₂ < v_ctrl < 0]: As shown in Figure 8a, the switches S₄, S₅, and S₈ are on, and switches S₃, S₆, and S₇ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₄, S₅, and S₈ and the diode D₂ to form a loop, and therefore, the voltage between the terminals A and B is zero, namely, v_AB = 0.

State V [u₁ < v_ctrl < u₂]: As shown in Figure 8b, the switches S₄, S₆, and S₇ are on, and the switches S₃, S₅, and S₈ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₄ and S₇ and the diodes D₂ and D₃ to form a loop, and therefore, the voltage between the terminals A and B is −V_in, namely, v_AB = −V_in.

State VI [v_ctrl < u₁]: As shown in Figure 8c, the switches S₄, S₅, and S₇ are on, and the switches S₃, S₆, and S₈ are off. The inductor current i_L will flow from the input voltage V_in through switches S₄, S₅, and S₇ and the diode D₂ to form a loop, and therefore, the voltage between the terminals A and B is −2 V_in, namely, v_AB = −2 V_in.

2.2.2. Type-2 Circuit

Figure 9 shows the waveforms of the switching signals of the proposed type-2 circuit, and there are six states of the circuit operation behavior. The signals v_gs1 to v_gs8 are the gate driving signals for switches S₁ to S₈.

When the output voltage operates in the positive half-cycle, the switch S₁ always remains on, the inverter operates between states I and II mainly by PWM-switching of S₅ to build up the first voltage level, and the switch S₇ is driven by the complementary signal of S₅, whereas the inverter operates between states II and III mainly by PWM-switching of S₅ to build up the second voltage level, and at this time switch S₇ remains on.

When the output voltage operates in the negative half-cycle, the switch S₁ always remains off, the inverter operates between states IV and V mainly by PWM-switching of S₇ to build up the first voltage level, and the switch S₅ is driven by the complementary signal of S₇, whereas the inverter operates between states V and VI mainly by PWM-switching of S₅ to build up the second voltage level, and at this time the switch S₇ remains on.

Moreover, the gate driving signals of switches S₂, S₆, and S₈ are complementary to the gate driving signals of the switches S₁, S₅, and S₇, respectively.

As shown in Figure 10, when the output voltage operates in the positive half-cycle, the control force v_ctrl does LS-PWM with triangular waves u₃ and u₄. When the control force v_ctrl locates between zero and triangular wave u₃, the inverter enters into state I. When the control force v_ctrl locates between triangular waves u₃ and u₄, the inverter enters into state II. When the control force v_ctrl is larger than triangular wave u₃, the inverter enters into state III.

Moreover, the gate driving signals of the switches S₄, S₆, and S₈ are complementary to the gate driving signals of the switches S₃, S₅, and S₇, respectively.

Furthermore, as shown in Figure 10, the output voltage of the type-2 circuit works in the positive half-cycle with two switching modes. By comparing the control force v_ctrl with the triangular wave u₃, the inverter is switched between states I and II, and the duty cycle in state II is controlled as D_a; by comparing the control force v_ctrl with the triangular wave u₄, the inverter is switched between states II and III, and the duty cycle in state III is controlled as D_b. In addition, the PWM-switching of the switches S₅ to S₈ in the type-2 circuit is the same as that in the type-1 circuit, so the duty cycles D_a and D_b in the type-2 circuit are the same as those in the type-1 circuit, as shown in (1) and (2).

State I [0 < v_ctrl < u₃]: As shown in Figure 11a, the switches S₁, S₆, and S₇ are on, and the switches S₂, S₅, and S₈ are off. The inductor current i_L will flow from the input voltage V_in through switches S₁, S₆, and S₇ to form a loop, and therefore, the voltage between the terminals A and B is zero, namely, v_AB = 0.

State 2 [u₃ < v_ctrl < u₄]: As shown in Figure 11b, the switches S₁, S₅, and S₈ are on, and the switches S₂, S₆, and S₇ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₁, S₈, and the diode D₄ to form a loop, and therefore, the voltage between the terminals A and B is V_in, namely, v_AB = V_in.

State 3 [u₄ < v_ctrl]: As shown in Figure 11c, the switches S₁, S₆, and S₈ are on, and the switches S₂, S₅, and S₇ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₁, S₆, and S₈ to form a loop, and therefore, the voltage between the terminals A and B is 2 V_in, namely, v_AB = 2 V_in.

As shown in Figure 12, when the output voltage operates in the negative half-cycle, the control force v_ctrl performs LS-PWM with triangular waves u₁ and u₂. When the control force v_ctrl locates between zero and triangular wave u₁, the inverter enters into state IV. When the control force v_ctrl locates between triangular waves u₁ and u₂, the inverter enters into state V. When the control force v_ctrl is smaller than triangular wave u₄, the inverter enters into state VI.

Moreover, the gate driving signals of switches S₃, S₅, and S₇ are complementary to the gate driving signals of switches S₄, S₆, and S₈, respectively.

Furthermore, as shown in Figure 12, the output voltage of the type-2 circuit works in the negative half-cycle with two switching modes. By comparing the control force v_ctrl with the triangular wave u₂, the inverter is switched between states IV and V, and the duty cycle in state V is controlled as D_c; by comparing the control force v_ctrl with the triangular wave u₁, the inverter is switched between states V and VI the duty cycle in state VI is controlled as D_d.

Moreover, since the PWM-switching of the switches S₅ to S₈ in the type-2 circuit are the same as that in the type-1 circuit, the duty cycles D_c and D_d in the type-2 circuit are identical to those in the type-1 circuit, as shown in (3) and (4).

State 4 [u₂ < v_ctrl < 0]: As shown in Figure 13a, the switches S₂, S₅, and S₈ are on and the switches S₁, S₆, and S₇ are off. The inductor current i_L will flow from the input V_in voltage through the switches S₂, S₅, and S₈ to form a loop, and therefore, the voltage between the terminals A and B is zero, namely, v_AB = 0.

State 5 [u₁ < v_ctrl < u₂]: As shown in Figure 13b, the switches S₂, S₆, and S₇ are on and the switches S₁, S₅, and S₈ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₂, S₆, and S₇ and the diode D₃ to form a loop, and therefore, the voltage between terminals A and B is −V_in, namely, v_AB = −V_in.

State 6 [v_ctrl < u₁]: As shown in Figure 13c, the switches S₂, S₅, and S₇ are on and the switches S₁, S₆, and S₈ are off. The inductor current i_L will flow from the input voltage V_in through the switches S₂, S₅, and S₇ to form a loop, and therefore the voltage between the terminals A and B is −2 V_in, namely, v_AB = −2 V_in.

2.3. Converter Component Operating Behavior

For clarity and completeness,

Table 2. Converter component operating behavior (1: On, 0: Off, C: Charge, D: Discharge).

Circuit	States	Switches								Capacitors				AC Output
		S1	S2	S3	S4	S5	S6	S7	S8	C1	C2	C3	C4	vAN	vBN	vAB
Type-1	1	---	---	1	0	0	1	1	0	---	---	C	---	1 Vin	1 Vin	0 Vin
	2	---	---	1	0	1	0	0	1	---	---	---	C	1 Vin	0 Vin	1 Vin
	3	---	---	1	0	0	1	0	1	---	---	C	D	1 Vin	−1 Vin	2 Vin
	4	---	---	0	1	1	0	0	1	---	---	---	C	0 Vin	0 Vin	0 Vin
	5	---	---	0	1	0	1	1	0	---	---	C	---	0 Vin	1 Vin	−1 Vin
	6	---	---	0	1	1	0	1	0	---	---	D	C	0 Vin	2 Vin	−2 Vin
Type-2	1	1	0	---	---	0	1	1	0	---	C	C	---	1 Vin	1 Vin	0 Vin
	2	1	0	---	---	1	0	0	1	---	C	---	C	1 Vin	0 Vin	1 Vin
	3	1	0	---	---	0	1	0	1	---	C	C	D	1 Vin	−1 Vin	2 Vin
	4	0	1	---	---	1	0	0	1	C	---	---	C	0 Vin	0 Vin	0 Vin
	5	0	1	---	---	0	1	1	0	C	---	C	---	0 Vin	1 Vin	−1 Vin
	6	0	1	---	---	1	0	1	0	C	---	D	C	0 Vin	2 Vin	−2 Vin

shows the switch behavior and clamping capacitor charging/discharging behavior of type-1 and type-2 circuits.

In addition, based on the above analysis,

Table 3. Circuit comparison between the existing and proposed topologies.

Inverter Type	Level Voltage	S1	S2	S3	S4	S5	S6	S7	S8
Diode Neutral-Point-Clamped (Figure 1a, [29])	0 Vin	0	0	1	1	0	1	---	---
	0.5 Vin	0	1	1	0	0	1	---	---
	1 Vin	1	1	0	0	0	1	---	---
	−0.5 Vin	1	1	0	0	1	0	---	---
	−1 Vin	0	1	1	0	1	0	---	---
T-type Neutral-Point-Clamped (Figure 1b, [30])	0 Vin	0	0	1	1	0	1	---	---
	0.5 Vin	0	1	1	0	0	1	---	---
	1 Vin	1	1	0	0	0	1	---	---
	0 Vin	1	1	0	0	1	0	---	---
	−0.5 Vin	0	1	1	0	1	0	---	---
	−1 Vin	0	0	1	1	1	0	---	---
Flywheel Capacitor (Figure 1c, [31])	0 Vin	0	0	1	1	0	1	---	---
	0.5 Vin	1	0	1	0	0	1	---	---
	1 Vin	1	1	0	0	0	1	---	---
	0 Vin	0	1	0	1	0	1	---	---
	0.5 Vin	1	1	0	0	1	0	---	---
	−0.5 Vin	0	1	0	1	1	0	---	---
	−1 Vin	1	0	1	0	1	0	---	---
	−0.5 Vin	0	0	1	0	1	0	---	---
Proposed (Type-1)	0 Vin	---	---	1	0	0	1	1	0
	1 Vin	---	---	1	0	1	0	0	1
	2 Vin	---	---	1	0	0	1	0	1
	0 Vin	---	---	0	1	1	0	0	1
	−1 Vin	---	---	0	1	0	1	1	0
	−2 Vin	---	---	0	1	1	0	1	0
Proposed (Type-2)	0 Vin	1	0	---	---	0	1	1	0
	1 Vin	1	0	---	---	1	0	0	1
	2 Vin	1	0	---	---	0	1	0	1
	0 Vin	0	1	---	---	1	0	0	1
	−1 Vin	0	1	---	---	0	1	1	0
	−2 Vin	0	1	---	---	1	0	1	0

shows the switching status of the proposed five-level MLIs and their corresponding output voltages, together with the existing three circuits shown in Figure 1, are employed as comparisons. From this table, it can be seen that the voltage gains of the proposed inverters have two times those of the existing topologies.

3. System Design

3.1. System Configuration

Figure 14 shows the system block diagram of the switched-capacitor five-level DC-AC inverter. The system configuration includes the main power stage containing a type-1 circuit or type-2 circuit, the gate drivers, and the output voltage feedback circuit containing the voltage divider, FPGA, DAC, and voltage sampling circuit without ADC. The operating principle of the main stage has already been discussed in the previous section, and the UCC21540 isolated driver is used as the gate driving circuit. In terms of the voltage feedback circuit, the output voltage v_o is divided into a small voltage signal v_od, and the reference voltage v_ref is subtracted from v_od to obtain an error signal which will be modulated into a pulse signal v_pulse via no ADC sampling technique [50]. After this, this signal v_pulse is sent to the FPGA with the PI controller embedded and converted to a signal v_FB, which will be then compensated to obtain the corresponding gate driving signals.

Table 4. Specifications of the proposed inverter.

Input Voltage (Vin)	58 V
Output AC Voltage (vo)	75 Vrms
Output Frequency (fline)	60 Hz
Rated Power (Po,rated)	250 W
Switching Frequency (fs)	58.6 kHz

shows the specifications of the proposed switched-capacitor five-level DC-AC inverter.

3.2. Design of Clamping Capacitor

In this paper, the AC output voltage frequency f_line is set at 60 Hz, which can be converted to an angular frequency of 377 (rad/s), and the time instants of clamping capacitor discharge in the positive half-cycle are calculated based on (5) to (8), which are shown as follows:

$$t_1=\frac{{\sin }^{-1}(\frac{2}{3})}{\omega }=1.936\mathrm{ms}$$

(5)

$$t_2=\frac{\pi }{2\cdot \omega }-\frac{0.5}{f_s}=4.1581\mathrm{ms}$$

(6)

$$t_3=\frac{\pi }{2\cdot \omega }+\frac{0.5}{f_s}=4.1752\mathrm{ms}$$

(7)

$$t_4=\frac{\pi }{\omega }-t_1=6.398\mathrm{ms}$$

(8)

The clamping capacitors used in the inverter can be divided into two classes according to the charging and discharging time. States III and IV are taken as examples. Figure 15 displays that the clamping capacitor C₁ in the first class is used as a DC power source for discharging when entering state III and providing state IV operation, whereas the clamping capacitor C₄ in the second class is used for fast charging and discharging behavior in accordance with the transition between these two states.

The maximum discharging charge of clamping capacitors C₁ and C₄ in the positive half-cycle can be calculated from (9) and (10) as follows:

$$\Delta Q_1={\displaystyle {\int }_{t_1}^{t_4}\sqrt{2}\cdot I_{o,rated}\cdot \sin \omega tdt}=25.43\mathrm{mC}$$

(9)

$$\Delta Q_4={\displaystyle {\int }_{t_2}^{t_3}\sqrt{2}\cdot I_{o,rated}\cdot \sin \omega tdt}=109.7\mu \mathrm{C}$$

(10)

In general, the ripple voltage on the capacitor is 1% of the DC voltage across it, so the corresponding ripple voltage is shown below:

$$\Delta V=58\times 0.01=0.58\mathrm{V}$$

(11)

Generally acknowledged, the amount of voltage change is proportional to the amount of charge change. As far as the symmetrical circuit structure is concerned, the clamping capacitance of C₃ is equal to the capacitance of C₁, and in the same way, the clamping capacitance of C₂ is equal to the capacitance C₄. Substituting (9)–(11) into (12) and (13) yields the clamping capacitances of C₁ to C₄ as follows:

$$C_1=C_3=\frac{\Delta Q_1}{\Delta V}=\frac{25.43\mathrm{mC}}{0.58\mathrm{V}}=43.837\mathrm{mF}$$

(12)

$$C_4=C_2=\frac{\Delta Q_4}{\Delta V}=\frac{109.7\mu C}{0.58\mathrm{V}}=189\mu \mathrm{F}$$

(13)

In (12), the value of C₁ and C₃ is calculated to be $43.837\mathrm{mF}$, which is too large for the 250 W DC-AC inverter. Therefore, the output voltage must not be affected by appropriate reduction of this capacitance, so the actual test of the capacitor ripple voltage is fixed at 4 V to get a better result, and re-substitution of this value into (12) can obtain (14) as follows:

$$C_1=C_3=C=\frac{\Delta Q_1}{\Delta V}=\frac{25.43\mathrm{mC}}{4\mathrm{V}}=6.356\mathrm{mF}$$

(14)

The capacitors C₁ to C₄, which are analyzed in the previous section for the type-1 and type-2 circuits, will be charging and discharging in accordance with the switching frequency, so it is sufficient to use the same capacitance of $6.356\mathrm{mF}$ for these capacitors. In addition, according to the analysis of the circuit operation principle, it can be seen that the voltages across such clamping capacitors are approximately equal to the input voltage. Since the electrolytic capacitors used should be derated, the rated voltage of the selected capacitors should be more than 1.5 times of the input voltage, that is,

$$V_{C,rated}\ge 1.5\times 58=87\mathrm{V}$$

(15)

Eventually, two 3.3 mF electrolytic capacitors paralleled can be used for these four capacitors.

3.3. Design of High Frequency Low-Pass Filter

When the inverters operate, the THD of the utility voltage supplied by the power company should be taken into account. According to the IEEE 519 standard [3], the total harmonic voltage distortion limit is 8% or less below 1 kV, implying that each harmonic voltage distortion should be 5% or less.

The harmonic components of the output voltage from a high-frequency switching inverter can be categorized into two cases. One is low-frequency harmonics generated by the fundamental waveform of the output voltage, locating between several to several tens of times of the line frequency, and the other is high-frequency harmonics generated by the switching of the switch. In the former case, the controller can be used for the closed-loop control to reduce the low-frequency harmonics by increasing the loop gain. In the latter case, the low-pass filter can be used to reduce the high-frequency harmonics.

As shown in Figure 16, the inductors L_o1 and L_o2 and the capacitor C_o are used to construct this second-order low-pass filter.

Due to the characteristics of the multi-level output voltage, it is possible to add a second-order low-pass filter with a higher cutoff radian frequency and the corresponding transfer function is as follows:

$$H\left(s\right)=ℒ\left\{\frac{v_o(t)}{v_{AB}(t)}\right\}=\frac{V_o(s)}{V_{AB}(s)}=\frac{1}{\frac{s^2}{{\omega }_c^2}+\frac{s}{Q\cdot {\omega }_c}+1}=\frac{1}{\frac{s^2}{L\cdot C_o}+s\frac{L}{R_o}+1}$$

(16)

where $L=L_{o1}+L_{o2}$; and the cutoff radian frequency is ${\omega }_c=\frac{1}{\sqrt{L\cdot C_o}}$, and the quality factor $Q=R_o\sqrt{\frac{C_o}{L}}$.

As shown in (17), the peak-to-peak ripple voltage v_rpp of the inverter is limited to 0.01 times of the maximum output voltage to reduce the high-frequency harmonic components of the output voltage. Equation (18) is used to calculate the value of v_rpp generated during the switching period. Since the operating principle of the inverter is similar to that of a buck inverter, the calculation method shown in [51] is adopted. Also, the peak-to-peak value of the inductor current generated during the switching period is shown in (19):

$$v_{rpp}=0.01\cdot \mathrm{Gain}\cdot V_{in}=0.01\times 3\times 58=1.74\mathrm{V}$$

(17)

$$v_{rpp}=\frac{1}{2}\cdot \frac{\Delta i_L}{2}\cdot \frac{1}{2\cdot f_s}\cdot \frac{1}{C_o}$$

(18)

$$\Delta i_L=\frac{V_{in}.D.(1-D)}{L.f_s}$$

(19)

Substituting (19) into (18) yields the effect of the filter inductor L and filter capacitor C_o on v_rpp, as shown in (20). In (20), it is also known that the maximum value of v_rpp will happen when the duty cycle D is 0.5. Therefore, substituting (20) into (21) yields and the cutoff frequency is f_c, as shown in (22):

$$v_{rpp}=\frac{V_{in}\cdot D\cdot (1-D)}{8\cdot L\cdot C_o\cdot f_s^2}=\frac{V_{in}\cdot D\cdot (1-D)}{8\cdot {\omega }_c^{-2}\cdot f_s^2}$$

(20)

$${\omega }_c=\sqrt{\frac{8\cdot v_{rpp}}{V_{in}\cdot D\cdot (1-D)}}\cdot f_s=\sqrt{\frac{8\cdot 1.74}{58\cdot 0.5\cdot (1-0.5)}}\cdot 58.6\mathrm{kHz}=57416.04 (\mathrm{rad}/\mathrm{s})$$

(21)

$$f_c=\frac{{\omega }_c}{2\cdot \pi }=9.138 \mathrm{kHz}$$

(22)

In (16), the relationship between the filter inductance L, the filter capacitance C_o, the load resistance R_o, and the cut-off radian frequency on the quality factor Q can also be obtained. Therefore, the value of Q at rated load is set at the inverse value of 0.707, and then the values of L and C_o can be obtained as shown in (23) and (24), respectively:

$$L=\frac{R_o}{Q\cdot {\omega }_c}=\frac{24.2}{1.414\cdot 57416.04}=298\mu \mathrm{H}$$

(23)

$$C_o=\frac{Q}{R\cdot {\omega }_c}=\frac{1.414}{24.2\cdot 57416.04}=1.02\mu \mathrm{F}$$

(24)

Eventually, a 1 μF metal film capacitor, manufactured by HJC Co., Seoul, Republic of Korea [52], is chosen.

4. Verification Based on Simulation and Experiment

In this section, the results of the proposed switched-capacitor five-level single-phase DC-AC inverters are simulated and experimented. First, the design parameters obtained in the previous section are put into the circuits to construct the PSIM simulation environment to simulate the closed-loop control of the proposed inverters so that the feasibility of the proposed two circuits can be demonstrated. After this, the FPGA is used as the digital control kernel to obtain experimental results so as to verify their effectiveness.

4.1. Simulated and Experimental Waveforms of Type-1 Circuit

Under the type-1 circuit at rated load, Figure 17 shows the output voltage v_o and output current i_o. Figure 18 shows the output voltage v_o and the unfiltered output voltage v_AB. Figure 19 shows the gate driving signals v_gs3, v_gs5, and v_gs7 for the switches S₃, S₅, and S₇, respectively. Figure 20 shows the gate driving signals v_gs4, v_gs6, and v_gs8 for the switches S₄, S₆, and S₈, respectively. Figure 21 shows the voltages across the clamping capacitors C₁ and C₂, called v_C1 and v_C2, respectively. Figure 22 shows the voltages across the clamping capacitors C₃ and C₄, called v_C3 and v_C4, respectively. Figure 23 shows the voltages across the switches S₃, S₅, and S₇, called v_ds3, v_ds5, and v_ds7, respectively. Figure 24 shows the voltages across the switches S₄, S₆, and S₈, called v_ds4, v_ds6, and v_ds8, respectively.

4.2. Simulated and Experimental Waveforms s of Type-2 Circuit

Under the type-2 circuit at rated load, Figure 25 shows the output voltage v_o and output current i_o. Figure 26 shows the output voltage v_o and the unfiltered output voltage v_AB. Figure 27 shows the gate driving signals v_gs3, v_gs5, and v_gs7 for the switches S₃, S₅, and S₇, respectively. Figure 28 shows the gate driving signals v_gs4, v_gs6, and v_gs8 for the switches S₄, S₆, and S₈, respectively. Figure 29 shows the voltages across the clamping capacitors C₁ and C₂, called v_C1 and v_C2, respectively. Figure 30 shows the voltages across the clamping capacitors C₃ and C₄, called v_C3 and v_C4, respectively. Figure 31 shows the voltages across the switches S₃, S₅, and S₇, called v_ds3, v_ds5, and v_ds7, respectively. Figure 32 shows the voltages across the switches S₄, S₆, and S₈, called v_ds4, v_ds6, and v_ds8, respectively.

4.3. Waveform Comparison of the Two Types

From the waveforms in Figure 19, Figure 20, Figure 21, Figure 22, Figure 23 and Figure 24, it can be seen that the type-1 circuit adopts the PWM-switching of mixing high and low speeds to generate the gate driving signals to drive the switches. The switches S₃ and S₄ switch with the output frequency, and the switches S₅ to S₈ switch with the high frequency to get the unfiltered output voltage v_AB, and then the output voltage v_o and output current i_o with low harmonic components are obtained through the filter. Moreover, the switching behavior of the switch is ignored by the blanking time, and this is because the switching period under this control state is too small, so the corresponding waveforms are not controlled. Accordingly, the gate driving signal of the switch can be seen as part of the switching cycle with the constant cutoff period. Figure 22 shows the clamping capacitors C₃ and C₄, which are clamped at the input voltages by switching the diodes D₃ and D₄, and the switches S₅ and S₆, with the result that the voltages across the clamping capacitor C₃ and C₄, called v_C3 and v_C4, are clamped at the input voltage. As shown in Figure 23 and Figure 24, the switches S₃ and S₄ are connected across the two ends of two series capacitors C₁ and C₂; the maximum voltages across the switches S₃ and S₄ are the sum of the voltages across the clamping capacitors C₁ and C₂, called v_C1 and v_C2. Similarly, the switches S₇ and S₈ are connected across the two ends of two series capacitors C₃ and C₄, and it is known that the capacitors C₃ and C₄ are clamped at the input voltages, so the maximum voltages across the switches S₇ and S₈ are two times the input voltage. Therefore, the switches S₇ and S₈ have to withstand twice the input voltage, while the switches S₅ and S₆ are connected to the input voltage, i.e., they only have to withstand the input voltage. In addition, due to the switch-opened detection being embedded in the experiment, the corresponding voltages across the switches have part of the blanking time, thereby making the experimental waveforms different from the simulated waveforms.

From the waveforms in Figure 25, Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31 and Figure 32, it can be seen that the type-2 circuit adopts the PWM-switching of mixing high and low speeds to generate the driving signals to drive the switches. The switches S₁ and S₂ switch with the output frequency, and the switches S₅ to S₈ switch with the high frequency to get the unfiltered output voltage v_AB, and then the output voltage v_o and output current i_o with low harmonic components are obtained through the filter. In addition, the switching behavior of the switch is ignored by the blanking time, and this is because the switching period under this control state is too small, so the corresponding waveforms are not controlled. Accordingly, the gate driving signal of the switch can be seen as part of the switching cycle with the constant cutoff period. Figure 30 shows the voltages across the clamping capacitors C₃ and C₄, called v_C3 and v_C4, are switched by the switches S₅ and S₆ to clamp the clamping capacitors C₃ and C₄ to the input voltage. As can be seen from Figure 31 and Figure 32, the switches S₇ and S₈ are connected across the two ends of the two series capacitors C₃ and C₄, and since the two clamping capacitors C₃ and C₄ are clamped at the input voltage, so the maximum voltages across the switches S₇ and S₈ are two times the input voltage, whereas the switches S₁, S₂, S₅, and S₆ are connected across the input voltage so the maximum voltages across them are the input voltage. Moreover, due to the switch-opened detection being embedded in the experiment, the corresponding voltages across the switches also have part of the blanking time, thus causing the experimental waveforms to be different from the simulated waveforms.

4.4. Harmonic Distribution and Efficiency of Two Types

Figure 33a,b show the harmonic distribution of the output voltage at rated load for the type-1 and type-2 circuits, respectively. From these figures, the values of THD, measured by the power analyzer (PM1000+), are 0.71% and 0.78% for the type-1 and type-2 circuits, respectively. All these values of THD comply with IEEE 519-2014, which states that the THD of harmonics voltage should be less than 8%.

Figure 34a,b show the curves of efficiency versus output power for the type-1 and type-2 circuits, respectively. From Figure 34a, it can be seen that for the type-1 circuit, the maximum efficiency is 97.43% and the minimum efficiency is 95.81%, whereas for the type-2 circuit, the maximum efficiency is 96.87% and the minimum efficiency is 95.80%, respectively. This is because these two circuits are designed to reduce the number of power-switching times by using a mixed high and low speed control strategy. However, the load current will flow through the diode, and the accompanying conduction loss caused will affect the overall efficiency, i.e., the higher the load is, the lower the efficiency.

4.5. Comparison between the Recent Related MLIs

Under the condition of the same number of DC power sources, a comparison of the recent papers presented for the five-level single-phase DC-AC inverters [2,31,43,44,45,46,47,48,49] with various criteria and feature emphases is tabulated in

Table 5. Comparison of the recent papers presented for 5-level single-phase DC-AC inverters.

	[2]	[43]	[31]	[45]	[46]	[47]	[48]	[49]	[50]	Proposed (Type-1)	Proposed (Type-2)
Number of Levels	5	5	5	5	5	5	5	5	5	5	5
Number of Switches	8	6	8	7	6	14	10	10	14	6	6
Number of Diodes	2	0	0	0	0	12	0	0	12	4	4
Number of Capacitors	2	1	3	2	2	0	5	1	2	4	4
Voltage Gain	0.75	1	0.5	10	1	1	2	1	0.5	2	2
Number of DC Power Sources	1	1	1	1	1	1	1	1	1	1	1
Two-Terminal Output	Yes	Yes	Yes	No	Yes	No	No	Yes	No	Yes	Yes
Rated-Load Power (W)	1000	25	300	400	1250	1450	250	250	1450	250	250
Input Voltage (V)	400	24	128	40	350	400	100	200	400	58	58
Peak Output Voltage (V)	311	21.6	64	400	350	400	200	---	141	106	106
Rated-load THD (%)	---	33.27	3.86	35.11	1.55	1.58	---	24.41	2.15	0.71	0.78
Peak Efficiency (%)	97.09	95.21	---	97.50	98.70	---	---	---	---	96.87	95.80
Control Strategy	UP-PWM/ OLC-PWM	PS-PWM	PS-PWM/PD-PWM	SPWM	PD-PWM	PD-SPWM	SPWM	LS-SPWM	PD-SPWM	LS-SPWM	LS-SPWM
Full Modularization	Yes	Yes	No	Yes	No	No	Yes	Yes	Yes	Yes	Yes

. Additionally, in this table, the full names for all the abbreviations of control strategies are shown in

Table 6. The full names for the abbreviations of control strategy in Table 5.

Abbreviation	Full Name
OLC-PWM	One-Leg Clamping-PWM
UP-PWM	Unipolar-PWM
PS-PWM	Phase Shifted-PWM
PD-PWM	Phase Disposition-PWM
SPWM	Sinusoidal Pulse Width Modulation
LS-SPWM	Level Shifted-SPWM

. From Table 5, it can be seen that the THD of the proposed inverters is least among those of the recent related inverters.

5. Conclusions

In this paper, two types of asymmetric switched-capacitor five-level single-phase DC-AC inverters are presented based on the clamping half-bridge circuit and the output half-bridge circuit. Furthermore, the half-bridge gate drivers can be used to drive the switches. From the measured results, the type-1 and type-2 circuits have the maximum efficiency of 97.43% and 96.87%, respectively. From Table 5, it can be seen that the THD of the proposed inverters is the least among those of the recent related inverters, the two-terminal output possesses linearity in control, and the proposed circuits can be implemented by full modularization. Accordingly, the proposed inverter is suitable for renewable energy applications.

6. Future Work

The limitation of the proposed inverter is that the output AC voltage will be affected by the input DC voltage. This will be a research point for the future. In addition, the proposed single-phase inverter will be extended to a three-phase inverter. Furthermore, the features and/or performance of the proposed inverters with some renewable energy-specific switches, such as management of next-generation energy [53], animal fat-based biodiesel supply chain networks [54], herbal medicines and biofuel [55], and various kinds of renewable energy, solar energy, wind energy, bioenergy, hydraulic energy, waste-to-energy, and hydrogen energy [56], can be focused on in the future.