Search Results (42)

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

This study aims to conduct an assessment of the dynamic characteristics of a proposed 6.6 kW bidirectional bridgeless three-leg interleaved totem-pole power factor correction (PFC) boost converter developed for the front-end stage of electric vehicle onboard charger applications during load cycles. This proposed PFC boost converter integrates the self-developed silicon carbide (SiC) power MOSFET modules for achieving high efficiency and high power density. To assess the switching transient behavior, power loss, and efficiency of the SiC MOSFET power modules, a fully integrated electromagnetic-circuit coupled simulation (ECCS) model that incorporates an electromagnetic model, an equivalent circuit model, and an SiC MOSFET characterization model are used. In this simulation model, the impact of parasitic effects on the system’s performance is considered. The accuracy of the ECCS model is confirmed through comparing the calculated results with the experimental data obtained through the double pulse test and the closed-loop converter operation. Furthermore, a comparative study between the interleaved and non-interleaved topologies is also performed in terms of power loss and efficiency. Additionally, the performance of the SiC MOSFET-based PFC boost converter is further compared with that of the silicon (Si) insulated gate bipolar transistor (IGBT)-based one. Finally, a parametric analysis is carried out to explore the impact of several operating conditions on the power loss of the proposed totem-pole PFC boost converter. Full article

The chemical–mechanical polishing (CMP) of silicon wafers involves high-precision surface machining after double-sided lapping. Silicon wafers are subjected to chemical corrosion and mechanical removal under pressurized conditions. The multichip CMP process for 4~6-inch silicon wafers, such as those in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated-Gate Bipolar Transistors), and MEMS (Micro-Electromechanical System) field materials, is conducted to maintain multiple chips to improve efficiency and improve polish removal uniformity; that is, the detected TTV (total thickness variation) gradually increases from 10 μm to less than 3 μm. In this work, first, a mathematical model for calculating the small deflection of silicon wafers under pressure is established, and the limit values under two boundary conditions of fixed support and simple support are calculated. Moreover, the removal uniformity of the silicon wafers is improved by improving the uniformity of the wax-coated adhesion state and adjusting the boundary conditions to reflect a fixed support state. Then, the stress distribution of the silicon wafers under pressure is simulated, and the calculation methods for measuring the TTV of the silicon wafers and the uniformity measurement index are described. Stress distribution is changed by changing the size of the pressure ring to achieve the purpose of removing uniformity. This study provides a reference for improving the removal uniformity of multichip silicon wafer chemical–mechanical polishing. Full article

In this paper, the degradation mechanism of the RF performance of 22 nm fully depleted (FD) silicon-on-insulator nMOSFETs at different total ionizing dose levels has been investigated. The RF figures of merit (the cut-off frequency f_T, maximum oscillation frequency f_max) show significant degradation of approximately 14.1% and 6.8%, respectively. The variation of the small-signal parameters (output conductance (g_ds), transconductance (g_m), reflection coefficient (|Γ_in|), and capacitance (C_gg)) at different TID levels has been discussed. TID-induced trapped charges in the gate oxide and buried oxide increase the vertical channel field, which leads to more complex degradation of small-signal parameters across a wide frequency range. Full article

This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (R_ON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV²/R_ON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-R_ON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results. Full article

Many silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) are used in deep space detection systems because they have higher radiation resistance than bulk silicon devices. However, SOI devices have to face the double challenge of radiation and conventional reliability problems, such as hot carrier stress, at the same time. Thus, we wondered whether there is any interaction between reliability degradation and irradiation damage. In this paper, the effect of hot-carrier injection (HCI) on γ-ray-irradiated partially depleted (PD) SOI n-MOSFETs with a T-shaped gate structure is investigated. A strange phenomenon that accelerated the annealing effect on irradiation devices caused by HCI in 5 s was observed. That is, HCI has fast recovery ability on the irradiated narrow-channel n-MOSFETs. We explain the physical mechanism of this recovery effect qualitatively. Moreover, we designed a comparable experiment to evaluate the effect on the wide-channel devices. These results show that the narrow-channel devices are more sensitive to irradiation and HCI effects than wide-channel devices. Full article

Silicon (Si)-based semiconductor devices have long dominated the power electronics industry and are used in almost every application involving power conversion. Examples of these include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gate turn-off (GTO), thyristors, and bipolar junction transistor (BJTs). However, for many applications, power device requirements such as higher blocking voltage capability, higher switching frequencies, lower switching losses, higher temperature withstand, higher power density in power converters, and enhanced efficiency and reliability have reached a stage where the present Si-based power devices cannot cope with the growing demand and would usually require large, costly cooling systems and output filters to meet the requirements of the application. Wide bandgap (WBG) power semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and diamond (Dia) have recently emerged in the commercial market, with superior material properties that promise substantial performance improvements and are expected to gradually replace the traditional Si-based devices in various power electronics applications. WBG power devices can significantly improve the efficiency of power electronic converters by reducing losses and making power conversion devices smaller in size and weight. The aim of this paper is to highlight the technical and market potential of WBG semiconductors. A detailed short-term and long-term analysis is presented in terms of cost, energy impact, size, and efficiency improvement in various applications, including motor drives, automotive, data centers, aerospace, power systems, distributed energy systems, and consumer electronics. In addition, the paper highlights the benefits of WBG semiconductors in power conversion applications by considering the current and future market trends. Full article

In today’s digital circuits, Si-based MOS devices have become the most widely used technology in medical, military, aerospace, and aviation due to their advantages of mature technology, high performance, and low cost. With the continuous integration of transistors, the characteristic size of MOSFETs is shrinking. Time-dependent dielectric electrical breakdown (TDDB) is still a key reliability problem of MOSFETs in recent years. Many researchers focus on the TDDB life of advanced devices and the mechanism of oxide damage, ignoring the impact of the TDDB effect on device parameters. Therefore, in this paper, the critical parameters of partially depleted silicon-on-insulator (PDSOI) under time-dependent dielectric electrical breakdown (TDDB) stress are studied. By applying the TDDB acceleration stress experiment, we obtained the degradation of the devices’ critical parameters including transfer characteristic curves, threshold voltage, off-state leakage current, and the TDDB lifetime. The results show that TDDB acceleration stress will lead to the accumulation of negative charge in the gate oxide. The negative charge affects the electric field distribution. The transfer curves of the devices are positively shifted, as is the threshold voltage. Comparing the experimental data of I/O and Core devices, we can conclude that the ultra-thin gate oxide device’s electrical characteristics are barely affected by the TDDB stress, while the opposite is true for a thick-gate oxide device. Full article

FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications. Full article

The cumulative inverter losses and power consumption of a silicon insulated gate bipolar transistor (Si IGBT) and three types of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) were evaluated on an electric motor test bench under a worldwide harmonized light vehicles test cycle (WLTC). SiC MOSFETs showed higher performance than Si IGBT regardless of the motor type and test vehicles. In the case of driving an interior permanent magnet synchronous motor (IPMSM), the latest 4th generation SiC MOSFET (SiC-4G) in ROHM has the lowest inverter loss and energy consumption compared with the other generations. In the case of driving an induction motor (IM), on the other hand, the 2nd generation SiC MOSFET (SiC-2G) in ROHM has the best energy consumption despite the fact that the inverter losses of SiC-2G are slightly larger than the loss of SiC-4G. The latest or later generation power device does not necessarily contribute to better performance in a total system by simply replacing early power devices. Full article

In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO₂ interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high. Full article

In the emerging process-based transistors, random telegraph noise (RTN) has become a critical reliability problem. However, the conventional method to analyze RTN properties may not be suitable for the advanced silicon-on-insulator (SOI)-based transistors, such as the fully depleted SOI (FDSOI)-based transistors. In this paper, the mechanism of RTN in a 22-nm FDSOI-based metal–oxide–semiconductor field-effect transistor (MOSFET) is discussed, and an improved approach to analyzing the relationship between the RTN time constants, the trap energy, and the trap depth of the device at cryogenic temperatures is proposed. The cryogenic measurements of RTN in a 22-nm FDSOI-based MOSFET were carried out and analyzed using the improved approach. In this approach, the quantum mechanical effects and diffuse scattering of electrons at the oxide–silicon interface are considered, and the slope of the trap potential determined by the gate voltage relation is assumed to decrease proportionally with temperature as a result of the electron distribution inside the top silicon, per the technology computer-aided design (TCAD) simulations. The fitted results of the improved approach have good consistency with the measured curves at cryogenic temperatures from 10 K to 100 K. The fitted trap depth was 0.13 nm, and the decrease in the fitted correction coefficient of the electron distribution proportionally with temperature is consistent with the aforementioned assumption. Full article

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results. Full article

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB. Full article

With the development of power modules for high voltage, high temperature, and high power density, their size is becoming smaller, and the packaging insulation experiences higher electrical, thermal, and mechanical stress. Packaging insulation needs to meet the requirement that internal electric field, temperature, and mechanical stress should be as low as possible. Focusing on the coupling principles and optimization design among electrical, thermal, and mechanical stresses in the power module packaging insulation, a multi-objective optimization design method based on Spice circuit, finite element field numerical calculation, and multi-objective gray wolf optimizer (MOGWO) is proposed. The packaging insulation optimal design of a 1.2 kV SiC MOSFET half-bridge power module is presented. First, the high field conductivity characteristics of the substrate ceramic and encapsulation silicone of the packaging insulation material were tested at different temperatures and external field strengths, which provided the key insulation parameters for the calculation of electric field distribution. Secondly, according to the mutual coupling principles among electric–thermal–mechanical stress, the influence of packaging structure parameters on the electric field, temperature, and mechanical stress distribution of packaging insulation was studied by finite element calculation and combined with Spice circuit analysis. Finally, the MOGWO algorithm was used to optimize the electric field, temperature, and mechanical stress in the packaging insulation. The optimal structural parameters of the power module were used to fabricate the corresponding SiC MOSFET module. The fabricated module is compared with a commercial module by the double-pulse experiment and partial discharge experiment to verify the feasibility of the proposed design method. Full article