Search Results (22)

Financial markets in emerging economies exhibit fractal long-memory dynamics ($H=0.93$ on CBOE VIX; $H=0.81$ on JSE realised volatility) and extreme non-Gaussianity (kurtosis $=51.6$) that together invalidate conventional Gaussian-emission regime models. This paper introduces SARDINE (Stochastic Adaptive Regime Detection via Integrated Neuro-Fuzzy Estimation), a continuous-time framework that embeds Takagi-Sugeno-Kang (TSK) fuzzy membership weights directly inside a stochastic differential equation integrator, governing the geometry of stochastic uncertainty at each integration step. Three formal results underpin the architecture: a Lyapunov-style diffusion stability bound, a regime-adaptive noise attenuation guarantee, and an asymmetric cost advantage condition. Evaluated on 17 JSE Top40 securities ($N=2778$ daily observations, 2015–2026; 537-day held-out test), SARDINE achieves FAR $=0.143$, FNR $=0.195$, and a 1.33-day early-warning lead time, reducing the asymmetric cost by 32% relative to GMM. Against 14 baselines including Neural SDE, PatchTST, and Mamba, the fuzzy-gated diffusion reduces false alarms by 54–63%. A fractional Brownian motion ablation ($H\in \{0.44,0.50,0.93\}$, $B=200$ replicates) reveals that long-memory information should be embedded in the input representation rather than the noise driver; $H=0.50$ is recommended for operational deployment. Full article

Magnetoresistive random-access memory (MRAM), as a promising non-volatile memory technology, has attracted extensive research interest owing to its unique combination of high operating speed, exceptional endurance, low standby power consumption, and CMOS process compatibility. In this review, we provide a comprehensive overview of the technological evolution of MRAM, spanning from Toggle-MRAM to spin-transfer torque (STT)-MRAM and then to spin–orbit torque (SOT)-MRAM. The working mechanisms, performance trade-offs, and integration potential of each generation are systematically summarized. Furthermore, the diverse applications of MRAM—including embedded systems-on-chip (SoCs), edge computing, aerospace and automotive electronics, artificial intelligence accelerators, neuromorphic computing, and hardware-level security—are thoroughly discussed. We also identify key challenges hindering large-scale commercialization, such as the trade-off between write energy and speed, process complexity, storage density constraints, and cost competitiveness. Finally, emerging research directions are proposed, emphasizing short-term priorities such as write current reduction and yield improvement, as well as long-term development strategies focusing on material–device–algorithm co-optimization and ecosystem establishment. Full article

With the continuous growth of data-intensive applications and artificial intelligence workloads, traditional dynamic random access memory (DRAM) is increasingly struggling to meet demands in terms of capacity scale, energy consumption constraints, and data retention after power failure. Consequently, non-volatile memory (NVM) has emerged as a crucial technology for bridging the gap between the memory and storage layers. However, due to inherent differences in write life, read–write performance variations, and consistency guarantee after failure, the systematic application of NVM still faces a series of challenges. Addressing these issues, this paper takes as its starting point the adaptation of medium characteristics and system design, and summarizes the research progress in aspects such as write optimization, consistency and security coordination mechanisms, data structure modification under hybrid memory architecture, and cross-layer resource collaboration. It also conducts an in-depth analysis of representative solutions and evaluation methods. The review results show that current research has shifted from improving a single performance bottleneck to multi-mechanism collaborative optimization. Various technical approaches have proven complementary in alleviating write amplification, enhancing persistence efficiency, and optimizing access patterns. This paper demonstrates that achieving stable and scalable application of NVM requires establishing a more systematic collaborative design concept between durability, security, and performance. As AI training workloads and big data analytics place increasing demands on memory bandwidth and persistence, the techniques surveyed here provide a foundational basis for next-generation memory-centric computing infrastructures. Full article

Wireless sensor systems can collect and share a large amount of data for different kinds of applications, but are also vulnerable to cyberattacks. The impact of cyberattacks on systems’ confidentiality, integrity, and availability can be mitigated by using authentication procedures and cryptographic algorithms. Authentication passwords and cryptographic keys may be stored in a non-volatile memory, which may be easily tampered with. Alternately, Physical Unclonable Functions (PUFs) can be adopted. They generate a chip’s unique fingerprint, by exploiting the randomness of process parameters’ variations occurring during chip fabrication, thus constituting a more secure alternative to the adoption of non-volatile memories for password storage. PUF reliability is of primary concern to guarantee a system’s availability. In this paper, the reliability of a Static Random Access Memory (SRAM)-based PUF implemented by a standard 32 nm CMOS technology is investigated, as a function of different operating conditions, such as noise, power supply voltage, and temperature, and considering different values of transistor conduction threshold voltages. The achieved results will show that transistor threshold voltage and noise are the operating conditions mostly affecting PUF reliability, while the impact of temperature variations is lower, and that of power supply variations is negligible. Full article

With the outstanding growth of Internet of Things (IoT) devices, security and power efficiency of integrated circuits can no longer be overlooked. Current approved standards for cryptographic algorithms are not suitable for constrained environments. In this context, the National Institute of Standards and Technology (NIST) started a lightweight cryptography (LWC) competition to develop new algorithm standards that can be fit into small devices. In 2023, NIST has decided to standardize the Ascon family for LWC. This algorithm has been designed to be more resilient to side-channel and fault-based analysis. Nonetheless, hardware implementations of Ascon have been broken by multiple statistical fault analysis and power analysis. These attacks have underlined the necessity to develop adapted countermeasures to side-channel and perturbation-based attacks. However, existing countermeasures are power and area consuming. In this article, we propose a new countermeasure for the Ascon cipher that does not significantly increase the area and power consumption. Our architecture relies on the nonvolatile feature of the Magnetic Tunnel Junction (MTJ) that is the single element of the emerging Magnetic Random Access Memories (MRAM). The proposed circuit removes the bias exploited by statistical attacks. In addition, we have duplicated and complemented the permutation of Ascon to enhance the power analysis robustness of the circuit. Besides the security aspect, our circuit can save current manipulated data, ensuring energy saving from 11% to 32.5% in case of power failure. The area overhead, compared to an unprotected circuit, is $\times 2.43$. Full article

The rapid advancement of technology, alongside state-of-the-art techniques is at an all-time high. However, this unprecedented growth of technological prowess also brings forth potential threats, as oftentimes the security encompassing these technologies is imperfect. Particularly within the automobile industry, the recent strides in technology have brought about increased complexity. A notable flaw lies in the CAN-FD protocol, which lacks robust security measures, making it vulnerable to data theft, injection, replay, and flood data attacks. With the rising complexity of in-vehicular networks and the widespread adoption of CAN-FD, the imperative to safeguard the protocol has never been more crucial. This paper aims to provide a comprehensive review of the existing in-vehicle communication protocol, CAN-FD. It explores existing security approaches designed to fortify CAN-FD, demonstrating multiple multi-layer solutions that leverage modern techniques including Physical Unclonable Function (PUF), Elliptical Curve Cryptography (ECC), Ethereum Blockchain, and Smart contracts. The paper highlights existing multi-layer security measures that offer minimal overhead, optimal performance, and robust security. Moreover, it identifies areas where these security measures fall short and discusses ongoing research along with suggestions for implementing software and hardware-level modifications. These proposed changes aim to streamline complexity, reduce overhead while ensuring forward compatibility. In essence, the methods outlined in this study are poised to excel in real-world applications, offering robust protection for the evolving landscape of in-vehicular communication systems. Full article

Current encryption technologies mostly rely on complex algorithms or difficult mathematical problems to improve security. Therefore, it is difficult for these encryption technologies to possess both high security and high efficiency, which are two properties that people desire. Trying to solve this dilemma, we built a new encryption technology, called configurable encryption technology (CET), based on the typical structure of reconfigurable quaternary logic operator (RQLO) that was invented in 2018. We designed the CET as a block cipher for symmetric encryption, where we use four 32-quit RQLO typical structures as the encryptor, decryptor, and two key derivation operators. Taking advantage of the reconfigurability of the RQLO typical structure, the CET can automatically reconfigure the keys and symbol substitution rules of the encryptor and decryptor after each encryption operation. We found that a chip containing about 70,000 transistors and 500 MB of nonvolatile memory could provide all the CET devices and generalized keys needed for any user’s lifetime, to implement a practical one-time pad encryption technology. We also developed a strategy to solve the current key distribution problem with prestored generalized key source data and on-site appointment codes. The CET is expected to provide a theoretical basis and core technology for using the RQLO to build a new cryptographic system with high security, fast encryption/decryption speed, and low manufacturing cost. Full article

Chemical analysis of hazardous surface contaminations, such as hazardous substances, explosives or illicit drugs, is an essential task in security, environmental and safety applications. This task is mostly based on the collection of particles with swabs, followed by thermal desorption into a vapor analyzer, usually a detector based on ion mobility spectrometry (IMS). While this methodology is well established for several civil applications, such as border control, it is still not efficient enough for various conditions, as in sampling rough and porous surfaces. Additionally, the process of thermal desorption is energetically inefficient, requires bulky hardware and introduces device contamination memory effects. Low-temperature plasma (LTP) has been demonstrated as an ionization and desorption source for sample preparation-free analysis, mostly at the inlet of a mass spectrometer analyzer, and in rare cases in conjunction with an ion mobility spectrometer. Herein, we demonstrate, for the first time, the operation of a simple, low cost, home-built LTP apparatus for desorbing non-volatile analytes from various porous surfaces into the inlet of a handheld IMS vapor analyzer. We show ion mobility spectra that originate from operating the LTP jet on porous surfaces such as asphalt and shoes, contaminated with model amine-containing organic compounds. The spectra are in good correlation with spectra measured for thermally desorbed species. We verify through LC-MS analysis of the collected vapors that the sampled species are not fragmented, and can thus be identified by commercial IMS detectors. Full article

Write-once-read-many-times (WORM) memory belonging to an important non-volatile memory type achieves the read-only state after the write operation and is used in the fields of data security storage widely. WORM memory has been developed based on a variety of materials. In recent years, halide perovskites have become the research hotspot material for this memory due to its excellent properties. Here, the all-inorganic CsPbBr₃ perovskite thin film was prepared on a FTO substrate by using a two-step method. The prepared CsPbBr₃ thin films have the characteristics of densely packed crystal grains and smooth surface. The device, having the FTO/CsPbBr₃/Al sandwich structure by evaporating the Al electrode onto the CsPbBr₃ thin film, represents the typical WORM behavior, with long data retention time (10⁴ s), a low operation voltage (2.1 V) and a low reading voltage (0.1 V). Additionally, the resistance transition mechanism of the resulting WORM devices was analyzed. Full article

Physical unclonable functions (PUFs) are gaining traction as an attractive alternative to generating and storing device keying material over traditional secure non-volatile memory (NVM) technologies. In this paper, we propose an engineered delay-based PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and present an analysis of the statistical quality of its bitstrings using data collected from a set of FPGAs subjected to extended industrial temperature-voltage environmental conditions. The SiRF PUF utilizes the Xilinx shift register primitive and an engineered network of logic gates that are designed to distribute signal paths over a wide region of the FPGA fabric using a MUXing scheme similar in principle to the shift-rows permutation function within the Advanced Encryption Standard algorithm. The shift register is utilized in a unique fashion to enable individual paths through a Xilinx 5-input LUT to be selected as a source of entropy by the challenge. The engineered logic gate network utilizes reconvergent-fanout as a means of adding entropy, eliminating bias and increasing uncertainty with respect to which paths are actually being timed and used in post-processing to produce the secret key or authentication bitstring. The SiRF PUF is a strong PUF build on top of a network with 10’s of millions of possible paths. Full article

In this work, we evaluate the resistive switching (RS) and synaptic characteristics of a fully transparent resistive random-access memory (T-RRAM) device based on indium-tin-oxide (ITO) electrodes. Here, we fabricated ITO/WO_X/ITO capacitor structure and incorporated DC-sputtered WO_X as the switching layer between the two ITO electrodes. The device shows approximately 77% (including the glass substrate) of optical transmittance in visible light and exhibits reliable bipolar switching behavior. The current-voltage (I–V) curve is divided into two types: partial and full curves affected by the magnitude of the positive voltage during the reset process. In the partial curve, we confirmed that the retention could be maintained for more than 10⁴ s and the endurance for more than 300 cycles could be stably secured. The switching mechanism based on the formation/rupture of the filament is further explained through the extra oxygen vacancies provided by the ITO electrodes. Finally, we examined the responsive potentiation and depression to check the synaptic characteristics of the device. We believe that the transparent WO_X-based RRAM could be a milestone for neuromorphic devices as well as future non-volatile transparent memory. Full article

Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache. Full article

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues. Full article

Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal. Full article

The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption. Full article