Search Results (84)

The Ring Oscillator Physical Unclonable Function (RO-PUF) is a hardware security innovation that creates a secure and distinct identifier by utilizing the special physical properties of ring oscillators. Their unique response, low hardware overhead, and difficulty of reproduction are some of the security benefits that make them valuable in safe authentication systems. Numerous developments, such as temperature adjustment methods, aging mitigation, and better architecture and layout, have been created to increase its security, dependability, and efficiency. However, achieving the sacrifice metric makes it challenging to implement with additional complex circuits. This work focuses on stability improvement in terms of the reliability of the RO-PUF in enhanced challenge and response (CRP) by exploiting existing on-chip hard processors. This work establishes only ROs and their counters inside the chip. The built-in microprocessor performs the remaining process using the intermediary process of a Q factor and new frequency mapping. As a result, the reliability improves significantly to 95.8% compared to previous methods. The proper use of resources due to the limitation of on-chip resources has been emphasized by considering that a hard processor exists inside the new FPGA chip. Full article

The residual magnetism of the iron core of power transformers can cause an excitation inrush current, posing a threat to the safe and stable operation of the power grid. This paper proposes a transformer remanence measurement method based on a demagnetization hysteresis loop to address the problems of large errors, complex operation, and poor universality in existing remanence measurement methods. This method is designed for off-grid transformers to avoid potential interference to the power grid caused by current pulses during the measurement process. This method constructs an RLC oscillation circuit that utilizes capacitor energy storage and iron core magnetic field energy conversion, combined with the dynamic characteristics of hysteresis loops, to achieve accurate measurement of residual magnetism and synchronous demagnetization. The effectiveness of this method has been verified through residual magnetism measurement experiments on ring transformers and large converter transformers, and it can be applied in specific engineering practice operations. Theoretical analysis shows that the charging range of energy storage capacitors is affected by the hysteresis characteristics of the iron core and the saturation magnetic flux, and the residual magnetization value can be directly calculated based on the difference in the intersection point of the longitudinal axis of the demagnetization hysteresis loop. Simulation and experimental results show that the measurement error of the proposed method is less than 5%—significantly better than traditional methods. This method does not require complex control strategies, has high precision and efficiency, and can provide reliable technical support for residual magnetism detection and suppression of off-grid power transformers. Full article

In this paper, a novel approach to symbolic regression using Kolmogorov–Arnold Networks (KAN) for developing gray-box Simulation Program with Integrated Circuit Emphasis models of generic transistors is proposed. Unlike traditional black-box models, such as artificial neural networks, (ANN), the developed KAN-based model enhances interpretability by generating explicit mathematical expressions while maintaining high accuracy in device modeling. By combining the computational efficiency of neural network approaches with the transparency of formula-based modeling, the SPICE model generation is significantly accelerated, thereby improving the efficiency of the design technology co-optimization (DTCO) process. The experimental results demonstrate that the expressions derived from the KAN model accurately represent the current–voltage (I–V) characteristics of the BSIM–CMG compact model and provide nearly symmetric results. To further validate the effectiveness and versatility of the approach, we embedded the trained I–V KAN model into a 12 nm FinFET SPICE model and performed 11-stage ring oscillator (RO) simulations. The results indicate that the KAN-based SPICE model achieves accuracy comparable to the original 12 nm FinFET SPICE model, demonstrating its potential to streamline device modeling for advanced technology nodes. Full article

This paper presents a novel passive floating memristor emulator that operates without an external DC bias, leveraging the DTMOS technique. The design comprises only four MOSFETs and eliminates the need for external capacitors. The emulator achieves a high operating frequency of around 250 MHz and consumes zero static power. A comprehensive analysis and simulation, conducted using 180 nm CMOS technology, validates the circuit’s performance. The versatility and effectiveness of the proposed emulator are demonstrated through its application in various circuits, including logic gates, a ring oscillator, and analog filters, highlighting its potential for diverse low-power, high-frequency applications. The proposed emulator provides a compact, efficient, and integrable solution for nanoelectronic circuit designs. Full article

The coupling capacitor of the MTP cell used in this paper is an NCAP-type capacitor that has only a source contact, and the layout size of the unit cell is 6.184 μm × 6.295 μm (=38.93 μm²), which is 0.44% smaller than the MTP cell that uses the coupling capacitor of the conventional NMOS transistor type that has both a source contact and a drain contact. In addition, a 4 Kb MTP IP with a built-in ECC function using an extended Hamming code capable of single-error correction and double-error detection was designed for safety considerations. In this paper, a new test algorithm is proposed to test whether the ECC function operates normally in the MTP IP with a built-in ECC function, and it is confirmed through a test using logic tester equipment that the output data DOUT[7:0] and the error flag ERROR_FLAG[1:0] are exactly the same in the cases of no error, a single-bit error, and a double-bit error. In addition, by sharing a current-controlled ring oscillator circuit that uses a current-starved inverter in the VPP, VNN, and VNNL charge pumping circuits that share a single ring oscillator in the erase and program operation modes of the MTP IP and using the regulated VPVR as power, the pumping capacitor size is reduced, and a new technology to reduce ripple voltage variation is proposed. Meanwhile, in the VNN level detector circuit that detects whether the VNN has reached the target voltage, a folded-cascode CMOS OP-AMP whose output swing voltage is almost VDD is used instead of a differential amplifier circuit with a PMOS differential input pair to ensure that normal VNN level detection operation occurs. Full article

Portable and wearable sensor systems implemented in the paradigm of the Internet of Things (IoT) are part of our daily activities as well as commercial and industrial products. The connection of measurement devices has led to not only a sharp increase in information sharing, but also to the frequency of cyber-attacks, in which system vulnerabilities are exploited to steal confidential information, corrupt data, or even make the system unavailable. Physical unclonable function (PUF)-based devices exploit the inherent randomness introduced during device manufacturing to create a unique fingerprint. They are widely used to generate passwords and cryptographic keys to mitigate security issues in IoT applications. Among the existing different PUF structures, ring oscillator (RO)-based PUF devices are very popular due to their simple structure and their potential easy integration onto chips. In this paper, the possibility of increasing the number of challenge–response pairs (CRPs) of RO-based PUF devices by measuring two different parameters (the oscillation frequency and the duty cycle) is investigated. The results achieved by the performed circuit level simulations and experimental measurements show that these two parameters feature a weak correlation. The proposed PUF device can be used to increase the number of CRPs to improve device security while achieving a high uniqueness value (49.77%). Full article

The primary functions of an energy harvesting system include the harvesting, transformation, management, and storage of energy. Until now, various types of energy, with different power levels, have been harvested and stored by the energy harvesting system. In low-power scenarios, such as microwaves, sound, friction, and pressure, a specific low-power energy harvesting system is required. Due to the absence of an external power supply in such systems, cold-start circuits play a crucial role in igniting the low-power energy harvesting system, ensuring a reliable start-up from the initial state. This paper reviews the categorization and characteristics of energy harvesting systems, with a focus on the design and performance parameters of cold-start circuits. A tabular comparison of existing cold-start strategies is presented herein. The study demonstrates that resonance-based integrated cold-start methods offer significant advantages in terms of conversion efficiency and dynamic range, while ring oscillator-based integrated cold-start methods achieve the lowest start-up voltage. Additionally, the paper discusses the challenges of self-starting and future research directions, highlighting the potential role of emerging technologies, such as artificial intelligence (AI) and neural networks, in optimizing the design of energy harvesting systems. Full article

Ultra-low-voltage design brings considerable outcomes in power reduction and energy efficiency improvement at the cost of performance degradation and uncertainty. Conventional standard cell design methodology cannot guarantee optimal performance for subthreshold operations due to the lack of consideration of process variation. In this paper, an effective subthreshold cell sizing method is proposed to minimize the worst-case propagation delay by deriving the optimal pMOS-to-nMOS width ratio (β) analytically, which reveals the relation between the minimal worst-case delay and the process parameters and provides distinct guidance for standard cell library design. The proposed method demonstrated good agreement with the Monte Carlo SPICE simulation results and was validated at the cell level and the circuit level. At the cell level, the logic cells designed with the proposed method show at least 8.6% and 7.4% improvement, on average, for worst-case delay and energy-delay product (EDP), respectively, with an additional 3.2% energy overhead compared to the prior approaches. At the circuit level, the proposed method improves the worst-case performance and worst-case EDP of the ring oscillator by at least 15.5% and 15.0%, respectively, with a 0.9% energy penalty. Moreover, the ISCAS’89 and OpenCores circuits synthesized with the optimized cells achieve at least 6.6% worst-case performance enhancement, 6.9% power reduction, and 9.4% area saving. Full article

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (tr_pbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (T_SD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (C_gg) as the T_SD increases. A higher TIS height prevents the C_gg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (C_L) increases. As C_L increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling tr_pbt and improving electro-thermal performance in sub-3 nm node NSFETs. Full article

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC. Full article

Statistical simulation is a necessary step in integrated circuit design since it provides a realistic picture of the circuit’s behavior in the presence of manufacturing process variations. When some of the circuit components lack an accurate analytical model, as is often the case for emerging semiconductor devices or ones working at cryogenic temperatures, an approximation model is necessary. Such models are usually based on a lookup table or artificial neural network individually fitted to measurement data. If the number of devices available for measurement is limited, so is the number of approximation model instances, which renders impossible a reliable statistical circuit simulation. Approximation models using the device’s physical parameters as inputs have been reported in the literature but are only useful if the end user knows the statistical distributions of those parameters, which is not always the case. The solution proposed in this work uses a type of artificial neural network called the variational autoencoder that, when exposed to a small sample of I-V curves under process variations, captures their essential features and subsequently generates an arbitrary number of similarly disturbed curves. No knowledge of the underlying physical sources of these variations is required. The proposed generative model trained on as few as 20 instances of a MOSFET is shown to precisely reproduce the period and power consumption distributions of a ring oscillator built with these MOSFETs. Full article

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm². Full article

Physical Unclonable Functions are security primitives that exploit the variation in integrated circuits’ manufacturing process, and, as a result, each instance processes applied stimuli differently. This feature can be used to provide a unique fingerprint of the electronic device, or as an interesting alternative to classic key storage methods. Due to their nature, they are often considered an element of the Internet of Things nodes. However, their application heavily depends on resource consumption. Lightweight architectures are proposed in the literature but are technology-dependent or still introduce significant hardware overhead. This paper presents a lightweight, Strong PUF based on ring oscillator architecture, which offers small hardware overhead and sufficient security levels for resource-constrained Internet of Things devices. The PUF design utilizes a Linear Feedback Shift Register-based scramble module to generate many challenge–response pairs from a small number of ring oscillators and a control module to manage the response generation process. The proposed PUF can be used as a Weak PUF for key generation or a Strong PUF for device authentication. Full article

With the development of the photovoltaic industry; there will be an increasing demand for efficient, high-power density, and low-cost grid interface converters. Compared with two-level inverters, multilevel inverters have the following advantages: (1) lower device voltage ratings; (2) better output filtering spectrum; (3) lower electromagnetic interference (EMI) noise; and (4) higher switching speed capability. However, the complex switching circuit of the multilevel inverter will bring more parasitic inductance, resulting in severe switching overvoltage (ringing). Especially in order to reduce the cost of the inverter, using the long-loop modulation mode, the commutation loop will introduce more parasitic inductance, which will make the overvoltage more serious. Consider that commonly used overvoltage absorption schemes are effective only for overvoltage or suppression of oscillations. Therefore, a new overvoltage absorption circuit is proposed in this paper, which can not only alleviate the overvoltage and ringing phenomena but also suppress the effect of voltage jumps during low-frequency switching on high-frequency input voltage. This overvoltage absorption circuit is characterized by low overvoltage, fast ringing damping, and minimum capacitance. Experiments and simulations are conducted to verify the effectiveness of this overvoltage absorption circuit using a three-level ANPC inverter as a prototype. The results show that the proposed overvoltage absorption circuit can significantly reduce the overvoltage level, shorten the oscillation time, and reduce the voltage difference between the upper and lower DC bus capacitors. Full article

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions ($V_{nom}\le V_{stress}\le 1.3V_{nom}$ and $25{}^{°}\mathrm{C}\le T_{stress}\le 115{}^{°}\mathrm{C}$) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between $50\%$ and $70\%$ of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of $1\%$, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA. Full article