Search Results (182)

Embedded systems increasingly require on-device deep learning, yet their processors must simultaneously handle real-time sensing, networking administration, and data control. Existing Field-Programmable Gate Array (FPGA) accelerators typically target peak per-operator throughput without addressing concurrent execution demands of real-time embedded platforms. This paper presents a systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted. Unlike traditional accelerators optimized for peak per-operator speed, this design prioritizes asynchronous co-executionbetween the processing system (PS, the dual-core Cortex-A9) and the programmable logic (PL): The PL performs tiled matrix multiplication, while the PS executes preprocessing, orchestration, and I/O data concurrently, increasing effective end-to-end throughput regardless of the relative isolated performance of CPU and FPGA. The proposed module includes high-level-synthesis (HLS)-based matrix multiplication, activation functions, and Advanced eXtensible Interface (AXI)-Stream Direct Memory Access (DMA) interfaces, wrapped as custom PyTorch kernels under the PetaLinux operating system. The results obtained on the PYNQ-Z2 board show that, once the DMA transfer time is included in the measurement, the FPGA path does not surpass Cortex-A9 in isolated per-operator latencies across the evaluated range; the benefit lies instead in delegating the matrix compute to the fabric at low incremental power while the host CPU cores stay available for concurrent tasks. A concurrent workload sweep across matrix sizes from $8\times 8$ to $256\times 256$ confirms that the co-execution mode sustains 98–99% of available PS compute throughput compared with a constant ≈50% in single-core blocking mode; the difference is statistically significant for all evaluated sizes (see Mann–Whitney U: $U=25$, $p=3.97\times {10}^{-3}$, perfect discrimination, $n=5$). A fair dual-core CPU-only baseline attains comparable PS availability, so this figure reflects the dual-core scheduling that co-execution enables rather than a per-operator advantage of the fabric; the accelerator’s distinct role is to perform the matrix arithmetic off the general-purpose cores at low incremental power. The design occupies only 8% of available look-up tables (LUTs) and 5% of digital signal processing (DSP) blocks, maintains 1.69 W power with a junction temperature of 44.5 °C, and achieves 96.10% MNIST accuracy under fixed-point arithmetic. Full article

Permanent magnet synchronous motors (PMSMs) used in hybrid shunting locomotive traction systems operate under complex conditions, and their electrical parameters may vary with temperature rise, load disturbance and magnetic saturation. To improve online parameter tracking under such conditions, this paper investigates a forgetting-factor recursive least squares (FFRLS)-based identification method for stator resistance, stator inductance and permanent magnet flux linkage. The main contribution lies in the traction-oriented formulation of the identification model, DSP28335-based real-time implementation, and simulation/experimental validation of three-parameter online tracking. Simulation results show that the proposed method can track the three key parameters under selected perturbation conditions. The experimental results provide algorithm-level evidence for the real-time implementation and three-parameter tracking capability of the proposed method on a scaled-down PMSM platform, thereby establishing a basis for subsequent full-scale validation and studies on traction-control robustness and energy-efficiency optimization. Full article

This paper presents the design, digital implementation, and experimental validation of a new 50 W scaled prototype of a quadratic buck converter (48 V to 5 V, 10 A) controlled by a finite control set model predictive control (FCS-MPC) strategy. The converter utilizes its quadratic step-down topology to achieve high voltage conversion gain without extreme duty cycles, making it suitable for low-power applications requiring precise voltage regulation. The proposed methodology encompasses the theoretical design of the power stage, the development of the experimental prototype based on a C2000 Digital Signal Processor DSP, and a comparative performance assessment between the proposed FCS-MPC and a conventionally tuned PD controller. An iterative tuning and real-time validation process is employed to optimize both the converter parameters and the control law, ensuring closed-loop stability and enhanced dynamic response under line and load disturbances. The experimental results demonstrate that the FCS-MPC strategy significantly outperforms the PD controller in terms of output voltage regulation, settling time (4.2 s vs. 5 ms), and disturbance rejection (<2 ms recovery). The main contribution of this work is the construction of a new scaled prototype and the experimental validation of a predictive control strategy for a high-gain DC–DC converter, positioning the FCS-MPC-controlled quadratic buck converter as a viable solution for modern applications demanding high energy efficiency and robustness. Full article

Field-oriented control and direct torque control of induction-motor (IM) drives, and conventional finite-control-set model predictive control (FCS-MPC), all depend explicitly on machine parameters that drift with temperature and saturation, degrading current quality and, for the predictive case, even threatening closed-loop stability. This paper develops a parameter-robust, weighting-factor-less model-free predictive current control (MFPCC) for IM drives, in which the lumped disturbance of an ultra-local model is reconstructed online by a linear extended-state observer (ESO) and the inverter state is chosen by a current-only cost function. A two-step ($k+2$) prediction horizon is utilized to explicitly compensate for the one-sample microprocessor computation-and-actuation delay inherent to digital predictive control. The speed loop is governed by a model-free intelligent-proportional controller; thus, no proportional-integral current regulator and no machine parameter appear in the control path, with the single exception of the ultra-local model design gain $\mathsf{\alpha }$, which is fixed at the nominal input gain $1/\left(\mathsf{\sigma } {\mathrm{L}}_{\mathrm{s}}\right)$ to establish parameter robustness. A comparative disturbance-observer study shows that the finite-difference estimator amplifies measurement noise and that an adaptive super-twisting observer cannot track the fast back electromotive force (back-EMF)-dominated lumped term of the IM at practical sampling rates, whereas the ESO tracks it faithfully (correlation 0.98). Under full inverter non-idealities (3 µs dead-time, 12-bit quantization, 50 mA offset, and 3% DC-link ripple), the proposed scheme attains 3.2% stator-current THD, matching an accurately tuned model-based FCS-MPC (3.9%) and significantly outperforming the finite-difference baseline (11.3%) while using none of the five machine parameters. Closed-loop stability and robust tracking are confirmed via a 50-run Monte-Carlo study, while a DSP timing estimate confirms real-time feasibility. Full article

This paper proposes a robust controller combined with extension theory (ET) and applies it to the speed control of a brushless DC motor (BLDCM) drive system. The controller uses the motor’s speed error and its rate of change as characteristic values to establish ET classical domain and neighborhood domain models. Appropriate weights are set, and then the real-time speed error and its rate of change are used as input to calculate their correlation function with the ET model. The system can automatically determine the optimal proportional–integral (P-I) parameters, enabling the controller to perform real-time adaptive adjustments in response to the system’s nonlinear and time-varying characteristics. This overcomes the shortcomings of traditional fixed-gain P-I controllers with insufficient response during speed tracking and load changes. Furthermore, the system is equipped with a synchronous reference frame-based sliding mode observer (SRF-SMO) to achieve speed sensorless control. A power factor correction (PFC) circuit and over-voltage and over-current protection circuits are added to the drive system to improve the power quality at the power source and the operational safety of the drive system. To verify the effectiveness of the proposed controller, this paper implements the control algorithm on a 32-bit floating-point digital signal processor (DSP) TMS320F28335 using PSIM SimCoder’s automatic code generation technology. The experimental results show that compared to three different sliding mode controllers (SMCs) designed with constant speed reaching law (CSRL), exponential reaching law (ERL), and extension theory combined with exponential reaching law (ETERL), the proposed extension theory robust speed controller exhibits superior control performance in speed command tracking and load regulation response. This demonstrates that the proposed robust controller not only possesses stronger anti-disturbance capability, smaller speed drop, and shorter recovery time but additionally, the power factor of the drive system under rated load can reach above 0.98, and the protection mechanism can be activated under both over-voltage and over-current conditions, allowing the drive system to operate safely. Full article

This paper proposes a practical heuristic engineering strategy for automated capacity allocation in a multifunctional parallel active power filter (PAPF) that simultaneously provides harmonic and reactive power compensation. Unlike theoretically optimal methods, our approach prioritizes real-time feasibility and ease of implementation. The key features are: (1) an event-triggered, closed-loop THD-feedback mechanism that dynamically recalculates the minimum active power required for harmonic compensation only when the load harmonic content changes, avoiding periodic computational waste; (2) a strict priority handling that guarantees grid current THD below 5% (IEEE-519 compliant) under all operating conditions, even when capacity is severely insufficient; (3) a closed-loop transition mechanism that uses measured grid current THD and remaining capacity as feedback inputs to continuously adapt power distribution. The proposed rule-based strategy does not claim theoretical optimality but provides a verifiable, ready-to-implement solution with experimental evidence. Simulation and experimental results on a three-level NPC PAPF prototype demonstrate that the strategy maintains grid current THD below 5% while keeping the apparent power within the rated capacity, achieving near-optimal reactive compensation (92–96% of the optimum) without iterative optimization. The experimental validation includes efficiency measurements, switching-loss estimation, DSP timing analysis, and robustness tests under grid disturbances. Future work will extend the concept to multi-inverter systems using multi-objective optimization and AI-based allocation. Full article

Objectives: Noninvasive prenatal testing relies on the analysis of total cell-free DNA (cfDNA) in maternal plasma, where fetal-derived DNA constitutes only a minor fraction. This study aimed to preliminarily compare a modified TPY cfDNA extraction protocol with two commercial extraction kits for the downstream detection of Y-chromosome-specific markers in pregnancies carrying male fetuses. Methods: Plasma samples were obtained from 52 singleton pregnancies between 10 and 30 weeks of gestation with male fetal sex confirmed by ultrasonography. Total cfDNA was extracted from aliquots of the same maternal plasma samples using the modified TPY protocol, the QIAamp DSP Virus Kit, and the MagMAX™ Cell-Free DNA Isolation Kit. Quantitative real-time PCR was performed for the Y-chromosome-specific markers SRY and DYS14. At the same time, GLO was used as a reference marker to reflect the total cfDNA background. Extraction performance was assessed primarily using total cfDNA concentration and Ct values obtained from amplification of fetal-specific Y-chromosome markers. Results: Total cfDNA concentrations varied among the extraction methods, with the commercial kits yielding higher total cfDNA concentrations than the modified TPY protocol. In contrast, the TPY protocol yielded slightly lower mean Ct values for SRY and DYS14 than the commercial kits. SRY and DYS14 amplification was detected in 90.4% and 94.2% of samples, respectively. However, these Ct differences should be interpreted cautiously because fetal fraction, maternal DNA contamination, extraction recovery, and fragment size distribution were not directly measured. Conclusions: The modified TPY protocol showed preliminary technical feasibility for extracting total cfDNA from maternal plasma and enabling downstream amplification of Y-chromosome-specific markers in male pregnancies. Nevertheless, the observed lower Ct values do not establish selective fetal DNA enrichment, reduced maternal DNA contamination, or clinical superiority over commercial methods. Further analytical validation using standardized fetal fraction measurement, recovery efficiency testing, fragment size analysis, fetal-to-maternal DNA ratio assessment, and larger cohorts including both male and female pregnancies is required before broader clinical applicability can be determined. Full article

High-performance control of surface-mounted permanent magnet synchronous motors (SPMSMs) is critical for unmanned aerial vehicle (UAV) rotor servo systems, which demand fast dynamic response, high steady-state accuracy, and strong robustness against complex disturbances. However, conventional sliding mode control (SMC) methods often suffer from inherent issues like integral windup, persistent chattering, and sensitivity to parameter variations, limiting their effectiveness in such challenging applications. To address these limitations, this paper proposes a novel composite control strategy. The method integrates an improved terminal integral sliding mode controller (ITISMC) with an adaptive super-twisting reaching law (ADSTA) and a terminal integral sliding mode observer (TISMO). The key innovations include: (1) a redesigned sliding surface incorporating a smooth nonlinear function to suppress chattering and a variable-gain integral term to mitigate integral windup; (2) an adaptive reaching law that dynamically adjusts its gains based on the system state to balance convergence speed and chattering suppression; and (3) a disturbance observer that provides real-time estimation and feedforward compensation of total disturbances, significantly enhancing robustness. The proposed ITISMC-ADSTA-TISMO strategy was implemented and validated on a TMS320F28379D DSP-based experimental platform. Comparative results demonstrate its superiority over benchmark methods (e.g., SMC-STA). Key achievements include a rapid no-load startup time of 0.45 s, high steady-state precision with speed fluctuations suppressed to only 3 rpm, and superior disturbance rejection capability under sudden load changes, sinusoidal disturbances, and parameter perturbations. The method also yields favorable q-axis current response. These results confirm that the proposed strategy offers a high-performance, practical solution for advanced UAV servo control systems. Full article

Real-time deployment of modern object-detection networks on edge devices is challenging because of limited compute resources, external-memory bandwidth, and strict power constraints. To address these issues, this paper presents a host–FPGA collaborative accelerator for quantized YOLOv5n on a Xilinx Zynq-7100 platform. The proposed design includes a modular multi-operator neural processing unit supporting seven atomic operators, a Dual-Multiply Packing (DMP) scheme to improve DSP48E1-based INT8 convolution density, a cache–compute–cache dataflow with global ping-pong buffering to overlap DMA transfers and computation, and a Multi-Quantization Domain Alignment (MQDA) pipeline to preserve accuracy at Add and Cat fusion nodes. Implemented at 200 MHz, the prototype achieves 24.617 ms FPGA-side forward-inference latency, 36.686 ms end-to-end single-frame latency, 27.2 FPS system-level performance, 182.8 GOPS equivalent throughput, and 8.536 W on-chip power consumption, corresponding to 21.42 GOPS/W. Experimental results also show that INT8 quantization causes only limited accuracy degradation, while MQDA improves quantized detection accuracy by reducing cross-domain fusion error. These results demonstrate that the proposed architecture provides an effective balance among throughput, energy efficiency, hardware cost, and quantized accuracy for real-time edge object detection. Full article

Many machine learning and deep learning algorithms based on Artificial Neural Networks (ANNs) have been implemented on software platforms for handwritten digit and character recognition. However, an ANN is difficult to deploy on an embedded platform based on a Central Processing Unit (CPU) because of its large computation, complex structure, and frequent memory access. However, Field Programmable Gate Array (FPGA) devices facilitate this task and offer the capability to design fully customizable hardware architectures. Additionally, they provide high flexibility and high parallel computations based on parallel processing techniques, and they contain sufficient on-chip Digital Signal Processing (DSP) blocks useful for complicated multiplications. In this paper, we present a detailed FPGA-based implementation of a handwritten digit recognition system based on a Multi-Layer Perceptron (MLP) model. The internal modules of the network are designed using the VHSIC Hardware Description Language (VHDL) to achieve a high-level optimization on the hardware platform, and the functionality is simulated and tested using Vivado ISIM Tools. The system has been characterized to reach acceptable performance compared to previous approaches. After implementing the whole neural network on a Xilinx Pynq-Z2 board, it occupies in the device 20758 LUTs, 4426 FFs, 3.50 blocks of random-access memory (BRAM), and 42 DSPs. It reaches an execution time of 2.192 µs to recognize a handwritten number, while consuming only 0.36 Watts, and it achieves a classification accuracy of 97%. Additionally, the proposed architecture can be easily scaled on different FPGA devices thanks to its regularity. Therefore, it offers more portability of the architecture and can be used on different real embedded applications. Full article

Real-time binaural beat synthesis in dynamic acoustic environments is challenged by carrier non-stationarity, interaural phase discontinuities, and processing delay in conventional digital signal processing pipelines. This study proposes a predictive dual-stage neural framework for phase-coherent auditory synthesis under non-stationary acoustic conditions. The framework decouples real-time carrier estimation from phase-coherent signal generation through two specialized modules. An intelligent acoustic sensing module (AI-1) estimates time-varying carrier information across harmonic, fluctuating, and broadband acoustic profiles using a causal neural front-end with an adaptive confidence-driven strategy. A predictive phase-coherent generator (AI-2) then forecasts short-horizon carrier trajectories and drives a discrete-time phase accumulator to maintain continuous phase evolution during binaural beat embedding. Objective evaluation under multiple acoustic profiles and noise conditions shows that the proposed framework maintains strong phase continuity, with a Phase Coherence Factor greater than 0.91, and low artifact levels, with a Signal-to-Artifact Ratio greater than 39.8 dB, under the evaluated conditions. Additional comparisons with conventional DSP baselines, stronger classical F0 estimators, a lightweight neural F0 tracker, and component-wise ablation variants further demonstrate that the performance improvement arises from the combination of adaptive carrier estimation and predictive phase-coherent actuation, rather than from carrier estimation alone. Hardware profiling shows a combined INT8 inference time of 2.4 ms per frame on a resource-constrained Raspberry Pi Zero 2W-class edge device. Importantly, this inference time and the sub-millisecond phase-accumulator resolution should not be interpreted as sub-millisecond end-to-end physical audio latency. The complete system still includes buffering, framing, neural inference, and output processing delay; the proposed method instead reduces effective phase-boundary misalignment through short-horizon predictive compensation. These results support the proposed framework as a lightweight engineering solution for real-time phase-continuous auditory synthesis in dynamic listening environments. The reported PCF and SAR values should be interpreted as signal-level indicators of phase continuity and artifact suppression, rather than as evidence of listener comfort, perceptual preference, or neurophysiological efficacy. Full article

With the rapid deployment of deep neural networks (DNNs) on edge devices, traditional hardware accelerators face significant challenges in terms of data security, computational redundancy caused by sparsity, and uneven utilization of on-chip resources. This paper proposes SaE-FPGA, a secure and efficient DNN accelerator designed specifically for edge FPGA platforms. The architecture introduces three core innovations: (1) Hash-Bypass Processing Unit (HBPU): Integrating a high-speed SHA-256 hardware engine with a hash-sparse bitmap mechanism, it enables real-time data integrity verification within a single clock cycle while skipping computations for redundant zero-value data. (2) Flexible Mixed-Precision Processing Element (FMP): By reconfiguring idle BRAM and LUT resources into an active lookup table multiplication engine, it overcomes the physical bit-width limitations of DSP blocks and supports INT8/INT6/INT4 mixed-precision multiplication. (3) Multi-mode Reconfigurable Streaming Frame (MRSF): A sparse-aware, elastic load balancing and data routing mechanism designed to mask long memory access latencies and ensure high hardware resource utilization. Experimental results on the Zynq 7045 platform demonstrate that SaE-FPGA reduces redundant computations by 23.2% while maintaining high precision and minimizing precision loss. The system effectively mitigates the risk of physical tampering. When tested on ResNet-50, it achieved a 27.2% improvement in energy efficiency and a 2.97× speedup compared to DSP-based FPGA solutions. Furthermore, by fully exploiting the hybrid BRAM-LUT and DSP configuration, the proposed accelerator achieves a remarkable peak throughput of 782.4 GOPS. Full article

Real-time Direction of Arrival (DOA) estimation demands high computational throughput and numerical precision. Consequently, dedicated hardware accelerators are essential. This paper presents an architecture to accelerate the MUSIC algorithm using an improved complex bilateral Jacobi eigenvalue decomposition (EVD). First, we design a triangular systolic array for Hermitian matrices. It employs an output-stationary dataflow to enable efficient parallel covariance computation. Second, we propose an enhanced EVD algorithm. It replaces CORDIC approximations with direct analytical rotations. This significantly improves numerical stability and accuracy. Third, we introduce hardware optimizations. These include unit reuse, integrated termination conditions, and pre-stored steering vectors. These measures reduce resource consumption while maintaining full functionality. Experiments on a Xilinx Virtex-6 platform validate the design. The architecture achieves a root mean square error (RMSE) below $0.24°$ with 300 snapshots. Processing latency is only 76.17 µs. The design utilizes 10,775 LUTs and 73 DSP slices. This work balances accuracy, speed, and efficiency. It offers a practical solution for real-time, high-precision DOA systems. Full article

This paper presents a novel integration of quadrature amplitude modulation (QAM)-based fast optical orthogonal frequency-division multiplexing (F-OFDM) with machine learning (ML)-based equalization in spatial division multiplexing (SDM) applications, using few-mode fibers (FMFs). The FMFs support four LP modes, resulting in a total of 12 orthogonal modes, each accommodating two polarizations. A digital multiple-input multiple-output channel equalizer is employed at the receiver’s digital signal processing (DSP) unit to effectively mitigate channel crosstalk. The study harnesses supervised ML-DSP techniques, in particular recurrent neural networks (RNNs) and deep neural networks (DNNs), achieving substantial reductions in bit error rates (BERs). In addition, higher-complexity architectures, namely convolutional neural networks (CNNs) and long short-term memory (LSTM) networks, are evaluated to assess the impact of advanced spatial and temporal feature extraction. It is shown that F-OFDM demonstrates superior performance over conventional optical OFDM, particularly when supported by ML techniques. Simulation results reveal that RNNs achieve a BER of 0.0019 over 15 km at 12 Gbaud (worst-case selected channel), showcasing a remarkable 52.5% improvement compared to linear equalization. DNNs achieve a BER of 0.0025, reflecting a 37.5% enhancement. While RNNs perform better, their computational demands pose challenges for real-time applications, and the more complex models (CNN and LSTM) do not provide additional performance gains. The paper also explores cyclic prefix management and subcarrier number strategies in F-OFDM to optimize performance, paving the way for future advancements in SDM networks. Full article

Viticulture is highly vulnerable to weather variability and climate change. Growers increasingly face risks associated with extreme weather events, water scarcity, and emerging pests and diseases. To address these challenges, this study presents the development and implementation of the first operational digital decision support platform (DSP) tailored to Montenegrin vineyards within the MONTEVITIS project. The platform integrates IoT sensor data, national meteorological records and high-resolution global climate datasets to provide real-time monitoring and climate projections for vineyard management. The system was piloted in four vineyards representing diverse microclimatic and soil conditions of Montenegro. Key functionalities include phenology, irrigation and disease alerts supported by a user-friendly dashboard, map-based visualisation tools and data export functions. The pilot deployment demonstrated that combining heterogeneous data streams increases the reliability of outputs and enables timely, site-specific recommendations. Challenges identified during implementation include connectivity limitations, gaps in data and variable levels of digital expertise among growers; however, lessons learned point to the importance of continuous stakeholder engagement and institutional support for sustained use. The MONTEVITIS experience demonstrates how digital agriculture tools can bridge tradition and innovation in viticulture. By fostering collaboration between growers, researchers and policy makers, the platform enables adaptive strategies for climate resilience and sustainable vineyard management. Although the platform has been successfully deployed and tested under pilot conditions, a comprehensive long-term validation of its performance and impact on vineyard decision-making remains part of ongoing future work. Full article