Search Results (154)

Edge detection is a key building block in real-time image-processing applications such as drone-based infrastructure inspection, autonomous navigation, and remote sensing. However, its computational cost remains a challenge for resource-constrained embedded systems. This work presents a hardware-accelerated edge detection architecture based on a homogeneous 2D-mesh Network-on-Chip (NoC) integrating systolic arrays to efficiently perform the convolution operations required by the Sobel filter. The proposed architecture was first developed and validated as a 3 × 3 mesh prototype on FPGA (Xilinx Zynq-7000, Zynq-7010, XC7Z010-CLG400A, Zybo board, utilizing 26,112 LUTs, 24,851 flip-flops, and 162 DSP blocks), achieving a throughput of 8.8 Gb/s with a power consumption of 0.79 W at 100 MHz. Building upon this validated prototype, a reduced 2 × 2 node cluster with 14-bit word width was subsequently synthesized at the physical level as a proof-of-concept using the OpenLane RTL-to-GDSII open-source flow targeting the SkyWater 130 nm PDK (sky130A). Post-layout analysis confirms the manufacturability of the design, with a total power consumption of 378 mW and compliance with timing constraints, demonstrating the feasibility of mapping the proposed architecture to silicon and its suitability for drone-based infrastructure monitoring applications. Full article

This work introduces a logic resource-efficient Artificial Neural Network (ANN) controller for embedded control applications on low-density Field-Programmable Gate Array (FPGA) platforms. The proposed design relies on 32-bit fixed-point arithmetic and incorporates an online learning mechanism, enabling the controller to adapt to system variations while maintaining low hardware complexity. Unlike conventional artificial intelligence solutions that require high-performance processors or Graphics Processing Units (GPUs), the proposed approach targets platforms with limited logic, memory, and computational resources. The ANN controller was described using a Hardware Description Language (HDL) and validated via cosimulation between ModelSim and Simulink. A practical comparison was also made between Proportional-Integral-Derivative (PID) control and an ANN for motor position control. The results confirm that the architecture efficiently utilizes FPGA resources, consuming approximately 50% of the available Digital Signal Processor (DSP) units, less than 40% of logic cells, and only 6% of embedded memory blocks. Owing to its modular design, the architecture is inherently scalable, allowing additional inputs or hidden-layer neurons to be incorporated with minimal impact on overall resource usage. Additionally, the computational latency can be precisely determined and scales with $(16n+39)m+31$ clock cycles, enabling precise timing analysis and facilitating integration into real-time embedded control systems. Full article

Ultra-high sampling rates in coherent optical front-ends increasingly exceed the processing capabilities of real-time baseband processors, creating a bottleneck in coherent free-space optical communication systems. We propose a unified state-space framework to systematically parallelize digital signal processing (DSP) algorithms. This approach transforms an algorithm’s transfer function into a state-space representation from which a parallel architecture is derived through matrix operations, overcoming the complexity of traditional ad hoc methods. Crucially, our framework enables an analysis of parallelization-induced latency. We introduce the parallel equivalent delay (PED) metric and demonstrate that it introduces right-half-plane zeros into the loop’s transfer function, thereby fundamentally constraining stability. This analysis leads to the derivation of “Throughput–Bandwidth Product” (TBP), a constant that provides a design guideline linking maximum stable loop bandwidth to the parallelization factor. The framework’s efficacy is demonstrated by designing a parallel Costas carrier recovery loop. Simulations validate its performance, confirm the TBP limit, and show significant advantages over conventional feedforward estimators, especially in low-SNR conditions. Implementation results on a AMD XCVU13P FPGA demonstrate that the proposed 50-parallel architecture achieves a throughput of 15.625 Gsps at a clock frequency of 312.5 MHz with a logic utilization below 7%. The experimental results confirm the theoretical trade-off between throughput and loop bandwidth, verifying the proposed design methodology. Full article

For the first time, a highly energy-efficient 32-parallel 64-point FFT scheme for IMDD OFDM-PON is proposed and implemented on a Xilinx ML605 platform. By experimentally verifying the power consumption model for the FPGA logic resources utilized in the FFT, the relationship between FFT calculating consumption and FPGA logic resource usage is established. Based on this relationship, we derive a resource selection principle for the FFT bit resolution optimization to minimize power consumption under different levels of received optical power. Consequently, the proposed FFT achieves a 76.1% reduction in power consumption compared to the traditional Spiral FFT at a received optical power of −21 dBm. Based on the proposed FFT, the real-time OFDM-PON receiver power consumption can save up to 43% compared with traditional OFDM-PON system. Full article

This paper presents the design, development, and evaluation of an embedded hardware and digital signal processing (DSP)-based real-time gesture-controlled system. The system architecture utilizes an MPU6050 inertial measurement unit (IMU), Arduino Uno microcontroller, and Python-based audio interface to recognize and classify directional hand gestures and transform them into auditory commands. Wrist tilts, i.e., left, right, forward, and backward, are recognized using a hybrid algorithm that uses thresholding, moving average filtering, and low-pass smoothing to remove sensor noise and transient errors. Hardware setup utilizes I²C-based sensor acquisition, onboard preprocessing on Arduino, and serial communication with a host computer running a Python script to trigger audio playing using the playsound library. Four gestures are programmed for basic needs: Hydration Request, Meal Support, Restroom Support, and Emergency Alarm. Experimental evaluation, conducted over more than 50 iterations per gesture in a controlled laboratory setup, resulted in a mean recognition rate of 92%, with system latency of 120–150 milliseconds. The approach has little calibration costs, is low-cost, and offers low-latency performance comparable to more advanced camera-based or machine learning-based methods, and is therefore suitable for portable assistive devices. Full article

In recent years, with the development of novel hardware such as memristors, integrating chaotic systems with hardware implementations has enabled efficient and controllable generation of chaotic signals, providing new avenues for both theoretical research and engineering applications. In this work, we propose a novel memristor-based chaotic system, named the three-dimensional discrete echo-memristor map (3D-DEMM). The 3D-DEMM is capable of generating complex dynamic behaviors with self-similar attractor structures; specifically, under different parameters and initial conditions, the system produces similar attractor shapes at different amplitudes, which we refer to as an echo chaotic map. By incorporating the discrete nonlinear characteristics of memristors, the 3D-DEMM is systematically designed. We first conduct a thorough dynamic analysis of the 3D-DEMM, including attractor visualization, Lyapunov exponents, and NIST tests, to verify its chaoticity and self-similarity. Subsequently, the attractors of the 3D-DEMM are captured on a DSP platform, demonstrating discrete-time hardware simulation and real-time operation. Experimental results show that the proposed system not only exhibits highly controllable chaotic behavior but also demonstrates strong robustness in maintaining amplitude-invariant attractor shapes, providing a new theoretical and practical approach for memristor-based chaotic signal generation and applications in information security. Full article

Synthetic Aperture Radar (SAR) onboard satellites provides high-resolution Earth imaging independent of weather conditions. SAR data are acquired by an aircraft or satellite and sent to a ground station to be processed. However, for novel applications requiring real-time analysis and decisions, onboard processing is necessary to escape the limited downlink bandwidth and latency. One such application is real-time target recognition, which has emerged as a decisive operation in areas such as defense and surveillance. In recent years, deep learning models have improved the accuracy of target recognition algorithms. However, these are based on optical image processing and are computation and memory expensive, which requires not only processing the SAR pulse data but also optimized models and architectures for efficient deployment in onboard computers. This paper presents a fast and accurate target recognition system directly on raw SAR data using a neural network model. This network receives and processes SAR echo data for fast processing, alleviating the computationally expensive DSP image generation algorithms such as Backprojection and RangeDoppler. Thus, this allows the use of simpler and faster models, while maintaining accuracy. The system was designed, optimized, and tested on low-cost embedded devices with low size, weight, and energy requirements (Khadas VIM3 and Raspberry Pi 5). Results demonstrate that the proposed solution achieves a target classification accuracy for the MSTAR dataset close to 100% in less than 1.5 ms and 5.5 W of power. Full article

You Only Look Once (YOLO) is a convolutional neural network-based object detection algorithm widely used in real-time vision applications. However, its high computational demand leads to significant power consumption and cost when deployed in graphics processing units. Field-programmable gate arrays offer a low-power alternative. However, their efficient implementation requires architecture-level optimization tailored to limited device resources. This study presents an optimized YOLOv2 accelerator for the Zynq-7000 system-on-chip (SoC). The design employs 16-bit integer quantization, a filter reuse structure, an input feature map reuse scheme using a line buffer, and tiling parameter optimization for the convolution and max pooling layers to maximize resource efficiency. In addition, a stall-based control mechanism is introduced to prevent structural hazards in the pipeline. The proposed accelerator was implemented on the Zynq-7000 SoC board, and a system-level evaluation confirmed a negligible accuracy drop of only 0.2% compared with the 32-bit floating-point baseline. Compared with previous YOLO accelerators on the same SoC, the design achieved up to 26% and 15% reductions in flip-flop and digital signal processor usage, respectively. This result demonstrates feasible deployment on XC7Z020 with DSP 57.27% and FF 16.55% utilization. Full article

The increasing integration of high-frequency power electronic converters in renewable energy-grid systems has escalated reliability concerns, necessitating FPGA-accelerated large-scale real-time electromagnetic transient (EMT) computation to prevent failures. However, most existing studies prioritize computational performance and struggle to achieve large-scale EMT computation. To enhance the computational scale, we propose a scalable hardware architecture comprising domain-specific components and data-centric processing element (PE) arrays. This architecture is further enhanced by a graph-based matrix mapping methodology and matrix-aware fixed-point quantization for hardware-efficient computation. We demonstrate our principles with FPGA implementations of large-scale multi-converter systems. The experimental results show that we set a new record of supporting 1200 switches with a computation latency of 373 ns and an accuracy of 99.83% on FPGA implementations. Compared to the state-of-the-art large-scale EMT computation on FPGAs, our design on U55C FPGA achieves an up-to 200.00× increase in the switch scale, without I/O resource limitations, and demonstrates up-to 71.70% reduction in computation error and 51.43% reduction in DSP consumption, respectively. Full article

In dynamic and information-rich contexts, systems must be capable of making instantaneous, context-aware decisions. Such scenarios require optimization methods that are both fast and flexible. This paper introduces an innovative hardware-based intelligent optimization framework, deployed on FPGAs, designed to support autonomous decisions in real-time systems. In contrast to conventional methods based on a single chaotic map, our scheme brings together six separate chaotic generators in simultaneous operation, orchestrated by an adaptive voting system based on past results. The system, in conjunction with the Secretary Bird Optimization Algorithm (SBOA), constantly adjusts its optimization approach according to the changing profile of the objective function. This delivers first-rate, timely solutions with improved convergence, resistance to local minima, and a high degree of adaptability to a variety of decision-making contexts. Simulations carried out on reference standards and engineering problems have demonstrated the scalability, responsiveness, and efficiency of the proposed model. These characteristics make it particularly suitable for use in embedded intelligence applications in sectors such as intelligent production, robotics, and IoT-based infrastructures. The suggested solution was tested using post-synthesis simulations on Vivado 2022.2 and experimented on three concrete engineering challenges: welded beam design, pressure equipment design, and tension/compression spring refinement. In each situation, the adaptive selection process dynamically determined the most suitable chaotic map, such as the logistics map for the Welded Beam Design Problem (WBDP) and the Tent map for the Pressure Vessel Design Problem (PVDP). This led to ideal results that exceed both conventional static methods and recent references in the literature. The post-synthesis results on the Nexys 4 DDR (Artix-7 XC7A100T, Digilent Inc., Pullman, WA, USA) show that the initial Q16.16 implementation exceeded the device resources (128% LUTs and 100% DSPs), whereas the optimized Q4.8 representation achieved feasible deployment with 80% LUT utilization, 72% DSP usage, and 3% FF occupancy. This adjustment reduced resource consumption by more than 25% while maintaining sufficient computational accuracy. Full article

The paper proposes a parallel transformerless (TL) static synchronous series compensator (SSSC) for the control of power flow along the power distribution lines under balanced or unbalanced voltages. This new SSSC configuration offers the advantages of a fast dynamic response, light weight, and high efficiency. By connecting multiple SSSCs in parallel, the current rating is increased, which improves the grid power transfer capabilities and flexibility. However, there may be circulating current flowing between the parallel-connected inverters, hence causing losses. A modified model predictive control scheme is thus developed, which ensures that the proposed SSSC accurately tracks the reference currents while effectively mitigating the circulating current. The model and cost function of the controller are derived and analyzed in the paper. A real-time simulation of a power line with the parallel TL SSSC controlled by a hardware-in-loop (HIL) DSP is developed to validate the performance of this device under both balanced and unbalanced line voltages. Full article

In this work, a controller hardware-in-the-loop (CHIL) simulation of a grid-connected three-phase inverter equipped with an LCL filter is implemented using a real-time digital simulator (RTDS) as the plant and a digital signal processor (DSP) as the control hardware. This work identifies and discusses the critical aspects of the CHIL implementation process, emphasizing the relevance of the control delays that arise from sampling, computation, and pulse width modulation (PWM), which also adversely affect system stability, accuracy, and performance. Time and frequency domains are used to validate the modeling of the system, either to represent large-signal or small-signal models. This work shows multiple representations of the system under study: the fundamental frequency model, the switched model, and the switched model controlled by the DSP, are used to validate the nonlinear model, whereas the impedance-based modeling is followed to validate the linear representation. The results demonstrate a strong correlation among the models, confirming that the delay effects are accurately captured in the different simulation approaches. This comparison provides valuable insights into configuration practices that improve the fidelity of CHIL-based validation and supports impedance-based stability analysis in power electronic systems. The findings are particularly relevant for wideband modeling and real-time studies in electromagnetic transient analysis. Full article

Addressing escalating demands for high-precision compact robotic actuators, this study overcomes persistent challenges from nonlinear transmission dynamics and computational constraints through a co-designed framework integrating three innovations. A real-time second-order characteristic modeling approach enables 10 kHz online parameter identification, reducing computational load by 13.1% versus MPC. Building on this foundation, a hybrid integral sliding-mode controller eliminating modeling errors while maintaining ≤0.25 rad/s tracking error (SRMSE) under variable loads was created. These algorithmic advances are embedded within a miniaturized dual-ARM platform (47 × 47 × 12 mm³) achieving <30-ns overcurrent protection and 36% cost reduction versus DSP/FPGA solutions. Validated via Lyapunov stability proofs and experiments, this framework is particularly effective for high-performance robotic joint control in spatially- and thermally-constrained environments while dynamically compensating for unmodeled nonlinearities. Full article

This review outlines the technological principles of neural–computer interface (NCI) construction, classifying them according to: (1) the degree of intervention (invasive, semi-invasive, and non-invasive); (2) the direction of signal communication, including BCI (brain–computer interface) for converting neural activity into commands for external devices, CBI (computer–brain interface) for translating artificial signals into stimuli for the CNS, and BBI (brain–brain interface) for direct brain-to-brain interaction systems that account for agency; and (3) the mode of user interaction with technology (active, reactive, passive). For each NCI type, we detail the fundamental data processing principles, covering signal registration, digitization, preprocessing, classification, encoding, command execution, and stimulation, alongside engineering implementations ranging from EEG/MEG to intracortical implants and from transcranial magnetic stimulation (TMS) to intracortical microstimulation (ICMS). We also review mathematical modeling methods for NCIs, focusing on optimizing the extraction of informative features from neural signals—decoding for BCI and encoding for CBI—followed by a discussion of quasi-real-time operation and the use of DSP and neuromorphic chips. Quantitative metrics and rehabilitation measures for evaluating NCI system effectiveness are considered. Finally, we highlight promising future research directions, such as the development of electrochemical interfaces, biomimetic hierarchical systems, and energy-efficient technologies capable of expanding brain functionality. Full article

The substantial volume of data acquired through remote-detection acoustic logging poses a remarkable challenge because of the limited real-time upload speed of the cable, which severely impedes its further application. To address this issue, a two-stage data compression method that was implemented at the acquisition node was proposed in this study. This approach includes a field programmable gate array (FPGA)-based hardware system and a two-stage downhole data compression algorithm combining wavelet transform and adaptive differential pulse-code modulation paired with ground decompression software. Finally, the proposed compression method was evaluated using actual logging data. The test results revealed that the overall compression rate of the two-stage compression method was 25.1%. The reconstructed waveforms highly retained the overall shape of the original waveforms, and the severe relative distortion of individual data points did not affect the extraction of the sliding longitudinal, sliding transverse and reflected waveforms. The FPGA compressed 2048 16-bit waveforms in approximately 100 μs with low resource utilization and workload. It considerably outperformed DSP-based pre-transmission compression. Herein, the data compression method at the acquisition node helped in reducing the workload on the master control node and increasing the effective speed of the cable transmission up to 400%, thereby enhancing the remote-detection acoustic logging. Full article