Contextual Real-Time Optimization on FPGA by Dynamic Selection of Chaotic Maps and Adaptive Metaheuristics

In dynamic and information-rich contexts, systems must be capable of making instantaneous, context-aware decisions. Such scenarios require optimization methods that are both fast and flexible. This paper introduces an innovative hardware-based intelligent optimization framework, deployed on FPGAs, designed to support autonomous decisions in real-time systems. In contrast to conventional methods based on a single chaotic map, our scheme brings together six separate chaotic generators in simultaneous operation, orchestrated by an adaptive voting system based on past results. The system, in conjunction with the Secretary Bird Optimization Algorithm (SBOA), constantly adjusts its optimization approach according to the changing profile of the objective function. This delivers first-rate, timely solutions with improved convergence, resistance to local minima, and a high degree of adaptability to a variety of decision-making contexts. Simulations carried out on reference standards and engineering problems have demonstrated the scalability, responsiveness, and efficiency of the proposed model. These characteristics make it particularly suitable for use in embedded intelligence applications in sectors such as intelligent production, robotics, and IoT-based infrastructures. The suggested solution was tested using post-synthesis simulations on Vivado 2022.2 and experimented on three concrete engineering challenges: welded beam design, pressure equipment design, and tension/compression spring refinement. In each situation, the adaptive selection process dynamically determined the most suitable chaotic map, such as the logistics map for the Welded Beam Design Problem (WBDP) and the Tent map for the Pressure Vessel Design Problem (PVDP). This led to ideal results that exceed both conventional static methods and recent references in the literature. The post-synthesis results on the Nexys 4 DDR (Artix-7 XC7A100T, Digilent Inc., Pullman, WA, USA) show that the initial Q16.16 implementation exceeded the device resources (128% LUTs and 100% DSPs), whereas the optimized Q4.8 representation achieved feasible deployment with 80% LUT utilization, 72% DSP usage, and 3% FF occupancy. This adjustment reduced resource consumption by more than 25% while maintaining sufficient computational accuracy.