Controller Hardware-in-the-Loop Validation of a DSP-Controlled Grid-Tied Inverter Using Impedance and Time-Domain Approaches

Abstract

In this work, a controller hardware-in-the-loop (CHIL) simulation of a grid-connected three-phase inverter equipped with an LCL filter is implemented using a real-time digital simulator (RTDS) as the plant and a digital signal processor (DSP) as the control hardware. This work identifies and discusses the critical aspects of the CHIL implementation process, emphasizing the relevance of the control delays that arise from sampling, computation, and pulse width modulation (PWM), which also adversely affect system stability, accuracy, and performance. Time and frequency domains are used to validate the modeling of the system, either to represent large-signal or small-signal models. This work shows multiple representations of the system under study: the fundamental frequency model, the switched model, and the switched model controlled by the DSP, are used to validate the nonlinear model, whereas the impedance-based modeling is followed to validate the linear representation. The results demonstrate a strong correlation among the models, confirming that the delay effects are accurately captured in the different simulation approaches. This comparison provides valuable insights into configuration practices that improve the fidelity of CHIL-based validation and supports impedance-based stability analysis in power electronic systems. The findings are particularly relevant for wideband modeling and real-time studies in electromagnetic transient analysis.

1. Introduction

Increasing integration of electronic devices within power grids has posed novel challenges concerning system stability. A significant emerging concern arises from the uncontrolled surplus energy in elements of power electronics-based systems, which manifests in rapid oscillations of stored energy between electric and magnetic fields [1]. These oscillations lead to swift fluctuations in electrical and control variables. This phenomenon is particularly pronounced in grids that incorporate controlled power electronics converters. The modeling and simulation of these systems is indispensable for the identification, evaluation, and analysis of such phenomena. Hence, it is imperative to execute these simulations with precision, incorporating the necessary parameters, controls, and elements. Typically, dynamic simulations are conducted to examine stability phenomena, including transient, voltage, and frequency stability. Control and protection applications can also be evaluated in specific simulation environments to better understand primary system behaviour. However, the complete effects of hardware implementation are not fully considered in offline simulations. This is especially true for power electronic converters, controls, and protection mechanisms that have a fast response. Consequently, the control hardware must be evaluated along with the simulation model of the system, particularly in advanced stages of test development. These simulation approaches, combining control hardware and real-time simulators, are known as controller hardware-in-the-loop simulations. Despite the advantages that CHIL simulations offer, such as a more realistic test environment, detailed models, safe operative conditions, and automation and repetitiveness of tests, there are still several challenges behind the successful implementation of this approach.

Various studies have implemented CHIL in different contexts. In [2], a passive method for detecting islanding based on the phase angle of overlapping negative sequence components is validated. Although the detection method is implemented in a dSPACE 1104 and the RTDS is used to develop a benchmark IEEE-34 bus network, none of the control systems of the generation units is dumped into an external hardware, and consequently the impact of the pulse width modulation strategy on the power system is not documented. The authors in [3] designed a robust controller to cope with network impedance variations and evaluates it in a CHIL environment. In this environment, the plant consisting of a high-voltage direct current (HVDC) link and a modular multilevel converter (MMC) was modeled in an RTDS and coupled to a controller implemented in a Xilinx Zynq XC7Z030-3FBG676E DSP/FPGA. Validation was performed by analyzing the system admittance. However, the impact of switching delays was not evaluated, nor was a comparison between the analytical model and the results obtained in CHIL presented. The work proposed in [4] developed a real-time co-simulation platform for grid-forming storage system controllers. This advanced simulation ecosystem allows for rapid control testing of an experimental test bench using an RTDS and an FPGA controller. Despite using powerful tools in the context of a CHIL setup, the proposal fails to provide guidelines for the control hardware implementation to mitigate instability caused by the inherent delays of the feedback loop. The work described in [5] proposes a comprehensive validation framework for power electronics systems that integrates SIL, HIL, CHIL, PHIL, and RCP. The framework is exemplified by a two-stage cascade conversion plant: a boost stage that controls the maximum power extracted from the photovoltaic panel and an inverter stage under control in the synchronous d–q frame, which maintains the DC bus voltage constant and regulates the reactive power injected into the grid. The methodology includes offline simulations, real-time simulations, and finally, a CHIL simulation. The real-time simulation is run entirely on the F28379D DSP; the CHIL is implemented on an Opal-RT OP-4510, separating the power and control circuits into different processors and considering the communication delays between them. The latencies in both configurations are analyzed and the resulting signals are compared. However, although aspects of the delays and the implementation of the PWM are discussed, the study does not address guidelines for external control hardware or evaluate the impact of these delays on controller performance. Finally, ref. [6] proposes a real-time testing method for digital power electronics controllers. The platform implements real-time simulation in an RTDS, coupled to an external controller based on a TI TMS320C28x DSP. Different representative cases are evaluated, including a buck type DC-DC converter and a DC-AC converter, and the duty cycle, the plant structure within the RTDS, and the control algorithm executed in the DSP are discussed. It also briefly addresses the switching frequency limitation imposed by the plant integration step in the RTDS and compares the results obtained between the configurations. Although it demonstrates the feasibility of the CHIL implementation, the study does not present comparisons with analytical models or experimental results.

This article addresses challenges in simulating a grid-connected three-phase inverter with an LCL filter. It uses a real-time digital simulator (RTDS) to model the plant and a digital signal processor (DSP) for control, and provides insights into the process of closing the loop via the control hardware. In the experience of the authors, these observations are valuable for less-experienced users and beginners as they can help save time in the debugging stages of the testing process. Preliminary results, figures, and models presented in the article were initially developed as part of the first author’s master’s thesis [7]. The remainder of this article is organized as follows. Section 2 discusses the main features of CHIL simulation. Section 3 presents the inverter model used in the real-time simulator, along with the PI control and phase-locked loop (PLL) used to manage power flow. Section 4 outlines a methodology for implementing CHIL. Section 5 discusses the test results and compares them with the mathematical model.

2. Introduction to Control Hardware-in-the-Loop Simulation

Hardware-in-the-loop (HIL) simulations involve integrating physical components into the simulation environment, rather than relying solely on digital mathematical models. When the controller is the physical component in the HIL setup, this configuration is referred to as controller hardware-in-the-loop (CHIL) [8,9]. CHIL simulations do not imply power transferred between the real-time simulation and the hardware. The interchange of signals between the digitally modeled plant and the hardware is performed only for communication protocols or low-power signals (voltage or currents). This method is generally used to test newly developed controllers. Figure 1 illustrates a basic implementation of CHIL, in which the power electronic converter is represented within the real-time simulator environment, while the controller interacts through the simulator’s interfaces. These concepts are better explained in [10].

3. Modeling of Three-Phase Inverter and Control

This section presents the test system used to validate and show the CHIL simulation approach. It briefly mentions the elements involved in the simulation, the plant, the control laws, and the synchronization control in the time domain. Moreover, a linear model of the system around the steady-state operating point is presented. For this purpose, the impedance model is derived in the $dq$ framework by considering only the positive sequence in the frequency domain, assuming a balanced system.

3.1. Three-Phase Grid-Connected Inverter

Figure 2 shows the control implementation diagram for the three-phase inverter. By expressing the current and voltage components in dq coordinates, the control strategy is simplified since it allows for setting independent current references for the d and q components.

3.2. Phase-Locked Loop

To implement the control in the dq reference frame, the transformation from abc to dq must be carried out. This transformation relies on the usage of the phase obtained from the phase-locked loop (PLL) as a reference frame. The PLL illustrated in Figure 3 is capable of obtaining the phase of a signal; in this way, the PLL acquires information from the electrical network, thus synchronizing the voltage and current signals between the converter and the electrical network.

3.3. Control Scheme

Currently, various control strategies are employed in voltage-source converters (VSCs), providing the flexibility to select the most suitable one based on system requirements. Some of these strategies regulate the grid voltage and frequency, and control the exchange of active and reactive power between the converter and the grid. In this study, a grid-following mode is adopted, which enables direct control of active and reactive power. The control scheme proposed in [11] is illustrated in Figure 4, which assumes ideal decoupling of the d and q components, allowing independent regulation of the current and voltage along each axis. In practice, however, some degree of coupling remains due to system dynamics and hardware limitations.

3.4. PI Controller Tuning

To calculate $K_p$ and $K_i$, frequency response tuning is used, as it is a technique used in the design of controllers for control systems. It consists of adjusting the controller parameters so that the frequency response of the closed-loop system meets certain performance requirements, such as gain margin and phase margin [12]. Consider the following open-loop model:

$$L\left(s\right)=C\left(s\right)D\left(s\right)F\left(s\right)G\left(s\right)$$

(1)

where $C\left(s\right)=K_p{\displaystyle \frac{T_{n}s+1}{T_{n}s}}$ is the PI; $D\left(s\right)={\displaystyle \frac{1}{1.5T_{switching}s+1}}$ groups the effects of digitization as if it were 1.5 times the switching period ($T_{switching}$) of the PWM; $F\left(s\right)={\displaystyle \frac{1}{\tau s+1}}$ is the digital filter; and $G\left(s\right)$ is the plant. Given the crossover frequency ${\omega }_c\left({\displaystyle \frac{rad}{s}}\right)$ and the desired phase margin (PM) in degrees, the following conditions apply:

• Phase condition for calculating $T_n$ is

  $$\mathrm{PM}={180}^{\circ }+\angle C+\angle D+\angle F+\angle G$$

  (2)
• Module condition for calculating $K_p$ in ${\omega }_c$ requires that $\left|L\left(j{\omega }_c\right)\right|=1$, i.e.,

  $$1=\left|C\left(j{\omega }_c\right)\right|\left|D\left(j{\omega }_c\right)\right|\left|F\left(j{\omega }_c\right)\right|\left|G\left(j{\omega }_c\right)\right|$$

  (3)

3.5. Three-Phase Closed-Loop Inverter Model

The time-domain model of the three-phase closed-loop inverter used in this study is based on the approach presented in [13], where a generalized framework for n parallel inverters connected to the grid was developed. The closed-loop control law adopts the formulation proposed in [11]. The models detailed in [14] provide the basis for deriving the impedance model discussed in the following subsection. See Appendix A for the equations that characterize the closed-loop inverter dynamics.

3.6. Small-Signal Impedance Model

The $2\times 2$ source-side impedance matrix of the test system shown in Figure 2, denoted by ${\mathit{Z}}_s\left(s\right)$, is expressed in the Laplace domain as follows:

$$\begin{array}{cc}\hfill {\mathit{Z}}_s\left(s\right)& ={\left[\mathit{I}+\left(\mathit{RD}+{\mathit{Y}}^{-1}\right)\left({\mathit{Z}}^{-1}-{\mathit{Z}}^{-1}{\mathit{G}}_e\right)\right]}^{-1}\hfill \\ \hfill & \times \left[\left(\mathit{RD}+{\mathit{Y}}^{-1}\right)\left(\mathit{I}-{\mathit{Z}}^{-1}{\mathit{G}}_d\right)\right]\hfill \end{array}$$

(4)

In the matrix ${\mathit{Z}}_s\left(s\right)$, the diagonal elements $Z_{s_{dd}}\left(s\right)$ and $Z_{s_{qq}}\left(s\right)$ correspond to the impedances along the d- and q-axes, respectively. The off-diagonal terms $Z_{s_{dq}}\left(s\right)$ and $Z_{s_{qd}}\left(s\right)$ represent the cross-coupling between these axes. This matrix is arranged by

$$\begin{array}{c}\hfill {\mathit{Z}}_s\left(s\right)=\left[\begin{array}{cc}{Z}_{s_{dd}}\left(s\right)& Z_{s_{dq}}\left(s\right)\\ Z_{s_{qd}}\left(s\right)& Z_{s_{qq}}\left(s\right)\end{array}\right]\end{array}$$

(5)

The matrices involved in Equation (4) are briefly described below. Key components include the diagonal matrices ${\mathit{C}}_i$, $\mathit{RD}$, ${\mathit{G}}_{ffv}$, and ${\mathit{G}}_{ffi}$, representing the PI current controller, damping resistor, voltage filter, and current filter, respectively. Variables with a subscript zero, $x_0$, denote their corresponding steady-state values. $\mathit{Z}$ is part of the filter impedance in the dq reference frame. The diagonal elements include $R_c$ and ${\displaystyle \frac{L_c}{{\omega }_b}}s$, while the off-diagonal terms capture the cross-coupling induced by $L_c$.

$$\begin{array}{c}{\mathit{C}}_i=\left[\begin{array}{cc}{K}_{p_{dq}}+{\displaystyle \frac{K_{i_{dq}}}{s}}& 0\\ 0& K_{p_{dq}}+{\displaystyle \frac{K_{i_{dq}}}{s}}\end{array}\right]\end{array}$$

(6)

$$\begin{array}{c}\mathit{RD}=\left[\begin{array}{cc}{R}_d& 0\\ 0& R_d\end{array}\right]\end{array}$$

(7)

$$\begin{array}{c}{\mathit{G}}_{ffv}=\left[\begin{array}{cc}{\displaystyle \frac{1}{{\tau }_{ffv}s+1}}& 0\\ 0& {\displaystyle \frac{1}{{\tau }_{ffv}s+1}}\end{array}\right]\end{array}$$

(8)

$$\begin{array}{c}{\mathit{G}}_{ffi}=\left[\begin{array}{cc}{\displaystyle \frac{1}{{\tau }_{ffi}s+1}}& 0\\ 0& {\displaystyle \frac{1}{{\tau }_{ffi}s+1}}\end{array}\right]\end{array}$$

(9)

$$\begin{array}{c}\mathit{Z}=\left[\begin{array}{cc}{R}_c+{\displaystyle \frac{L_c}{{\omega }_b}}s& -L_c\\ L_c& R_c+{\displaystyle \frac{L_c}{{\omega }_b}}s\end{array}\right]\end{array}$$

(10)

$\mathit{Y}$ represents the admittance of the filter capacitor, also expressed in dq coordinates. The diagonal elements contain the capacitive term ${\displaystyle \frac{C}{{\omega }_b}}s$, while the off-diagonal elements account for the capacitive coupling:

$$\begin{array}{c}\hfill \mathit{Y}=\left[\begin{array}{cc}{\displaystyle \frac{C}{{\omega }_b}}s& -C\\ C& {\displaystyle \frac{C}{{\omega }_b}}s\end{array}\right]\end{array}$$

(11)

Park’s transformation matrix $\mathit{T}$ is used to transform the three-phase ($abc$) system into the rotating $dq$ reference frame:

$$\begin{array}{c}\hfill \mathit{T}=\left[\begin{array}{cc}cos\left(\delta \right)& sin\left(\delta \right)\\ -sin\left(\delta \right)& cos\left(\delta \right)\end{array}\right]\end{array}$$

(12)

${\mathit{G}}_a$ models the dynamics associated with the PLL and the voltage filter. It incorporates the PLL gain ${\mathit{G}}_{pll}$, voltage filter gain ${\mathit{G}}_{ffv}$, and the transformation matrices $\mathit{T}$ and its time derivative $\dot{\mathit{T}}$, evaluated at the operating point ${\mathit{v}}_{PC{C}_0}$.

$$\begin{array}{cc}\hfill {\mathit{G}}_a& ={\left[1-\left({\displaystyle \frac{{\omega }_b}{s}}{\mathit{G}}_{pll}{\mathit{G}}_{ffv}\dot{\mathit{T}}{\mathit{v}}_{PC{C}_0}\right)\right]}^{-1}\left[{\displaystyle \frac{{\omega }_b}{s}}{\mathit{G}}_{pll}{\mathit{G}}_{ffv}\mathit{T}\right]\hfill \end{array}$$

(13)

${\mathit{G}}_b$ captures the contribution of the voltage filter to the system, combining the filter gain ${\mathit{G}}_{ffv}$ with the effects of coordinate transformation and PLL dynamics via ${\mathit{G}}_a$.

$$\begin{array}{c}\hfill {\mathit{G}}_b={\mathit{G}}_{ffv}\left(\mathit{T}+\dot{\mathit{T}}{\mathit{v}}_{PC{C}_0}{\mathit{G}}_a\right)\end{array}$$

(14)

${\mathit{G}}_c$ incorporates the current controller ${\mathit{C}}_i$, the compensation gain ${\mathit{G}}_{Lc}$, the current filter ${\mathit{G}}_{ffi}$, and the PLL-related dynamics.

$$\begin{array}{cc}\hfill {\mathit{G}}_c& =\left(\left(-{\mathit{C}}_i+{\mathit{G}}_{Lc}\right){\mathit{G}}_{ffi}\dot{\mathit{T}}{\mathit{I}}_{D{Q}_0}{\mathit{G}}_a\right)+{\mathit{G}}_b\hfill \end{array}$$

(15)

${\mathit{G}}_d$ reflects the impact of the digital delay $e^{-T_{s}s}$ introduced by the switching frequency, as well as the dynamics of the current controller. The DC bus voltage $V_{dc}$ scales the overall gain.

$$\begin{array}{c}\hfill {\mathit{G}}_d=V_{dc}{\mathit{T}}^{-1}{\displaystyle \frac{e^{-T_{s}s}}{V_{dc}}}\left(-{\mathit{C}}_i+{\mathit{G}}_{Lc}\right){\mathit{G}}_{ffi}\mathit{T}\end{array}$$

(16)

${\mathit{G}}_e$ is a composite expression that aggregates several system effects, including delay, controller dynamics, and interactions with the network impedance $(\mathit{RD}+{\mathit{Y}}^{-1})$.

$$\begin{array}{cc}\hfill {\mathit{G}}_e& =V_{dc}\left[{\mathit{T}}^{-1}{\displaystyle \frac{e^{-T_{s}s}}{V_{dc}}}\left(-{\mathit{C}}_i+{\mathit{G}}_{Lc}\right){\mathit{G}}_{ffi}\mathit{T}{\left(\mathit{RD}+{\mathit{Y}}^{-1}\right)}^{-1}\right]\hfill \\ \hfill & +\left({\mathit{T}}^{-1}{\displaystyle \frac{e^{-T_{s}s}}{V_{dc}}}{\mathit{G}}_c\right)+\left({\dot{\mathit{T}}}^{-1}{\mathit{e}}_{d{q}_0}{\mathit{G}}_a\right)\hfill \end{array}$$

(17)

4. Insights into DSP-Based Control Integration with RTDS

The implementation of CHIL allows the performance of the controller to be verified under realistic conditions prior to its practical application. In this context, the RTDS is used as the plant, while the DSP is the hardware responsible for controlling the inverter switching, as visualized in Figure 5.

4.1. Procedure

For a proper implementation of CHIL, the following steps are recommended:

• Define the system to be controlled: Identify the system to be controlled and establish clear objectives.
• Select system components: Choose necessary elements such as the real-time simulator and data processing board.
• Configuring the simulation environment: Set up the simulator as a plant and configure all the necessary parameters.
• Calibrate the inverter parameters: Adjust the three-phase inverter parameters within the simulation, including the gigabit transceiver digital output (GTAO) and the gigabit transceiver digital input (GTDI) settings.
• Integrate hardware and software: Connect DSP to RTDS, ensuring correct signal transmission.
• Perform initial tests: Perform preliminary tests to verify the correct operation and effectiveness of communication.
• Execute the CHIL simulation: Conduct simulations under different operating conditions to evaluate controller performance.
• Analyze results and adjust: Review the results obtained and make adjustments to the controller as necessary.

Following the above steps helps to avoid conflicts during CHIL implementation. Clearly defining the system to be controlled is fundamental; for instance, a three-phase inverter capable of transferring power to the grid with high efficiency is required, implementing control laws that adjust the current via proper switching of the inverter [15].

4.2. Timing and Digital Control Implementation

The selection of system components demands careful consideration of their distinct characteristics, particularly regarding delay and accuracy in the GTAO, GTDI, and DSP cards. For the GTAO card, a write delay of approximately 9.203 $\mathsf{\mu }$s is presented in the simulation, due to its interface with the simulator [16]. While these delays from data transfer cards are inherent and unavoidable, they must be accounted for in test design to avoid compromising result accuracy. Proper hardware and software integration is crucial. If signals from the simulation are not correctly scaled or exhibit offsets, control laws in the DSP will not execute properly, producing inconsistent PWM signals. To accurately capture each switching transition and avoid missing SPWM pulses, at least N time steps per switching period is required. Thus, the maximum admissible switching frequency is $f_{\mathrm{sw},\max }={\displaystyle \frac{1}{N\Delta t_s}}$. Using $\Delta t_s=1.5\mathsf{\mu }\mathrm{s}$ and $N=10$ gives $f_{\mathrm{sw},\max }={\displaystyle \frac{1}{10\times 1.5\mathsf{\mu }\mathrm{s}}}\approx 66.7\mathrm{kHz}$. However, the maximum recommended switching frequency for modeling voltage-source converters in RTDS is 3 kHz. Beyond this threshold, the RTDS model experiences significant power losses. In order to implement continuous-time control laws within the DSP, it is necessary to discretize them using appropriate techniques that ensure accurate real-time execution. The method selected due to its numerical stability is bilinear transformation. This method can be briefly summarized by the following rule: given a continuous-time transfer function $H\left(s\right)$, its discrete equivalent is obtained using $H_T\left(z\right)=H\left(s\right)$ with $s={\displaystyle \frac{2}{T}}{\displaystyle \frac{z-1}{z+1}}$, according to [12]. This transformation helps to convert continuous transfer functions into difference equations that the DSP executes at fixed sampling intervals. The sampling frequency ($f_s$) must be chosen according to the processing capacity of the DSP. For example, if the maximum clock frequency of the device is $100\mathrm{kHz}$ and a sampling frequency of $150\mathrm{kHz}$, the processor will not be able to perform the calculations in the time available, which will degrade the controller’s performance and may make it unstable. In order to efficiently couple the control loop implemented within the DSP with the real-time simulation in the RTDS, it is essential to apply two constraints:

• Frequency coverage. The sampling frequency within the RTDS must be sufficiently small to capture the dynamics of the controller, i.e., if the closed-loop control bandwidth ($f_{BW}$) is $100\mathrm{Hz}$, the rule applies $f_s\ge 10f_{BW}$; therefore, it is sufficient for the sampling period of the real-time simulation to be less than 1 ms [17].
• Deterministic synchrony. The DSP sampling period must be an integer multiple of the RTDS time step. This will prevent fluctuations because it ensures that each control interruption coincides exactly with a moment in the simulation [18].

Open-loop testing is recommended for each component and can be structured into three cases:

• Evaluate only real-time simulation, either by implementing the control within the RTDS or by using constant values for the variables needed to construct the PWM signal that controls the power flow.
• Evaluate only the DSP, making sure that the control laws are properly executed with constant current values and verifying that the generated PWM signals are coherent.
• Connect the DSP to the RTDS, but control the system only by means of a PWM with predefined variables. This allows us to verify that the results obtained in the simulation are correct and to validate that each component is properly configured.

When running the CHIL simulation, it is necessary to perform additional tests to verify that the control laws are properly tuned to the inverter parameters. This is performed by changing reference variables and adjusting the DSP-clock timing to ensure the control can drive the three-phase inverter to different operating points. Figure 6 shows key parts of the simulation. The inverter must be configured to receive switching signals from each switch via the GTDI, ideally conditioned with a trigger pulse filter. The LCL filter must be accurately calculated, as CHIL would be ineffective without accounting for factors like power flow limits, direction, and resonant frequency. Lastly, the grid is selected according to the power capacities.

4.3. Methodology

An effective way to recognize inconsistencies or errors in the CHIL simulation is through understanding the implementation methodology. By properly understanding each component of the simulation, it is easier to identify mismatches in the system. Key steps in achieving this include the following:

• Obtaining current and voltage signals from the system: This step is crucial to ensure that the initial conditions are representative of the real system.
• Normalization and proper signal transmission to the DSP: Correct normalization ensures that the signals are correctly interpreted by the digital processor.
• Implementation of the control laws within the DSP: It is critical that the control laws are implemented accurately to maintain the desired system performance.
• Construction of PWM signals using control laws: PWM signals are essential for effective hardware control.
• Reception of PWM signals in the RTDS: Correct reception and processing in the RTDS allows for the validation of the performance of the simulated system.

4.4. Analog I/O Path and DSP Integration

The signals acquired from the RTDS comprise the source-side currents and the grid-side voltages in the three-phase schematic. These are transmitted to the GTAO card. Upon measurement with an oscilloscope, an offset was detected, prompting the decision to attenuate it within the simulation. To comply with the development board’s security protocols, the signals were also constrained to a 0–$3\mathrm{V}$ range. Once correctly configured, it is possible to adjust various parameters in the software’s analog output block, including scaling, oversampling, and delay [19]. As shown in Figure 7, this process uses the voltage and current signals from the inverter in Figure 6 during real-time simulation. These signals, normalized to per-unit system, allow scaling within the DSP, enabling more effective control of system variables. After computing the phase and modulation amplitude for PWM generation, the control outputs the pulses through the DSP digital channels to the GTDI card, regulating the inverter in simulation. Analog inputs in Figure 7 are configured to ensure that changes to control reference variables do not affect the DSP analog output.

4.5. Timing and Delay Compensation

Several key factors must be considered. Delays from the GTAO board output are critical, as they can impair PLL synchronization and control precision. Even with concurrent system initiation, GTAO delays hinder accurate phase synchronization without a PLL. This highlights the importance of accounting for delays in systems requiring precise synchronization. Proper DSP-based control implementation in real-time simulation depends on all these aspects. These considerations are essential to ensure fidelity and performance.

5. Results

5.1. Test Bench and Operating Conditions

This section presents the results of the CHIL implementation of the inverter with the LCL filter. The plant is modeled in RTDS and the control is executed on a DSP F28379D, closing the loop using CHIL. As a preliminary validation, Model-in-the-Loop (MIL) simulations of the plant and controller are performed entirely in RSCAD/RTDS, without hardware or physical I/O, in two variants: averaged model and switched model of the converter. Based on this, the CHIL simulation is run with the switched model in RTDS and the control in the DSP. Then, the impedance response of the grid side obtained in CHIL is compared with the small-signal analytical model and the MILs, considering different scenarios of short-circuit capacity (SCC) and short-circuit ratio (SCR). Finally, the sensitivity of the CHIL signals with respect to the time step used in the RTDS is analyzed. All cases use the same three-phase inverter parameters and control laws. The control hardware operates with a sampling period of $30\mathsf{\mu }$s, a phase margin of ${60}^{\circ }$, and an approximate bandwidth of 75 Hz, in accordance with previously established guidelines.

The LCL filter parameters are listed in

Table 1. System parameters.

Parameter	Scenario 1	Scenario 2	Scenario 3
SCC	5 MVA	2.5 MVA	1 MVA
$L_c$	3.54 $\mathrm{mH}$	3.52 $\mathrm{mH}$	2.8 $\mathrm{mH}$
$L_g$	2.37 $\mathrm{mH}$	7.93 $\mathrm{mH}$	2.15 $\mathrm{mH}$
$R_d$	5.09 $\Omega$	4.88 $\Omega$	5.67 $\Omega$
C	13.5 $\mathsf{\mu }$F	13.88 $\mathsf{\mu }$F	15 $\mathsf{\mu }$F
$K_{p_{dq}}$	2.99	2.86	2.51
$K_{i_{dq}}$	105.22	110.11	125.08
$SCR$	50	25	10

. The system operates at 60 Hz with a switching frequency of 2340 Hz. The inverter delivers 100 kVA to a 690 V grid. PLL gains were set to $K_{p_{pll}}=12.25$ and $K_{i_{pll}}=1950$, and filter resistances $R_c$ and $R_g$ were both 0.1 $\Omega$. Table 1 also includes three grid scenarios with different short-circuit capacities to assess performance under varying grid strengths.

5.2. Preliminary MIL and CHIL Validation

Figure 8a,b illustrate the dynamics of the voltage and current signals in the $dq$ scheme of the RTDS implementation of the average model; since it is an average model, no oscillations due to switching or other factors that may affect the system are observed. Note that $V_d=1.0203\mathrm{pu}$ and $V_q$ = 7.5885 $\times {10}^{-6}\mathrm{pu}$.

Figure 9a,b represent the voltage and current signals in the $dq$ scheme of the implementation of the switched model in RTDS; in this case, oscillations related to the switching of the PWM implemented in the system can be observed. To evaluate the performance of the model acurately, the root mean square error (RMSE) is computed for a steady state condition. The switched model achieves an RMSE of 0.0078 for the d axis and 0.0088 for the q axis. Similarly, for the currents, the RMSE reaches 0.0006 for both the d and q axes.

In the previous cases, the control laws were implemented within the same simulator. In Figure 10a,b, the dynamics of the voltage and current signals in the $dq$ scheme were derived from the real-time simulation of the switched model, which incorporates the controller within the DSP and transmits PWM signals to the RTDS through the GTDI. For this scenario, the RMSE is calculated, yielding 0.0133 and 0.0095 for the d- and q-axis voltages, and 0.0089 and 0.0074 for the d- and q-axis currents. The analysis reveals that modeling under the CHIL concept is accurate, with a maximum error of 1.33% in the worst case.

5.3. Frequency Response Comparison

Impedance response is crucial for characterizing the operation and control of grid-connected converters [20,21]. A comprehensive evaluation of the CHIL setup with RTDS and a DSP card is conducted by comparing the impedance obtained via the perturbation method against that computed by the RTDS impedance computation module. This comparison employs the analytical model given by Equation (5) as a baseline. Three environments are assessed: (i) the analytical model, integrating the full set of differential equations; (ii) an MIL case, with plant and control running in RTDS; and (iii) a CHIL case, with the plant in RTDS and the controller on a DSP. In CHIL, three RTDS time steps ($14\mathsf{\mu }\mathrm{s}$, $20\mathsf{\mu }\mathrm{s}$, and $30\mathsf{\mu }\mathrm{s}$) are analyzed to quantify step-size effects and contextualize performance relative to the analytical model and MIL. All cases use a switching frequency of $2340\mathrm{Hz}$, with sampling times chosen to avoid missing PWM pulses. The model controlled by the development board (red circles) is compared with the analytical method (blue) and the RTDS implementation (purple circles). This comparison highlights differences in impedance response between the CHIL implementation and the other methods. Results show that, although all methods yield similar responses under ideal conditions, differences emerge under varying conditions. These indicate that CHIL may offer advantages in terms of stability and efficiency.As shown in Figure 11, the CHIL response is more accurate than that obtained with the control laws implemented in the RTDS.

As illustrated in

Table 2. RMSE per d-q element of $Z_s$, comparing analytical model with MIL and CHIL simulations (SCC = 5 MVA, $f\ge 100$ Hz).

Channel	RMSE MIL Simulation	RMSE CHIL Simulation
$dd$	1.8147	0.67422
$dq$	4.0676	4.1725
$qd$	1.1361	1.4164
$qq$	3.264	3.7677

, CHIL and MIL yield analogous RMSEs. CHIL demonstrates the lowest error in the $dd$ channel, while in $dq$, $qd$, and $qq$, its RMSE is slightly higher than that of MIL. The RMSE was calculated in relation to the analytical model using only samples with frequencies greater than 100 Hz to mitigate low-frequency bias.

Further analysis is recommended to explore the practical implications of these results. Having compared frequency responses across different simulation types—and confirmed that the CHIL approach performs best, as seen in Figure 12, 14, and 16—an additional test was performed by increasing the RTDS simulation time step while keeping the DSP clock fixed at $30\mathsf{\mu }\mathrm{s}$. In Figure 12, the same system is compared, but changes $T_s$ in the simulation within RTDS. As the time step increases, the response of the system remains the same, suggesting that, within this range of sampling times, the system is robust and is not significantly affected by changes in $T_s$.

Figure 13 presents a comparison of the frequency responses derived from simulations executed with a system possessing a short-circuit capacity of 2.5 MVA. The data acquired from the CHIL simulation indicate that the system’s response remains satisfactory despite variations in short-circuit capacity.

Table 3. RMSE per d-q element of $Z_s$, comparing the analytical model with MIL and CHIL simulations (SCC = 2.5 MVA, $f\ge 100$ Hz).

Channel	RMSE MIL Simulation	RMSE CHIL Simulation
$dd$	1.7644	0.66472
$dq$	3.8537	3.776
$qd$	3.1528	3.3321
$qq$	1.162	1.4195

summarizes the RMSE between the analytical model and the MIL/CHIL simulations for a network with an SCC of $2.5$ MVA. Overall, MIL and CHIL are comparable: CHIL achieves the lowest error in the $dd$ channel, whereas its RMSE is slightly higher than that of MIL in $dq$, $qd$, and $qq$.

In Figure 14, it can be seen that the system maintains the same dynamics despite the large changes in $T_s$ and short-circuit capacity. This consistency suggests that the system is robust and capable of adapting to various operating conditions without compromising its performance.

Finally, a comparison of the system with an SCC of 1 MVA is carried out. In Figure 15 and Figure 16, values very similar to those obtained earlier are obtained. Considering this, compared to the average model, the values obtained are stable and do not show abrupt changes when varying $T_s$.

Table 4. RMSE per d-q element of $Z_s$ comparing analytical model with MIL and CHIL simulations (SCC = 1 MVA, $f\ge 100$ Hz).

Channel	RMSE MIL Simulation	RMSE CHIL Simulation
$dd$	1.8432	1.7482
$dq$	4.1207	3.7659
$qd$	1.205	2.4042
$qq$	3.2756	4.764

summarizes the RMSE between the analytical model and the MIL and CHIL simulations for a network with SCC = 1.0 MVA. In general, the performance is comparable. In the $dq$ element, CHIL has a smaller error than MIL. In $dd$, CHIL is slightly inferior to MIL, while in $qd$ and $qq$, it is considerably superior. These figures quantify the difference in performance per element in the d-q framework.

Modifying the simulation time step alters the delay in the CHIL setup. Each compilation introduces a fixed delay of 9.203 $\mathsf{\mu }$s for signal transmission (GTAO to DSP) and 1.433 $\mathsf{\mu }$s for DSP processing and feedback (GTDI). These delays slightly affect the system response, as illustrated in Figure 12, Figure 14, and Figure 16.

6. Conclusions

Real-time simulators such as Typhoon, RTDS, Opal-RT, and dSPACE are widely used in power system analysis and testing due to their ability to simulate dynamic systems in real time. These simulators differ significantly in terms of accuracy and communication delays, which makes them suitable for various types of analyses. The main objective of this paper was to implement CHIL using a digital signal processor in a real-time simulation of a three-phase inverter interconnected to the grid. After the validation of the system response under the implemented control, a software tool was used to obtain the frequency responses. In general terms, the simulations performed were satisfactory, since the voltage and current signals showed a behavior in accordance with the theoretical expectations. Likewise, the frequency responses obtained from the average model and the real-time switched model showed consistent results, close to the values predicted by the analytical model. Comparison of results of the implementation of the control by means of the DSP allows us to demonstrate that the implementation of CHIL presents some differences in the impedance response in comparison with the other methods. However, the response of the CHIL implementation is the most accurate of the three approaches, since the DSP and its control are not just a model, but constitute a real device with its control implemented. This even considers the accuracy and speed limitations of the DSP, as well as the error introduced by control discretization and communication challenges. Our findings demonstrate that the CHIL approach with control implemented on a DSP accurately reproduces real dynamics by incorporating practical limitations on computational precision and speed, control discretization, and communication latencies. The comparison using RMSE against the analytical model shows that, although CHIL has lower error than MIL in several bands and channels, in other scenarios, the error increases. These discrepancies are attributed to quantization effects, unwanted sampling noise, and I/O delays. Despite this, when taking MIL as a reference and considering the positive correlation between the frequency responses of the averaged and switched models with the analytical formulation, the overall performance is deemed satisfactory.