Search Results (56)

The increasing computational demands of deep neural network inference drive the need for energy-efficient hardware accelerators that minimize data movement between memory and processing units. Compute-in-memory (CIM) architectures address this bottleneck by embedding computation directly within memory arrays, reducing the overhead of repeated weight transfers in conventional von Neumann systems. Conventional 6T SRAM-based digital CIM bitcells incur significant transistor overhead as arrays scale, motivating exploration of reduced-transistor bitcell alternatives. We propose a compact 4T+2T SRAM-based digital CIM bitcell implemented in 45 nm CMOS, combining a 4T SRAM storage cell with a 2T multiplier for bitwise multiply-and-accumulate (MAC) operations. The proposed design reduces transistor count from 8 to 6 compared to the 6T+2T reference, lowering parasitic capacitance and hardware overhead without compromising memory or computation functionality. Transient simulations confirm correct write, read, and CIM operations. The bitcell achieves a read delay of 26.91 ps, read power of 1.351 nW, and read energy of 0.005403 fJ—reductions of 98.7%, 86.5%, and 73.1% over the 6T+2T reference, respectively. For CIM operation, bitwise multiplication power decreases from 1.772 µW to 0.8014 µW and energy from 10.63 fJ to 4.808 fJ, representing a 54.8% reduction in both metrics, with only a marginal CIM delay increase of 3.13 ps. Monte Carlo analysis across 100 samples confirms robust write behavior under process variation, with write delay ranging from 55.02 to 69.59 ps and write energy from 0.05870 to 0.06557 fJ. Static noise margin analysis yields an SNM of 83.7 mV under nominal conditions, confirming stable data retention. These results demonstrate that the proposed 4T+2T bitcell offers strong transistor efficiency, energy savings, and computational correctness, making it a promising candidate for area-efficient digital CIM architectures targeting edge AI inference. Full article

This paper presents a behavioral-level, pre-silicon analytical co-design framework for memristor read–write interfaces, intended to establish closed-form design rules that subsequently guide SPICE-level and silicon-level realizations. Memristor-based neural hardware requires interfaces that can program resistance states efficiently while suppressing read disturbance, yet existing designs typically rely on empirical tuning without closed-form analytical rules. We close this gap by deriving a single closed-form operating-window inequality $(v_{\mathrm{on}}<V_{\mathrm{rd}}<v_{\mathrm{off}},V_{\mathrm{wr}}\ge V_{\mathrm{wr}}^{min}\left(T_{\mathrm{wr}}\right))$ from the VTEAM state equation, embedding it in an Energy–Delay–Accuracy (EDA) cost function, and validating the resulting parameter set hierarchically up to MNIST-scale inference. The main finding is that this analytically derived parameter set simultaneously achieves a 96.08% set-cycle energy saving and 90.6% MNIST top-1 accuracy (1.2% below software baseline) under realistic D2D/C2C variability, with every measured number agreeing with its analytical prediction within 2%. The framework is instantiated with a two-phase over-threshold-write and sub-threshold-read timing strategy together with a mutually exclusive PMOS-NMOS path-isolation topology, evaluated through behavioral-level MATLAB simulation under linear-drift and VTEAM models. Behavioral simulation confirms each analytical bound within 2%: a 13.78× resistance window with $\le 0.008\%$ cycle-to-cycle drift, 5.01% read-current CV, and 30.94%/96.08% Reset/Set energy savings versus a no-separation baseline. Transistor-level non-idealities (slew rate, charge injection, RTN, retention aging, peripheral overhead) are bounded analytically; full SPICE/silicon validation is identified as immediate follow-up work. These results establish a reusable, analytically grounded reference design that bridges memristive device modeling, circuit-level interface implementation, and neural network-level usability. Full article

Internet of Things (IoT) nodes continuously acquire, buffer, and transmit sensor data under strict constraints on area, latency, and energy consumption. However, conventional complementary metal–oxide–semiconductor (CMOS)-based memory-access circuits face increasing power loss, parasitic effects, interconnect complexity, and sensitivity to process variations at the nanoscale. To address these limitations, this paper proposes a quantum-dot cellular automata (QCA)-based decoder-driven static random-access memory (SRAM)-access architecture for compact and energy-efficient IoT perception-layer memory. The proposed framework integrates three main components: a majority-logic RAM cell with feedback-based storage and non-destructive readout, a compact 2 × 4 decoder with enable and auxiliary asynchronous set/reset control, and a 1 × 4 SRAM array in which the decoder is embedded to reduce routing and clocking overhead. The circuit layouts were implemented and functionally verified using QCADesigner 2.0.3, while the energy behavior was evaluated using QCADesigner-E. Simulation results confirm correct write/read (W/R) and address-selection behavior. The proposed 2 × 4 decoder achieves 86 QCA cells, 0.08 µm² occupied area, and one clocking unit, reducing cell count, area, and clocking by 48.19%, 50.00%, and 20.00%, respectively, compared with the best selected decoder baseline. The integrated 1 × 4 SRAM array achieves 684 cells and 14 clocking units, improving timing by 30.00% compared with the closest SRAM-array baseline. These results demonstrate that the proposed QCA-based memory-access structure provides a compact and low-overhead solution for energy-constrained IoT communication systems. Full article

With the continuous growth of data-intensive applications and artificial intelligence workloads, traditional dynamic random access memory (DRAM) is increasingly struggling to meet demands in terms of capacity scale, energy consumption constraints, and data retention after power failure. Consequently, non-volatile memory (NVM) has emerged as a crucial technology for bridging the gap between the memory and storage layers. However, due to inherent differences in write life, read–write performance variations, and consistency guarantee after failure, the systematic application of NVM still faces a series of challenges. Addressing these issues, this paper takes as its starting point the adaptation of medium characteristics and system design, and summarizes the research progress in aspects such as write optimization, consistency and security coordination mechanisms, data structure modification under hybrid memory architecture, and cross-layer resource collaboration. It also conducts an in-depth analysis of representative solutions and evaluation methods. The review results show that current research has shifted from improving a single performance bottleneck to multi-mechanism collaborative optimization. Various technical approaches have proven complementary in alleviating write amplification, enhancing persistence efficiency, and optimizing access patterns. This paper demonstrates that achieving stable and scalable application of NVM requires establishing a more systematic collaborative design concept between durability, security, and performance. As AI training workloads and big data analytics place increasing demands on memory bandwidth and persistence, the techniques surveyed here provide a foundational basis for next-generation memory-centric computing infrastructures. Full article

Due to the Von Neumann bottleneck of traditional CMOS computing, there is an urgent need to develop in-memory logic devices with low power consumption. In this work, we demonstrate ferroelectric diode devices based on the TiN/Hf_0.5Zr_0.5O₂/HfO₂/TiN structure, implementing 16 Boolean logic operations through single-step or multi-step (2–3 steps) cascade and achieving attojoule-level one-bit full-adder computation. The TiN/Hf_0.5Zr_0.5O₂/HfO₂/TiN ferroelectric diode exhibits non-destructive readout and bidirectional rectification characteristics, with the conduction mechanism following Schottky emission behavior in the on-state. Based on its bidirectional rectification characteristics, we designed and simulated the circuit scheme of 16 Boolean logic and one-bit full-adder through cascaded operations. Both the input and output logic values are represented in the form of resistance, without the need for additional form conversion circuits. The state writing is performed by pulse-controlled polarization flipping, and the state reading is non-destructive. The logic circuits in this work demonstrate superior performance with ultralow computing power consumption in simulation. This breakthrough establishes a foundation for developing energy-efficient and scalable in-memory computing systems. Full article

In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D voltage plane for aging simulation of SRAM circuits. According to the physical mechanism of failure, based on the reaction–diffusion and hot carrier energy-driven theory, revised degradation models of threshold voltage shift (∆Vth) for the NBTI and HCD are established, respectively, with explicit expressions for gate voltage (V_G)/drain voltage (V_D). An NBTI/HCD coupling model is built on the 2-D {V_G, V_D} voltage plane with a weighting factor in the form of V_G and V_D power law. The model also takes into account the AC effect and long-term saturation behavior. The predicted ∆Vth under various stress conditions shows an average relative error of 11.6% with experimental data across the entire bias space. SRAM circuit simulation shows that the read static noise margin (RSNM) and write static noise margin (WSNM) have a maximum absolute error of 4.2% and 3.1%, respectively. This research provides a valuable reference for the reliability simulation of nanoscale integrated circuits. Full article

This paper reads coal as a metonym for London’s social fabric in the writings of police theorist Patrick Colquhoun, the archival reports on the Wapping Coal Riot, and the anti-carceral poetry of William Blake. In 1798, at the behest of the West India Committee, Colquhoun had developed the first modern police force, the Thames River Police, which predated Robert Peel’s metropolitan police by over 20 years. Colquhoun’s “Treatise on the Commerce and Police of the River Thames” (1800) centers on coal in his case for policing. In his argument, coal’s energy economies link domestic affairs with the entire metropolis, making policing a city-wide problem, one that merits public support (and public funding). In reading Colquhoun’s treatise as an example of the entanglement of policing and fossil fuel power, I discuss the relevant literature from the energy humanities that connects fossil energy to the larger extractive ideologies of empire. I also demonstrate how Colquhoun’s figuring of coal builds on but alters portrayals of coal in Jonathan Swift and Anna Barbauld. The final section of this discussion demonstrates how Blake’s Jerusalem (1820) indexes dispersed, atmospheric systems of carceral power and summons dynamic, unpoliceable crowds. Blake’s smoke poetics sketch a limit of generalization, one that recoups figures of pollution and waste to riot against the systems that produce them. Full article

Resource-constrained sensor nodes in Internet-of-Things (IoT) and embedded sensing applications frequently rely on low-cost microcontrollers, where even basic algorithmic choices directly impact latency, energy consumption, and memory footprint. This study evaluates six sorting algorithms—Bubble Sort, Insertion Sort, Selection Sort, Merge Sort, Quick Sort, and Heap Sort—in the restricted environment that microcontrollers provide. Three Arduino boards were used: Arduino Uno, Arduino Leonardo, and Arduino Mega 2560. Each algorithm was implemented in its unoptimized form and tested on datasets of increasing size, emulating buffered time-series sensor readings in random, ascending, and descending order. Execution time, number of write operations, and memory usage were measured. The tests show clear distinctions between the slower $O\left(n^2\right)$ algorithms and the more efficient $O(nlogn)$ algorithms. For random inputs of $n=1000$ elements, Bubble Sort required 1,958,193.75 $\mathsf{\mu }$son average, whereas Quick Sort completed it in 54,260.50 $\mathsf{\mu }$s and Heap Sort in 92,429.00 $\mathsf{\mu }$s, i.e., speedups of more than one order of magnitude compared to the quadratic baseline. These gains, however, come with very different memory footprints. Merge Sort kept the runtime below 100,000 $\mathsf{\mu }$s at $n=1000$ but required approximately 2023 bytes of additional static random-access memory (SRAM), effectively exhausting the 2 kB SRAM of the Arduino Uno. QuickSort used approximately 311 bytes of extra SRAM and failed to process larger ascending and descending datasets on the more constrained boards due to its recursive pattern and stack usage. Heap Sort offered the best overall trade-off: it successfully executed all tested sizes up to the SRAM limit of each board while using only about 12–13 bytes of additional SRAM and keeping the runtime below 100,000 $\mathsf{\mu }$s for $n=1000$. The results provide practical guidelines for selecting sorting algorithms on 8-bit AVR Arduino-class microcontrollers, which are widely used as simple sensing and prototyping nodes operating under strict RAM, program-memory, and energy constraints. Full article

With continued CMOS scaling, transistor miniaturization has significantly raised SRAM integration density while lowering the critical charge (Qc), increasing cell vulnerability to spaceborne high-energy particles. Single-event upset (SEU) and especially single-event multiple node upsets (SEMNU) due to charge sharing present major reliability challenges. To overcome these issues, this study introduces a radiation-hardened 20T SRAM cell with read/write optimization (RWO-20T) designed for space applications. Benchmarking against hardened cells RH14T, RHSCC16T, S8P8N16T, and CC18T reveals that RWO-20T delivers superior read static noise margin (RSNM), increased word-line write trip voltage (WWTV), and faster read and write access times. Although the higher transistor count incurs some area overhead and slightly lowers the hold static noise margin (HSNM), RWO-20T achieves improved recovery rates for dual-node upsets (DNU) and triple-node upsets (TNU) under SEMNU conditions. The circuits were simulated in a 90 nm CMOS process and operated at 1 V. Full article

In space, high-energy particle radiation poses a serious threat to the data stability and reliability of SRAM. Existing radiation-tolerant techniques, such as Triple Modular Redundancy (TMR) and Error Correction Code (ECC), have disadvantages such as large area, high power consumption, and additional delay, making them unsuitable for small satellite systems. To overcome these limitations, this paper proposes a 16-transistor-based radiation-tolerant SRAM cell, WRTU-16T, which applies a read-decoupled structure and a charge-sharing suppression mechanism. The proposed structure effectively isolates the storage node from external disturbances and improves the recovery capability for single-event inversion (SEU) and multiple-node inversion (SEMNU) by reducing charge loss. WRTU-16T shows superior performance in terms of write delay, charge recovery capability (Qc), hold power, and word line write threshold voltage (WWTV) compared to existing radiation-tolerant SRAM designs. The integrated circuit is implemented using a 90 nm CMOS process and has an operating voltage of 1V. Full article

Gamma-Ray Bursts(GRBs) are the most violent and energetic astrophysical phenomena, which I dare call “the Energy Monsters of the Universe”. Indeed, they show an enormous emitted isotropic energy ranging from ∼3 × ${10}^{46}$ erg (GRB 170817A) to ∼${10}^{55}$ erg (GRB 221009A) and a duration ranging from ≈milliseconds to ∼${10}^4$ s. In this review—which I agreed to write as a scientist not directly involved in the field of GRBs—I will present the history of GRBs from the time of their discovery by chance until the new era whose beginning was marked by the detection of gravitational waves coming from the merger of two neutron stars. I will discuss the experimental results and their physical interpretation, which is still a source of heated debate within the scientific community. Due to the reasonable length of this review and especially given my limited knowledge, I do not claim to have exhausted the complicated topic of GRBs, but to have contributed in making this subject easy to read for non-experts, providing a critical contribution that is hopefully useful to the whole community. Full article

We propose dependency reduction techniques for the performance enhancement of the Hyperledger Fabric blockchain. A dependency hazard may result from the parallelism in Hyperledger Fabric, which executes multiple transactions simultaneously in a single block. Since multiple transactions in a block are executed in parallel for throughput enhancement, dependency problems may arise among transactions involving the same key (If Z = A + D is executed in parallel with A = B + C, a read-after-write hazard for A will occur). To address these issues, our scheme proposes a transaction dependency checking system that integrates a dependency-tree-based management approach to dynamically prioritize transactions based on factors such as the tree level, arrival time, and starvation possibility. Our scheme constructs a dependency tree for transactions in a block to be executed in parallel over multiple execution units. We rearrange the transactions into blocks in such a way that the dependency among the transactions are removed as far as possible. This allows parallel execution of transactions to be performed without collision, enhancing the throughput against the conventional implementation of Hyperledger Fabric. Our illustrative implementation of the proposed scheme in a testbed for trading renewable energy shows a performance improvement as big as 27%, depending on the input mixture of transactions. A key innovation is the introduction of the Starve-Avoid method, which mitigates data starvation by dynamically adjusting the transaction priorities to balance throughput and fairness, ensuring that no transaction experiences indefinite delays. Unlike existing approaches that require structural modifications to the conventional Hyperledger Fabric, the proposed scheme optimizes the performance as an independent module, maintaining compatibility with the conventional Hyperledger Fabric architecture. Full article

As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. This has led to a reduction in the critical charge of sensitive nodes, making the SRAM cells more susceptible to soft errors. When high-energy particles in space strike the sensitive nodes of an SRAM cell, a single-event upset (SEU) can occur, altering the stored data. Additionally, the charge-sharing effect between transistors can cause single-event multi-node upsets (SEMNUs). To address these challenges, this paper proposes a radiation-hardened 16T SRAM cell optimized for stability and power, referred to as RHSP16T. The performance of the proposed RHSP16T cell was compared with other radiation-hardened SRAM cells, including QUC-CE12T, WE-QUATRO, RHBD10T, RHD12T, and RSP14T. Simulation results indicate that the proposed RHSP16T cell exhibits higher read and write stability, along with lower-leakage power consumption. compared with all other cells. This demonstrates that RHSP16T ensures high reliability for stored data. Furthermore, EQM results show that the RHSP16T cell outperformed the compared designs in overall SRAM cell performance. The proposed integrated circuit was implemented in a 90 nm CMOS process and operated on 1 V supply voltage. Full article

Reconfigurable processor-based acceleration of deep convolutional neural network (DCNN) algorithms has emerged as a widely adopted technique, with particular attention on sparse neural network acceleration as an active research area. However, many computing devices that claim high computational power still struggle to execute neural network algorithms with optimal efficiency, low latency, and minimal power consumption. Consequently, there remains significant potential for further exploration into improving the efficiency, latency, and power consumption of neural network accelerators across diverse computational scenarios. This paper investigates three key techniques for hardware acceleration of sparse neural networks. The main contributions are as follows: (1) Most neural network inference tasks are typically executed on general-purpose computing devices, which often fail to deliver high energy efficiency and are not well-suited for accelerating sparse convolutional models. In this work, we propose a specialized computational circuit for the convolutional operations of sparse neural networks. This circuit is designed to detect and eliminate the computational effort associated with zero values in the sparse convolutional kernels, thereby enhancing energy efficiency. (2) The data access patterns in convolutional neural networks introduce significant pressure on the high-latency off-chip memory access process. Due to issues such as data discontinuity, the data reading unit often fails to fully exploit the available bandwidth during off-chip read and write operations. In this paper, we analyze bandwidth utilization in the context of convolutional accelerator data handling and propose a strategy to improve off-chip access efficiency. Specifically, we leverage a compiler optimization plugin developed for Vitis HLS, which automatically identifies and optimizes on-chip bandwidth utilization. (3) In coefficient-based accelerators, the synchronous operation of individual computational units can significantly hinder efficiency. Previous approaches have achieved asynchronous convolution by designing separate memory units for each computational unit; however, this method consumes a substantial amount of on-chip memory resources. To address this issue, we propose a shared feature map cache design for asynchronous convolution in the accelerators presented in this paper. This design resolves address access conflicts when multiple computational units concurrently access a set of caches by utilizing a hash-based address indexing algorithm. Moreover, the shared cache architecture reduces data redundancy and conserves on-chip resources. Using the optimized accelerator, we successfully executed ResNet50 inference on an Intel Arria 10 1150GX FPGA, achieving a throughput of 497 GOPS, or an equivalent computational power of 1579 GOPS, with a power consumption of only 22 watts. Full article

The increasing demand for cleaner and more sustainable energy sources has sparked significant interest in small modular reactors (SMRs). Due to their compact and modular design, SMRs pose unique challenges in radiation shielding, requiring a more refined approach. This study focuses on developing a new variance reduction technique (VRT) for radiation shielding analysis, specifically tailored for SMRs, to address the limitations of traditional methods such as surface source write/surface source read (SSW/SSR). The proposed VRT supports multi-threading and enhances computational efficiency by redefining source particles using a two-step method. The analysis is conducted using the Monte Carlo radiation transport code, MCNP6, and the effectiveness of the new VRT is evaluated through sensitivity analyses across various energy and directional divisions. Full article