MDPI - Publisher of Open Access Journals

18 pages, 6121 KiB

Open AccessArticle

A 640 nA I_Q Output-Capacitor-Less Low Dropout (LDO) Regulator with Sub-Threshold Slew-Rate Enhancement for Narrow Band Internet of Things (NB-IoT) Applications

by Yuxin Zhang, Jueping Cai, Jizhang Chen and Yixin Yin

Micromachines 2024, 15(8), 1019; https://doi.org/10.3390/mi15081019 - 9 Aug 2024

Viewed by 1321

Abstract

An ultra-low quiescent current output-capacitor-less low dropout (OCL-LDO) regulator for power-sensitive applications is proposed in this paper. To improve the gain of the OCL-LDO feedback loop, the error amplifier employs a combination of a cross-coupled input stage for boosting the equivalent input transconductance and a negative resistance technique to improve the gain. Meanwhile, in order to address the issue of transient response of the ultra-low quiescent current OCL-LDO, a sub-threshold slew-rate enhancement circuit is proposed in this paper, which consists of a transient signal input stage and a slew-rate current increase branch. The proposed OCL-LDO is fabricated in a 0.18

μ

m CMOS process with an effective area of 0.049 mm². According to the measurement results, the proposed OCL-LDO has a maximum load current of 100 mA and a minimum quiescent current of 640 nA at an input voltage of 1.2 V and an output voltage of 1 V. The overshoot and undershoot voltages are 197 mV and 201 mV, respectively, and the PSR of the OCL-LDO is −72.4 dB at 1 kHz when the load current is 100

μ

A. In addition, the OCL-LDO has a load regulation of 7.6

μ

V/mA and a line regulation of 0.87 mV/V. Full article

(This article belongs to the Section D1: Semiconductor Devices)

► Show Figures

Figure 1

13 pages, 3838 KiB

Open AccessArticle

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

by Yongkai Ning, Jiangfei Guo, Yangchen Jia, Duosheng Li and Guiliang Guo

Electronics 2023, 12(19), 4067; https://doi.org/10.3390/electronics12194067 - 28 Sep 2023

Viewed by 2312

Abstract

A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1

μ

s edge time, [...] Read more.

μ

s edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2

μ

s and 1.6

μ

s, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm

^{2}

(without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/

^{\circ}

C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz. Full article

► Show Figures

Figure 1

13 pages, 9140 KiB

Open AccessArticle

A Low-Power, Fast-Transient FVF-Based Output-Capacitorless LDO with Push–Pull Buffer and Adaptive Resistance Unit

by Yuanzhe Li, Lixin Wang, Yue Wang, Shixin Wang, Mengyao Cui and Min Guo

Electronics 2023, 12(6), 1285; https://doi.org/10.3390/electronics12061285 - 8 Mar 2023

Cited by 6 | Viewed by 4803

Abstract

An output-capacitorless low-dropout regulator (LDO) with a push–pull buffer was presented in this paper. The proposed push–pull buffer was able to provide a large charge and discharge current to increase the slew rate at the gate of the power transistor effectively, thereby improving the transient response of this LDO. In addition, an adaptive resistance unit (ARU) was proposed to solve the right half-plane zero problem caused by Miller compensation to optimize the loop stability of the LDO. The proposed LDO was implemented in a 0.18-µm CMOS technology. Simulation results showed that the quiescent current of this LDO was only 16.1 µA. It regulated the output at 1.5 V from a 1.8 V supply, with a dropout voltage of 300 mV at the maximum output current of 50 mA. The maximum value of the voltage spike was 129 mV. Additionally, the recovery time of the LDO was 0.2 µs. Full article

► Show Figures

Figure 1

12 pages, 6529 KiB

Open AccessArticle

An Output-Capacitorless Low-Dropout Regulator with Slew-Rate Enhancement

by Shenglan Ni, Zhizhi Chen, Chenkai Hu, Houpeng Chen, Qian Wang, Xi Li, Sannian Song and Zhitang Song

Micromachines 2022, 13(10), 1594; https://doi.org/10.3390/mi13101594 - 25 Sep 2022

Cited by 5 | Viewed by 3048

Abstract

A novel output-capacitorless low-dropout regulator (OCL-LDO) with an embedded slew-rate-enhancement (SRE) circuit is presented in this paper. The SRE circuit adopts a transient current-boost strategy to improve the slew rate at the gate of the power transistor when a large voltage spike at the output is detected. In addition, a feed-forward transconductance cell is introduced to form a push–pull output structure with the power transistor. The simulation results show that the maximum transient output voltage variation is

23.5 mV

when the load current

I_{L O A D}

is stepped from

0

100 mA

100 ns

with a load capacitance of

100 pF

, and the settling time is

1.2 μ s

. The proposed OCL-LDO consumes a quiescent current of

30 μ A

and has a dropout voltage of

200 mV

for the maximum output current of

100 mA

. Full article

► Show Figures

Figure 1

13 pages, 5890 KiB

Open AccessArticle

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

by Yange Lu, Ming Chen, Kunyu Wang, Yanjun Yang and Haiyong Wang

Electronics 2022, 11(19), 3009; https://doi.org/10.3390/electronics11193009 - 22 Sep 2022

Cited by 5 | Viewed by 6103

Abstract

The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively. Full article

(This article belongs to the Special Issue Design of CMOS Integrated, Circuits and Systems for Wireless Communications)

► Show Figures

Figure 1

15 pages, 51449 KiB

Open AccessArticle

A Low-Power, Fast-Transient Output-Capacitorless LDO with Transient Enhancement Unit and Current Booster

by Yongchao Jiang, Lixin Wang, Shixin Wang, Mengyao Cui, Zhuoxuan Zheng and Yuanzhe Li

Electronics 2022, 11(5), 701; https://doi.org/10.3390/electronics11050701 - 24 Feb 2022

Cited by 10 | Viewed by 4767

Abstract

With the wide application of advanced portable devices, output-capacitorless low dropout regulators (OCL-LDO) are receiving increasing attention. This paper presents a low quiescent current OCL-LDO with fast transient response. A transient enhancement unit (TEU) is proposed as the output voltage-spike detection circuit. It enhances the transient response by improving the slew-rate at the gate of the power transistor. In addition, a current booster (CB), which consists of a current subtractor and a non-linear current mirror, is designed to improve the slew-rate further. The current subtractor increases the transconductances of the differential-input transistors to obtain a large slewing current, while the non-linear current mirror further boosts the current with no extra quiescent current consumption. The simulated results show that the proposed OCL-LDO is capable of supplying 100 mA load current while consuming 10.3 μA quiescent current. It regulates the output at 1 V from a supply voltage ranging from 1.2 to 1.8 V. When the load current is stepped from 1 mA to 100 mA in 100 ns, the OCL-LDO has attained a settling time of 190 ns, and the output voltage undershoot and overshoot are controlled under 110 mV. Full article

(This article belongs to the Section Power Electronics)

► Show Figures

Figure 1

13 pages, 4013 KiB

Open AccessArticle

An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

by Jihoon Park, Woong-Joon Ko, Dong-Seok Kang, Yoonmyung Lee and Jung-Hoon Chun

Energies 2019, 12(2), 211; https://doi.org/10.3390/en12020211 - 10 Jan 2019

Cited by 9 | Viewed by 6838

Abstract

An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process. Full article

► Show Figures

Figure 1

Search Results (7)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

Saved Queries

Search Filter Reset All

Years

Feature Papers

Subjects

Journals

Article Types

Countries / Regions

Search Results (7)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI