A Low-Power, Fast-Transient FVF-Based Output-Capacitorless LDO with Push–Pull Buffer and Adaptive Resistance Unit

Abstract

An output-capacitorless low-dropout regulator (LDO) with a push–pull buffer was presented in this paper. The proposed push–pull buffer was able to provide a large charge and discharge current to increase the slew rate at the gate of the power transistor effectively, thereby improving the transient response of this LDO. In addition, an adaptive resistance unit (ARU) was proposed to solve the right half-plane zero problem caused by Miller compensation to optimize the loop stability of the LDO. The proposed LDO was implemented in a 0.18-µm CMOS technology. Simulation results showed that the quiescent current of this LDO was only 16.1 µA. It regulated the output at 1.5 V from a 1.8 V supply, with a dropout voltage of 300 mV at the maximum output current of 50 mA. The maximum value of the voltage spike was 129 mV. Additionally, the recovery time of the LDO was 0.2 µs.

1. Introduction

Low-dropout (LDO) regulators are often used in power management mobile systems requiring small size and clean supply voltage. A traditional LDO always needs to connect a µF-level capacitor at its output pin to reduce output voltage spikes and ensure loop stability. However, with the miniaturization and portability of electronic equipment, the off-chip capacitance that occupies a large area is no longer allowed, so output capacitorless low-dropout regulator (OCL-LDO) recently became a new research direction [1,2,3,4,5,6,7,8,9].

There are many problems without the off-chip capacitor. The transient response problem is quite evident. When the load current suddenly decreases and the current supplied by the LDO does not have time to decrease accordingly, the excess current will charge the output voltage node, resulting in a rapid increase in the output voltage. This phenomenon is known as overshoot of the output voltage. Conversely, when the load current sharply increases, it will cause undershoot of the output voltage. Both overshoot and undershoot can cause instability in the LDO output voltage, which worsens the performance of the subsequent equipment; thus, suppressing voltage spikes caused by load changes has always been one of the main functions of the LDO [10,11,12,13,14,15,16]. Traditional LDOs tended to use large off-chip capacitors to suppress voltage spikes, while OCL-LDOs do not. In actuality, the transient response is dependent on a number of critical parameters such as the slew rate at the gate of the power transistor (SR_G) and the loop bandwidth (BW_L). The slew rate is a large-signal parameter related to the magnitude of the bias current, whereas the loop bandwidth involves small-signal parameters that significantly depend on the positions of the poles and the zeros in the feedback system.

Figure 1 shows one reported LDO structure used in [17,18,19,20,21,22] to enable OCL-LDO, the core for which was a flipped voltage follower (FVF). The advantages of FVF include low circuit complexity and short transient response loop in the case of small-signal response. However, if there is rapid and large change of load current (I_O), the output-capacitorless LDO will experience a large-signal response. At this point, the slew rate of each node in the transient response loop, especially the node at the gate of the power transistor, becomes the main limitation of the transient response of the OCL-LDO, and the slew rate of most nodes is limited by its quiescent current. As shown in Figure 1, when the output voltage rises suddenly, I_bias1 charges the gate capacitance of the power transistor, so the maximum charging current is equal to the bias current I_bias1, and, conversely, when the output voltage drops, (I_bias2-I_bias1) is the maximum discharge current at the gate of power transistor. However, due to the large area of the power transistor, there is a large parasitic capacitance at its gate, and a small quiescent current is not enough to charge this capacitance rapidly. However, if the quiescent current is increased, it will lead to an increase in power dissipation. Therefore, a new structure is needed to solve this problem. Man et al. [20] reported using dynamic biasing to solve this problem. In [20], the output voltage (V_OUT) was compared to the reference voltage (V_REF) by a common-gate amplifier. Additionally, in order to inject and withdraw more current for charging and discharging during the transient instant, a push–pull circuit was used as the output stage of this amplifier. However, this structure was limited by the narrow common-mode input range and bandwidth of the common-gate amplifier. More power was required for common-gate amplifiers to detect fast voltage spikes to improve transient response significantly. Another researcher used the replica transistor of the power transistor to provide additional bias current when the load current increases [23,24], but there was a large bias current through the circuit when the output current was maximum, resulting in unnecessary power dissipation. Furthermore, Park et al. [2] reported an external transient enhancement circuit to provide a temporary bias current by capacitive coupling. It could be used not only for FVF-based LDOs, but also in a variety of LDO circuits. However, limited by the coupled capacitance and the matching resistor, this method often does not balance the speed and accuracy of charge and discharge. According to the brief review, it was evident that a structure is needed which can burst out large charging and discharging currents when the load current changes rapidly. Therefore, this work uses a push–pull buffer to meet the transient response requirements.

In addition, frequency compensation is another problem for OCL-LDO. Due to the large off-chip capacitance, traditional LDOs tend to set the dominate pole at the output voltage node, while OCL-LDO does not. So, a node is selected inside the OCL-LDO as the dominate pole. The gate of the power transistor is well suited as a node for setting the main pole due to its large parasitic capacitance. In addition, Miller compensation is used to further improve its stability. However, relying only on parasitic capacitance, the frequency of the dominate pole is not low enough to ensure loop stability; so, Miller compensation is used to further improve its stability. However, Miller compensation creates a right half-plane zero point, which threatens the stability of the system; so, it is necessary to select a suitable zeroing resistor. In this paper, an adaptive resistor unit (ARU) is proposed as the zeroing resistor for Miller compensation, which optimizes the loop stability in the load range.

In this paper, Section 2 introduces the structure and principle of the FVF-based push-pull buffer. Section 3 presents the frequency compensation in this work and introduces the adaptive resistor unit. The simulation results are presented in Section 4. Finally, the conclusion of this paper is given.

2. Optimization of Transient Response

2.1. FVF-Based OCL-LDO

The LDO shown in Figure 1 was based on a flipped voltage follower (FVF) [25]. M_P is the power transistor, while M_C1 and M_C2 form a folded error amplifier in the common-gate configuration [20]. V_OUT, the output voltage, is controlled by a constant voltage source, V_CTRL, when the bias current through M_C1 is constant. V_OUT is given by:

$${\mathrm{V}}_{\mathrm{OUT}}={\mathrm{V}}_{\mathrm{CTRL}}+{\mathrm{V}}_{\mathrm{SG}1}$$

(1)

where V_SG1 is the source-to-gate voltage of M_C1. Moreover, the voltage source is generated by the control-voltage generator circuit in Figure 2. An operational amplifier consists of a differential amplifier and a common-source amplifier, and then, it is connected to a unity-gain amplifier. In this way, the reference voltage, V_REF, generated by the Bandgap circuit, is regenerated and has ability to drive the load consisting of M_C3 and quiescent current source I_DC. So, the control voltage, V_CTRL, is given by:

$${\mathrm{V}}_{\mathrm{CTRL}}={\mathrm{V}}_{\mathrm{FB}}-{\mathrm{V}}_{\mathrm{SG}3}={\mathrm{V}}_{\mathrm{REF}}-{\mathrm{V}}_{\mathrm{SG}3}$$

(2)

where V_SG3 is the source-to-gate voltage of M_C3. Since M_C1 and M_C3 are of the same size and of the same bias condition, the following relationship is achieved:

$${\mathrm{V}}_{\mathrm{OUT}}={\mathrm{V}}_{\mathrm{REF}}$$

(3)

when the output voltage changes, the source of M_C1 senses change of the output voltage and eventually generates an error signal at the gate of the power transistor. The output impedance of the LDO is reduced drastically by the loop gain of the shunt feedback. Since there is no large output capacitor in an output-capacitorless LDO, the shunt feedback can push the pole created at the LDO output away from BW_L. Therefore, the BW_L of this LDO is wide and SR_G is the dominate factor affecting the transient response of this LDO.

2.2. FVF-Based OCL-LDO

Figure 3 shows the structure of the push–pull buffer. V_E is the error voltage signal generated by the comparison of output voltage and load voltage. V_G is connected to the gate of the power transistor and two control signals, V_GC and V_GD, of the same phase are generated by two voltage sources, controlling the two output transistors M_C and M_D, respectively. In steady state (Vin remains stable), M_C and M_D pass only little quiescent current, which ensures a high efficiency of OCL-LDO at both light and heavy loads. As shown in Figure 3a, under large-signal responses, when V_G rises rapidly, V_GC and V_GD affected by V_G also rise rapidly, resulting in the M_C transistor being off and M_D receiving a large gate-to-source voltage. Therefore, a M_D transistor can provide a large drain current to discharge the capacitance at the gate of the power transistor. Conversely, as shown in Figure 3b, when V_G drops rapidly, M_D will turn off and M_C will turn on, and the parasitic capacitance at the gate of the power transistor can be quickly charged by Mc. The above discussion proves that the push–pull buffer has the ability to quickly charge and discharge capacitors; so, this work uses a push–pull buffer to increase the SR_G.

Figure 4 shows the schematic of the push–pull buffer, with two source followers used to act as voltage sources in Figure 3. The source follower can provide a constant source-gate voltage V_SG with a constant bias current. In addition, the source followers can reduce the equivalent impedance of the gate of M_C and M_D and push the poles generated at these two nodes, which is beneficial to the loop stability of this circuit.

2.3. LDO with the Push–Pull Buffer

Figure 5 shows the overall structure of an FVF-based OCL-LDO with the push–pull buffer. The source of M_C1 senses the drop (or increase) of V_O and generates an error voltage signal at the drain of M_C1. Since diode-connected transistors are used as the load, the swing range of vs. is similar to that of V_OUT. The next stage uses a common-source amplifier loaded with a constant current source. The purpose of this stage is to first increase the DC gain of the negative feedback loop to compensate for the low DC gain of the FVF topology. Secondly, regarding the large-signal response, this structure enables V_E to have a larger voltage swing range and increase the charge and discharge current of the push–pull buffer. Moreover, the current source I_DC which supplies quiescent current to M_C3 should match the one that provides quiescent current to M₃ as much as possible to ensure that the output voltage V_OUT is equal to the reference voltage V_REF.

3. Optimization of Loop Stability

A large off-chip capacitor (often in the µF level) is always connected to the pin of V_OUT in traditional LDOs, which creates a low-frequency pole at the output voltage node as the dominate pole. However, OCL-LDO has no off-chip capacitance, the pole created by the output voltage node is often the non-dominate pole. Furthermore, for FVF-based LDOs, the output impedance of the LDO is reduced by the loop gain of the shunt feedback, and the output poles are pushed further away. Thus, a low-frequency pole must be created as the dominate pole. The gate of the power transistor is an excellent node as the dominate pole position, because the area of the power transistor is quite large, resulting in a large parasitic capacitance. It allows the capacitance used for compensation to be reduced. Additionally, the push–pull buffer makes the impedance at the gate of power transistor large, and so, it is an excellent dominate pole position. If other nodes are selected as the dominate pole, it will come with the following risks. Firstly, the pole created by the gate of power transistor will threaten the loop stability as the non-dominate pole. Additionally, then, the compensation capacitor connected to the dominate pole will cause new slew rate problems in the case of large-signals response. Therefore, the gate of power transistor was selected as the dominate pole for this work. Miller capacitors are still needed to improve loop stability. As shown in Figure 6a, C_C is the Miller capacitor. In addition, when V_OUT overshoot or undershoot, C_C can act as a coupling capacitor to regulate the gate voltage of power transistor. However, the Miller capacitor creates a right half-plane zero Z₀, where Z₀ is given by:

$${\mathrm{Z}}_0={\mathrm{g}}_{\mathrm{mP}}/{\mathrm{C}}_{\mathrm{C}}$$

(4)

where g_mP is the equivalent transconductance of the power transistor. The right half-plane zero greatly affects the loop stability of this circuit, so a zeroing resistance R_Z is always connected in series with the Miller capacitor. The position of Z₀ becomes:

$${\mathrm{Z}}_0=\frac{1}{\left(1/{\mathrm{g}}_{\mathrm{mP}}-{\mathrm{R}}_{\mathrm{Z}}\right){\mathrm{C}}_{\mathrm{C}}}$$

(5)

It can be observed from the above equation that the closer R_Z and g_mP are, the better the zeroing effect will be. However, g_mP is a parameter related to the output current I_O, which changes with the load, and the transconductance of the transistor operating in the saturation region is given by:

$${\mathrm{g}}_{\mathrm{m}}={\mathsf{\mu }\mathrm{C}}_{\mathrm{ox}}\frac{\mathrm{W}}{\mathrm{L}}\left({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{TH}}\right)=\sqrt{2{\mathsf{\mu }\mathrm{C}}_{\mathrm{OX}}\frac{\mathrm{W}}{\mathrm{L}}{\mathrm{I}}_{\mathrm{D}}}$$

(6)

where µ is the carrier mobility, C_OX is gate oxide capacitance per unit area, V_TH is the threshold voltage of the transistor and I_D is the drain current. Transistors operating in the linear region can be used as resistors, and its resistance value is inversely proportional to the overdrive voltage. For example, in [26], a way of frequency compensation named pole-zero tracking was proposed, which used a transistor operating in the linear region as a variable resistor. So, in this work, a transistor M_R operating in the linear region was used as the resistance, as shown in Figure 6b. The resistance of the transistor operating in the linear region R_M was:

$${\mathrm{R}}_{\mathrm{M}}=\frac{1}{{\mathsf{\mu }\mathrm{C}}_{\mathrm{OX}}\frac{\mathrm{W}}{\mathrm{L}}\left({\mathrm{V}}_{\mathrm{GS}}-{\mathrm{V}}_{\mathrm{TH}}\right)}$$

(7)

From the above two formulas, it is evident that R_M and 1/g_m have the same trend with I_O. Therefore, transistors operating in the linear region can be used as zeroing resistors.

However, when the output current is little, there is huge difference between the reciprocal of the actual transconductance of the power transistor and the actual equivalent resistance of M_R. The reason for this is that the above equation is accurate only when the power transistor M_P is operating in the saturation region and transistor M_R is operating in the linear region. In most cases, the above two assumptions are true, except when the output current is very small. At light loads, the power transistor M_P is in the subthreshold region and M_R turns off. Therefore, both the transconductance of M_P and the equivalent resistance of M_R deviate from the calculated value, especially the latter. The equivalent resistance of M_R in the cut-off region is much larger than that in the linear region. Consequently, a resistor R₀ is paralleled across the M_R. This structure is named adaptive resistance unit (ARU). When I_O is small, the resistance of ARU, R_Z is approximately equal to R₀, and conversely, when I_O is large, R_Z is approximately equal to R_M. R₀ can effectively solve the problem of mismatch between the zeroing resistor and the transconductance of the power transistor at light loads. The comparison of 1/g_m and R_Z over the entire load current range is shown in Figure 7, and it was clear that their values were close in the whole load range. Additionally, the amplitude-frequency curve and phase-frequency curve using ARU and the fixed resistor are shown in Figure 8, it can be observed that when the fixed resistance was used as zeroing resistance, there was a right half-plane zero point located in the low frequency region at light loads, and there was a left half-plane zero point within the bandwidth at heavy loads. However, when ARU was used as the zeroing resistor, there were no zeros or poles except the main pole located within the bandwidth. So, it was proved that ARU had a significant improvement in loop stability.

4. Simulation Result and Discussion

The OCL-LDO in this paper was created and simulated in a CMOS process. The layout is shown in Figure 9, and the whole layout had a total area of around 279.16 µm × 165.16 µm. The Miller capacitor C_C which is within the black dashed frame was about 50 pF, so it cost a lot of area. C_C only spanned the output stage composed of the power transistor, so a large Miller capacitor was required to maintain loop stability. In particular, the control voltage generator circuit and standard current source I_DC are not shown in Figure 9. Due to matching considerations, they were placed with the Bandgap circuit of the power management system. This power management system included this OCL-LDO, matching Bandgap circuit, the current source circuit and another auxiliary circuit. M_C3, which was matched with M_C1, was placed in the buffer area in this figure. The post-simulation results are exhibited as follows:

The LDO had a dropout voltage of 0.3 V and could provide 50 mA of load current. Additionally, when output capacitor value ranged from 0 to 1 nF, the loop of LDO was stable. The OCL-LDO also used a negligible 16.1 µA of quiescent current when the load current reached 50 mA; at this point, its current efficiency was 99.97%. The current efficiency η is a common measure of LDO efficiency and its formula is:

$$\mathsf{\eta }=\frac{{\mathrm{I}}_{\mathrm{OUT}}}{{\mathrm{I}}_{\mathrm{OUT}}+{\mathrm{I}}_{\mathrm{Q}}}$$

(8)

where I_OUT is the output current and I_Q is the quiescent current of the OCL-LDO. In addition, with a 50 pF output capacitor, the load regulation was simulated for V_IN = 1.8 V and V_OUT = 1.5 V, and this result is shown in Figure 10a, and the load regulation was 1.45 mV/A.

By incorporating a sinusoidal signal into a DC input voltage of 1.8 V and monitoring the result, the power supply rejection (PSR) can be simulated. Additionally, the PSR of the OCL-LDO with 50 pF output capacitor under various load currents is depicted in Figure 10b, where V_IN = 1.8 V. The PSR in the low frequency region was approximately 51 dB.

The phase margin is an important parameter to measure the stability of the LDO loop, which can be seen from the amplitude-frequency curve and phase-frequency curve. Amplitude-frequency and phase-frequency curves under different load current are shown in Figure 11a, when C_L = 50 pF. As can be seen from Figure 11a, the bandwidth was approximately 500 kHz and there were no zeros or poles except the main pole located within the bandwidth. Thus, the phase margin was nearly 90 degrees. It was indicated that the circuit was stable over the entire load current range. Figure 11b shows the amplitude-frequency and phase-frequency curves under different load current, temperature, and process corner. The worst combination of process corner, output current, and temperature was 0 A and 125° and the minimum value of the phase margin was 38 degrees. This proved the feasibility of the proposed OCL-LDO.

The load transient response was simulated when the output of the OCL-LDO was connected to a 50 pF capacitor. Additionally, the range of load current was from 200 µA to 50 mA, with the rise/fall time of 10 ns. At V_OUT = 1.5 V, as shown in Figure 12, the maximum output voltage overshoot and undershoot were both less than 130 mV. The fluctuations in output voltage were roughly ±8.5%. Based on the high slew rate push–pull buffer, it was possible to produce the little overshoot or undershoot under large load-step. Additionally, then, as can be seen in Figure 12, the push–pull buffer can provide a 255 µA charge current and 610 µA discharge current in large-signal response. With large temporary charge and discharge currents, the gate of the power transistor can be quickly raised and lowered to control the output current of the OCL-LDO. As shown in Figure 12, the voltage at the gate of the power transistor V_G varied with load from 1.05 V to 1.4 V. Moreover, the maximum value of recovery time was about 200 ns. Additionally, the LDO was able to accomplish the well-behaved settling characteristic due to the high phase margin over the entire load range.

As shown in

Table 1. Performance summary and comparison of OCL-LDO.

	[27]	[28]	[2]	[4]	[29]	[30]	This Work
Year	2007	2012	2014	2012	2020	2017	2023
Technology (nm)	350	130	180	65	65	65	180
Chip Area (mm2)	0.12	0.018	0.14	0.017	0.0105	0.016	0.046
Input Voltage (V)	3	1.2	1.8	1.2	0.95–1.2	0.6	1.8
Maximum Output Current (mA)	50	50	50	100	100	50	50
Quiescent Current (µA)	65	37.32	55	0.9–82.4	14	32	16.1
Current Efficiency (%)	99.87	99.93	99.89	99.99	99.99	99.94	99.97
On-chip Capacitor (pF)	23	21	28	4.5	6	40	50
Off-chip Capacitor (pF)	100	20	100	0–100	100	40	0–1000
Settling Time (µs)	15	0.4	6	6	3.2	N/A	0.2
FOM (ps)	0.233	0.017	0.264	0.056	0.0322	0.137	0.0415

, the proposed OCL-LDO showed improved performance when compared to several previously reported OCL-LDOs. The parameter known as the figure of merit, or FOM [10], which was used to measure transient response, is provided by:

$$\mathrm{FOM}={\mathrm{T}}_{\mathrm{R}}\ast \frac{{\mathrm{I}}_{\mathrm{Q}}}{{\mathrm{I}}_{\mathrm{LOAD}\_\mathrm{MAX}}}$$

(9)

where I_Q is the quiescent current and I_{LOAD_MAX} is the maximum output current. The response time, T_R, is given by:

$${\mathrm{T}}_{\mathrm{R}}=\frac{{\mathrm{C}}_{\mathrm{OUT}}{\ast \mathsf{\Delta }\mathrm{V}}_{\mathrm{OUT}}}{{\mathrm{I}}_{\mathrm{LOAD}\_\mathrm{MAX}}}$$

(10)

where C_OUT is the equivalent resistance of the output node and ΔV_OUT is maximum output spike voltage. It can be seen from Table 1 that the proposed LDO achieved a fast transient response and a low quiescent current.

5. Conclusions

This paper proposed a new structure of output-capacitorless LDO with low quiescent current and fast transient response. The flipped voltage follower topology was used to extend its bandwidth, and reduce the complexity of the LDO for fast response to load current transients. A push–pull buffer was implemented to increase the temporary charging and discharging currents at the gate of the power transistor in large signal transient response, ensuring the high slew rate at the gate of power transistor. In addition, an adaptable resistance unit was employed to solve the right half plane zero point problem caused by Miller compensation, which improved the loop stability over the entire load variation range. The LDO loop was stable over a load capacitance range of 0–1 nF. The simulation results showed that the maximum overshoot and undershoot voltage of the LDO was still less than 130 mV when the load current quickly changed from 200 μA to 50 mA within 10 ns, and Vout = 1.5 V. In addition, its quiescent current was only 16.1 μA. Low power and fast transient response made this output capacitorless LDO highly favorable for supply regulation of digital circuitry in small, portable devices.