Search Results (64)

Neuromorphic computing has emerged as a promising paradigm for edge AI systems owing to its event-driven operation and high energy efficiency. However, conventional spiking neural network (SNN) architectures often suffer from redundant computation and inefficient power control, particularly during on-chip learning. This paper proposes a network-on-chip (NoC) architecture featuring a unified refractory-enabled neuron (UREN)-based router that globally coordinates spike-driven computation across multiple neuron cores. The router applies a unified refractory time to all neurons following a winner spike event, effectively enabling clock gating and suppressing redundant activity. The proposed design adopts a star-routing topology with multicasting support and integrates nearest-neighbor spike-timing-dependent plasticity (STDP) for local online learning. FPGA-based experiments demonstrate a 30% reduction in computation and 86.1% online classification accuracy on the MNIST dataset compared with baseline SNN implementations. These results confirm that the UREN-based router provides a scalable and power-efficient neuromorphic processor architecture, well suited for energy-constrained edge AI applications. Full article

Machine vision (MV) is reshaping numerous industries by giving machines the ability to understand what they “see” and respond without human intervention. This review brings together the latest developments in deep learning (DL), image processing, and computer vision (CV). It focuses on how these technologies are being applied in real operational environments. We examine core methodologies such as feature extraction, object detection, image segmentation, and pattern recognition. These techniques are accelerating innovation in key sectors, including healthcare, manufacturing, autonomous systems, and security. A major emphasis is placed on the deepening integration of artificial intelligence (AI) and machine learning (ML) into MV. We particularly consider the impact of convolutional neural networks (CNNs), generative adversarial networks (GANs), and transformer architectures on the evolution of visual recognition capabilities. Beyond surveying advances, this review also takes a hard look at the field’s persistent roadblocks, above all the scarcity of high-quality labeled data, the heavy computational load of modern models, and the unforgiving time limits imposed by real-time vision applications. In response to these challenges, we examine a range of emerging fixes: leaner algorithms, purpose-built hardware (like vision processing units and neuromorphic chips), and smarter ways to label or synthesize data that sidestep the need for massive manual operations. What distinguishes this paper, however, is its emphasis on where MV is headed next. We spotlight nascent directions, including edge-based processing that moves intelligence closer to the sensor, early explorations of quantum methods for visual tasks, and hybrid AI systems that fuse symbolic reasoning with DL, not as speculative futures but as tangible pathways already taking shape. Ultimately, the goal is to connect cutting-edge research with actual deployment scenarios, offering a grounded, actionable guide for those working at the front lines of MV today. Full article

This study provides an in-depth analysis of the learning dynamics of multichannel optical neurons based on spatial solitons generated in lithium niobate crystals. Single-node and multi-node configurations with different topological complexities (3 × 3, 4 × 4, and 5 × 5) were compared, assessing how the number of channels, geometry, and optical parameters affect the speed and efficiency of learning. The simulations indicate that single-node neurons achieve the desired imbalance more rapidly and with lower energy expenditure, whereas multi-node structures require higher intensities and longer timescales, yet yield a greater variety of responses, more accurately reproducing the functional diversity of biological neural tissues. The results highlight how the plasticity of these devices can be entirely modulated through optical parameters, paving the way for fully optical photonic neuromorphic networks in which memory and computation are co-localized, with potential applications in on-chip learning, adaptive routing, and distributed decision-making. Full article

Modern neuromorphic processors exhibit neuron densities that are orders of magnitude lower than those of the biological cortex, hindering the deployment of large-scale spiking neural networks (SNNs) on single chips. To bridge this gap, we propose HDNIP, a 40 nm high-density neuromorphic inference platform with a density-first architecture. By eliminating area-intensive on-chip SRAM and using 1280 compact cores with a time-division multiplexing factor of up to 8192, HDNIP integrates 10 million neurons and 80 billion synapses within a 44.39 ${\mathrm{mm}}^2$ synthesized area. This achieves an unprecedented neuron density of 225 k neurons/${\mathrm{mm}}^2$, over 100 times greater than prior art. The resulting bandwidth challenges are mitigated by a ReRAM-based near-memory computation strategy combined with input reuse, reducing off-chip data transfer by approximately 95%. Furthermore, adaptive TDM and dynamic core fusion ensure high hardware utilization across diverse network topologies. Emulator-based validation using large SNNs, demonstrates a throughput of 13 GSOP/s at a low power consumption of 146 mW. HDNIP establishes a scalable pathway towards single-chip, low-SWaP neuromorphic systems for complex edge intelligence applications. Full article

This review outlines the technological principles of neural–computer interface (NCI) construction, classifying them according to: (1) the degree of intervention (invasive, semi-invasive, and non-invasive); (2) the direction of signal communication, including BCI (brain–computer interface) for converting neural activity into commands for external devices, CBI (computer–brain interface) for translating artificial signals into stimuli for the CNS, and BBI (brain–brain interface) for direct brain-to-brain interaction systems that account for agency; and (3) the mode of user interaction with technology (active, reactive, passive). For each NCI type, we detail the fundamental data processing principles, covering signal registration, digitization, preprocessing, classification, encoding, command execution, and stimulation, alongside engineering implementations ranging from EEG/MEG to intracortical implants and from transcranial magnetic stimulation (TMS) to intracortical microstimulation (ICMS). We also review mathematical modeling methods for NCIs, focusing on optimizing the extraction of informative features from neural signals—decoding for BCI and encoding for CBI—followed by a discussion of quasi-real-time operation and the use of DSP and neuromorphic chips. Quantitative metrics and rehabilitation measures for evaluating NCI system effectiveness are considered. Finally, we highlight promising future research directions, such as the development of electrochemical interfaces, biomimetic hierarchical systems, and energy-efficient technologies capable of expanding brain functionality. Full article

Drawing inspiration from biological brains’ energy-efficient information-processing mechanisms, photonic integrated circuits (PICs) have facilitated the development of ultrafast artificial neural networks. This in turn is envisaged to offer potential solutions to the growing demand for artificial intelligence employing machine learning in various domains, from nonlinear optimization and telecommunication to medical diagnosis. In the meantime, silicon photonics has emerged as a mainstream technology for integrated chip-based applications. However, challenges still need to be addressed in scaling it further for broader applications due to the requirement of co-integration of electronic circuitry for control and calibration. Leveraging physics in algorithms and nanoscale materials holds promise for achieving low-power miniaturized chips capable of real-time inference and learning. Against this backdrop, we present the State of the Art in neuromorphic photonic computing, focusing primarily on architecture, weighting mechanisms, photonic neurons, and training, while giving an overall view of recent advancements, challenges, and prospects. We also emphasize and highlight the need for revolutionary hardware innovations to scale up neuromorphic systems while enhancing energy efficiency and performance. Full article

Leveraging the human brain as a paradigm of energy-efficient computation, considerable attention has been paid to photonic neurons and neural networks to achieve higher computing efficiency and lower energy consumption. This study experimentally demonstrates on-chip silicon photonic neurons and neural networks based on thermally tunable microring resonators (MRRs) implement weighting and nonlinear operations. The weight component consists of eight cascaded MRRs thermally tuned within wavelength division multiplexing (WDM) architecture. The nonlinear response depends on the MRR’s nonlinear transmission spectrum, which is analogous to the rectified linear unit (ReLU) function. The matrix multiplication and recognition task of digits 2, 3, and 5 represented by seven-segment digital tube are successfully completed by using the photonic neural networks constructed by the photonic neurons based on the on-chip thermally tunable MRR as the nonlinear units. The power consumption of the nonlinear unit was about 5.65 mW, with an extinction ratio of about 25 dB between different digits. The proposed photonic neural network is CMOS-compatible, which makes it easy to construct scalable and large-scale multilayer neural networks. These findings reveal that there is great potential for highly integrated and scalable neuromorphic photonic chips. Full article

The traditional von Neumann architecture encounters significant limitations in computational efficiency and energy consumption, driving the development of neuromorphic devices. The optoelectronic synaptic device serves as a fundamental hardware foundation for the realization of neuromorphic computing and plays a pivotal role in the development of neuromorphic chips. This study develops a ternary heterojunction synaptic transistor based on perovskite quantum dots to tackle the critical challenge of synaptic weight modulation in organic synaptic devices. Compared to binary heterojunction synaptic transistor, the ternary heterojunction synaptic transistor achieves an enhanced hysteresis window due to the synergistic charge-trapping effects of acceptor material and perovskite quantum dots. The memory window decreases with increasing source-drain voltage (V_DS) but expands with prolonged program/erase time, demonstrating effective carrier trapping modulation. Furthermore, the device successfully emulates typical photonic synaptic behaviors, including excitatory postsynaptic currents (EPSCs), paired-pulse facilitation (PPF), and the transition from short-term plasticity (STP) to long-term plasticity (LTP). This work provides a simplified strategy for high-performance optoelectronic synaptic transistors, showcasing significant potential for neuromorphic computing and adaptive intelligent systems. Full article

An ultralow-power, high-performance online-learning and anomaly-detection system has been developed for edge security applications. Designed to support personalized learning without relying on cloud data processing, the system employs sample-wise learning, eliminating the need for storing entire datasets for training. Built using memristor-based analog neuromorphic and in-memory computing techniques, the system integrates two unsupervised autoencoder neural networks—one utilizing optimized crossbar weights and the other performing real-time learning to detect novel intrusions. Threshold optimization and anomaly detection are achieved through a fully analog Euclidean Distance (ED) computation circuit, eliminating the need for floating-point processing units. The system demonstrates 87% anomaly-detection accuracy; achieves a performance of 16.1 GOPS—774× faster than the ASUS Tinker Board edge processor; and delivers an energy efficiency of 783 GOPS/W, consuming only 20.5 mW during anomaly detection. Full article

This article provides an overview of the implementation of electromyography (EMG) signal classification algorithms in various embedded system architectures. They address the specifications used for implementation in different devices, such as the number of movements and the type of classification method. Architectures analyzed include microcontrollers, DSP, FPGA, SoC, and neuromorphic computers/chips in terms of precision, processing time, energy consumption, and cost. This analysis highlights the capabilities of each technology for real-time wearable applications such as smart prosthetics and gesture control devices, as well as the importance of local inference in artificial intelligence models to minimize execution times and resource consumption. The results show that the choice of device depends on the required system specifications, the robustness of the model, the number of movements to be classified, and the limits of knowledge concerning design and budget. This work provides a reference for selecting technologies for developing embedded biomedical solutions based on EMG. Full article

In this paper, we propose an optimization approach using Particle Swarm Optimization (PSO) to enhance reservoir separability in Liquid State Machines (LSMs) for spatio-temporal classification in neuromorphic systems. By leveraging PSO, our method fine-tunes reservoir parameters, neuron dynamics, and connectivity patterns, maximizing separability while aligning with the resource constraints typical of neuromorphic hardware. This approach was validated in both software (NEST) and on neuromorphic hardware (SpiNNaker), demonstrating notable results in terms of accuracy and low energy consumption when using SpiNNaker. Specifically, our approach addresses two problems: Frequency Recognition (FR) with five classes and Pattern Recognition (PR) with four, eight, and twelve classes. For instance, in the Mono-objective approach running in NEST, accuracies ranged from 81.09% to 95.52% across the benchmarks under study. The Multi-objective approach outperformed the Mono-objective approach, delivering accuracies ranging from 90.23% to 98.77%, demonstrating its superior scalability for LSM implementations. On the SpiNNaker platform, the mono-objective approach achieved accuracies ranging from 86.20% to 97.70% across the same benchmarks, with the Multi-objective approach further improving accuracies, ranging from 94.42% to 99.52%. These results show that, in addition to slight accuracy improvements, hardware-based implementations offer superior energy efficiency with a lower execution time. For example, SpiNNaker operates at around 1–5 watts per chip, while traditional systems can require 50–100 watts for similar tasks, highlighting the significant energy savings of neuromorphic hardware. These results underscore the scalability and effectiveness of PSO-optimized LSMs on resource-limited neuromorphic platforms, showcasing both improved classification performance and the advantages of energy-efficient processing. Full article

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution. Full article

Hybrid neural networks (HNNs), integrating the strengths of artificial neural networks (ANNs) and spiking neural networks (SNNs), provide a promising solution towards generic artificial intelligence. There is a prevailing trend towards designing unified SNN-ANN paradigm neuromorphic computing chips to support HNNs, but developing platforms to advance neuromorphic computing systems is equally essential. This paper presents the PAIBoard platform, which is designed to facilitate the implementation of HNNs. The platform comprises three main components: the upper computer, the communication module, and the neuromorphic computing chip. Both hardware and software performance measurements indicate that our platform achieves low power consumption, high energy efficiency and comparable task accuracy. Furthermore, PAIBoard is applied in a robot dog for tracking and obstacle avoidance system. The tracking module combines data from ultra-wide band (UWB) transceivers and vision, while the obstacle avoidance module utilizes depth information from an RGB-D camera, which further underscores the potential of our platform to tackle challenging tasks in real-world applications. Full article

A neuromorphic computing network based on SiC_x memristor paves the way for a next-generation brain-like chip in the AI era. Up to date, the SiC_x–based memristor devices are faced with the challenge of obtaining flexibility and uniformity, which can push forward the application of memristors in flexible electronics. For the first time, we report that a flexible artificial synaptic device based on a Ag NPs:a–SiC_0.11:H memristor can be constructed by utilizing aluminum foil as the substrate. The device exhibits stable bipolar resistive switching characteristic even after bending 1000 times, displaying excellent flexibility and uniformity. Furthermore, an on/off ratio of approximately 10⁷ can be obtained. It is found that the incorporation of silver nanoparticles significantly enhances the device’s set and reset voltage uniformity by 76.2% and 69.7%, respectively, which is attributed to the contribution of the Ag nanoparticles. The local electric field of Ag nanoparticles can direct the formation and rupture of conductive filaments. The fitting results of I–V curves show that the carrier transport mechanism agrees with Poole–Frenkel (P–F) model in the high-resistance state, while the carrier transport follows Ohm’s law in the low-resistance state. Based on the multilevel storage characteristics of the Al/Ag NPs:a–SiC_0.11:H/Al foil resistive switching device, we successfully observed the biological synaptic characteristics, including the long–term potentiation (LTP), long–term depression (LTD), and spike–timing–dependent plasticity (STDP). The flexible artificial Ag NPs:a–SiC_0.11:H/Al foil synapse possesses excellent conductance modulation capabilities and visual learning function, demonstrating the promise of application in flexible electronics technology for high-efficiency neuromorphic computing in the AI period. Full article

As the key hardware of a brain-like chip based on a spiking neuron network (SNN), memristor has attracted more attention due to its similarity with biological neurons and synapses to deal with the audio signal. However, designing stable artificial neurons and synapse devices with a controllable switching pathway to form a hardware network is a challenge. For the first time, we report that artificial neurons and synapses based on multilayered HfO_x/TiO_y memristor crossbar arrays can be used for the SNN training of audio signals, which display the tunable threshold switching and memory switching characteristics. It is found that tunable volatile and nonvolatile switching from the multilayered HfO_x/TiO_y memristor is induced by the size-controlled atomic oxygen vacancy pathway, which depends on the atomic sublayer in the multilayered structure. The successful emulation of the biological neuron’s integrate-and-fire function can be achieved through the utilization of the tunable threshold switching characteristic. Based on the stable performance of the multilayered HfO_x/TiO_y neuron and synapse, we constructed a hardware SNN architecture for processing audio signals, which provides a base for the recognition of audio signals through the function of integration and firing. Our design of an atomic conductive pathway by using a multilayered TiO_y/HfO_x memristor supplies a new method for the construction of an artificial neuron and synapse in the same matrix, which can reduce the cost of integration in an AI chip. The implementation of synaptic functionalities by the hardware of SNNs paves the way for novel neuromorphic computing paradigms in the AI era. Full article