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Electronics
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Unlocking the Brain-Inspired Future: Frontiers in Neuromorphic Computing
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Unlocking the Brain-Inspired Future: Frontiers in Neuromorphic Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Artificial Intelligence".

Deadline for manuscript submissions: 10 November 2026 | Viewed by 1355

Special Issue Editors

Dr. Guanchao Qiao

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Guest Editor
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Interests: intelligent chips and algorithms; neuromorphic computing
Prof. Dr. Shaogang Hu

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Guest Editor
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Interests: emerging memory devices; neuromorphic chips; brain-inspired computing
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The quest for artificial intelligence that emulates the brain's efficiency and adaptability has led to the rise of neuromorphic computing. This Special Issue, "Unlocking the Brain-Inspired Future: Frontiers in Neuromorphic Computing," explores the most exciting frontiers of this transformative field. We are looking for submissions that push the boundaries of what is currently possible. Contributions are sought in foundational theory and novel computational models, with a particular focus on how these models can achieve unprecedented energy efficiency and scalability. We are also keenly interested in submissions that detail revolutionary hardware and architectures, from innovative ASICs and programmable arrays to advancements in on-chip learning and plasticity that enable systems to learn and adapt autonomously.

Beyond hardware, we seek papers on the software and toolchains that are essential for democratizing access to this technology. This includes work on advanced simulation tools, new programming languages tailored for spiking neural networks, and sophisticated data preprocessing techniques. A key focus of this Special Issue is on applications that leverage the unique advantages of neuromorphic systems. We invite case studies that demonstrate significant breakthroughs in edge computing for the Internet of Things, robust real-time control for robotics, and intelligent pattern recognition. The final section of this collection will look forward, featuring papers that forecast the future trajectory of neuromorphic computing, including the promise of hybrid architectures and the critical ethical considerations surrounding this technology. By bringing together diverse perspectives, this Special Issue aims to illuminate the path forward and inspire the next wave of innovation in brain-inspired AI.

Dr. Guanchao Qiao
Prof. Dr. Shaogang Hu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • neuromorphic computing
  • neuromorphic devices
  • spiking neural networks (SNNs)
  • bio-inspired AI

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Published Papers (2 papers)

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19 pages, 1184 KB  
Article
Hardware-Accelerated Cryptographic Random Engine for Simulation-Oriented Systems
by Meera Gladis Kurian and Yuhua Chen
Electronics 2026, 15(6), 1297; https://doi.org/10.3390/electronics15061297 - 20 Mar 2026
Viewed by 520
Abstract
Modern computing platforms increasingly rely on random number generators (RNGs) for modeling probabilistic processes in simulation, probabilistic computing, and system validation. They are also essential for cryptographic operations such as key generation, authenticated encryption, and digital signatures. Deterministic Random Bit Generators (DRBGs), as [...] Read more.
Modern computing platforms increasingly rely on random number generators (RNGs) for modeling probabilistic processes in simulation, probabilistic computing, and system validation. They are also essential for cryptographic operations such as key generation, authenticated encryption, and digital signatures. Deterministic Random Bit Generators (DRBGs), as specified in the National Institute of Standards and Technology (NIST) Special Publication (SP) 800-90A, provides a standardized method for expanding entropy into cryptographically strong pseudorandom sequences. This work presents the design and Field Programmable Gate Array (FPGA) implementation of a hash-based DRBG using Ascon-Hash256, a lightweight, quantum-resistant hash function from the NIST-standardized Ascon cryptographic suite. It implements hash-based derivation, instantiation, generation, and reseeding of the generator via iterative hash invocations and state updates. Leveraging Ascon’s sponge-based structure, the design achieves efficient entropy absorption and diffusion while maintaining an area-efficient FPGA architecture, making it well suited for resource-constrained platforms. The diffusion properties of the proposed DRBG are evaluated through avalanche and reproducibility analyses, confirming strong sensitivity to input variations and secure, repeatable operation. Moreover, Monte Carlo and stochastic-diffusion evaluation of the generated bitstreams demonstrates correct convergence and statistically consistent behavior. These results confirm that the proposed hash-based DRBG provides reproducible, hardware-efficient, and cryptographically secure random numbers suitable for next-generation neuromorphic, probabilistic computing systems, and Internet of Things (IoT) devices. Full article
(This article belongs to the Special Issue Unlocking the Brain-Inspired Future: Frontiers in Neuromorphic Computing)
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22 pages, 6111 KB  
Article
DeVSA: A Density-Efficient Vector SNN Accelerator Exploiting Compressor-TreeReuse for Spike-Weight Accumulation
by Yue Zuo, Zhilin Li, Yang Liu and Ning Ning
Electronics 2026, 15(6), 1296; https://doi.org/10.3390/electronics15061296 - 20 Mar 2026
Viewed by 373
Abstract
Spiking neural networks are promising for energy-efficient edge intelligence, but mapping 1-bit spikes onto high-precision vector datapaths leads to underutilization and low compute density. This paper presents DeVSA, a 16-lane vector SNN accelerator for LIF-based SNNs with 1-bit spikes and BF16 weights. DeVSA [...] Read more.
Spiking neural networks are promising for energy-efficient edge intelligence, but mapping 1-bit spikes onto high-precision vector datapaths leads to underutilization and low compute density. This paper presents DeVSA, a 16-lane vector SNN accelerator for LIF-based SNNs with 1-bit spikes and BF16 weights. DeVSA reuses the compressor tree of a standard BF16 multiplier to support an 8-way spike-weight dot-product (DOT8) by directly reducing exponent-aligned, spike-gated mantissas without introducing a dedicated SNN accumulation datapath, preserving full BF16 multiplication capability. DeVSA integrates single-cycle fire-and-reset to streamline per-timestep LIF updates. A hardware micro-loop controller amortizes instruction fetch/decode over up to 256 iterations, and a shared reconfigurable adder tree supports both element-wise operations and hierarchical reductions. Synthesized in 28-nm CMOS, DeVSA operates at 1.4 GHz and achieves a peak throughput of 340.6 GFLOPS at 163 mW, corresponding to 2.09 TFLOPS/W and 838 GFLOPS/mm2 post-synthesis compute density in DOT8 mode. On N-MNIST, DVS-Gesture, and CIFAR-10, DeVSA provides end-to-end effective speedups of up to 7.76× over standard vector baselines and outperforms state-of-the-art programmable SNN processors by 5.0×–7.9× in estimated post-P&R density under 50% utilization. DeVSA shows that compressor-tree reuse can deliver high compute density and energy efficiency with vector-level programmability for SNN inference. Full article
(This article belongs to the Special Issue Unlocking the Brain-Inspired Future: Frontiers in Neuromorphic Computing)
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