Search Results (158)

The proliferation of intelligent edge devices demands compact, low-power hardware capable of dynamically switching between sensing, logic, and learning tasks—a versatility that traditional multi-chip solutions fundamentally lack. Here, we demonstrate a reconfigurable spin–orbit torque (SOT) device based on an FeTb/Ru/Co synthetic antiferromagnetic (SAF) heterostructure. By modulating the input current amplitude, the device dynamically switches between two distinct operating modes: saturation and activation. In the saturation regime (>80 mA), deterministic magnetization reversal enables Boolean logic operations (AND, NOR). In the activation regime (<80 mA), gradual, non-volatile conductance modulation emulates synaptic plasticity. Benefiting from the strong antiferromagnetic coupling and near-zero net magnetization of the SAF structure, all operations are achieved without external magnetic fields. This single-device, dual-mode reconfigurable architecture establishes a new paradigm for high-density, low-power, multifunctional in-memory computing units, with promise for advancing adaptive edge computing chips. Full article

Accurate yaw alignment is critical for maximizing power capture in horizontal-axis wind turbines, as even moderate yaw misalignment leads to significant aerodynamic losses, increased actuator usage, and accelerated mechanical wear. This research paper proposes a hybrid smart yaw control system for small-scale wind turbines that combines real-time measurements with short-term wind direction prediction to improve alignment accuracy, operational reliability, and energy efficiency under realistic operating conditions. The system integrates four wind direction information sources, such as physical wind vane sensing, live online weather data, forecast data, and a data-driven prediction module within a structured priority framework (VANE → LIVE → FORECAST → AI), to ensure continuous yaw control during sensor or communication unavailability. The prediction module is based on a long short-term memory (LSTM) neural network trained in MATLAB using live data from an online platform, with sine–cosine encoding employed to address the circular nature of directional data. The yaw controller incorporates a ±15° deadband, dwell-time logic, shortest-path rotation, and cable-safe constraints to reduce unnecessary actuation while maintaining effective alignment. The proposed system is validated through MATLAB/Simulink simulations and real-time microcontroller-based experiments using a stepper motor-driven nacelle. Compared with conventional vane-based yaw control, the hybrid AI-assisted approach reduces the average yaw error by approximately 35–45%, maintains a yaw error within ±15° for more than 90% of the operating time, increases average electrical power output by 3–5%, and reduces yaw motor energy consumption by 10–15%, while decreasing corrective yaw actuation events by 30–40%. These results demonstrate that integrating an LSTM-based wind direction predictor with multi-source wind data provides a robust, low-cost, and practically deployable yaw control solution that enhances energy capture and mechanical durability in small-scale wind turbines. Full article

Lamport’s Bakery algorithm is a well-known, simple, and elegant solution to the mutual exclusion problem for N ≥ 2 concurrent/parallel processes. However, the algorithm generates an unbounded number of tickets, even when only 2 processes are arbitrated. Various proposals in the literature were introduced to bound the number of tickets. Anyway, almost all these proposals prove to be correct when operated with atomic registers (AR) only. They become incorrect when working with non-atomic registers (NAR), as may occur in embedded hardware platforms with multi-port memory and relaxed memory-bus control, such as microcontrollers, FPGA-based systems, or specialized network devices. A notable solution with bounded tickets is Taubenfeld’s Black-White Bakery (BWB) algorithm. BWB relies on tickets which are couples <number,mycolor> where mycolor can be Black or White and number ranges in [0, N]. BWB, too, was confirmed, through informal reasoning, it is correct with AR only. The original contribution of this paper is a reformulation of BWB, which is formally modelled and exhaustively verified by timed automata in the Uppaal toolbox. In the reformulation, a ticket’s couple is coded as a single integer, and decoded and processed according to the BWB logic. The reformulated BWB remains fully correct with AR regardless of the number N of processes, but it is also correct with NAR for N = 2 processes. As a further original contribution, the paper demonstrates that the BWB version for 2 processes can be embedded in a general, state-of-the-art solution, based on a binary tournament tree (TT), to become AR/NAR correct, that is, RW-safe, for any number of processes. However, due to model complexity, the correctness of the TT versions of BWB, that is, based on atomic and non-atomic registers, is mainly studied by stochastic simulation of the formal model reduced to actors in Java. Full article

Asymmetric error characteristics in spin-transfer torque magnetic random-access memory (STT-MRAM), particularly the imbalance between logical ‘0’ and ‘1’ error probabilities, can significantly degrade system reliability under conventional modulation and error-correcting schemes. This issue is especially critical in sensor network applications, where STT-MRAM is widely adopted for its non-volatility, low standby power, and robustness under energy-constrained and intermittently active operation. Existing approaches typically optimize the detection threshold under the assumption of a fixed or equiprobable bit distribution, while sparse coding techniques impose a predefined imbalance without explicitly accounting for its interaction with threshold detection. In this paper, we formulate the bit error rate (BER) minimization problem as a joint optimization of the codeword bit distribution and the detection threshold over an asymmetric cascaded STT-MRAM channel. Analytical results reveal that the minimum BER is achieved when the error probabilities associated with transmitted ‘0’ and ‘1’ bits are balanced, which induces an intrinsic coupling between the optimal detection threshold and the codeword composition. Motivated by this insight, we propose a new family of threshold-matched probability codes (TMPCs), in which the proportion of logical ‘1’s in each codeword is explicitly designed to match the optimal detection threshold of the underlying channel. The proposed coding framework generalizes conventional sparse modulation by enabling adjustable bit distributions while preserving low-complexity linear encoding and syndrome-based decoding. Numerical evaluations demonstrate that the TMPC achieves consistently lower BERs than existing sparse and fixed-distribution coding schemes across a wide range of STT-MRAM operating conditions, particularly under severe write asymmetry and resistance variation. These results indicate that the proposed joint design offers a principled and flexible approach for improving reliability in STT-MRAM-based sensor networks and non-volatile memory systems. Full article

The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs). This paper proposes a novel ADC-free CiM architecture based on Ferroelectric Field-Effect Transistors (FeFETs). Logic circuits (NOR, NAND, XNOR) that store weight vectors within FeFETs were designed. Compared with analog CiM circuits, the FeFETs-CiM circuits proposed in this paper can reduce power consumption by 901.1 times and latency by 272.7 times. Furthermore, the design of 3-bit FeFETs-CiM gates was extended, demonstrating flexible configurability for scalable edge computing applications. Finally, an application specific FeFETs-CiM subtractor for k-nearest neighbor (kNN) distance calculation was designed, which energy consumption is as low as 85.02 fJ/OP and latency is as low as 0.56 ns under 500 MHz operation frequency. The calculation robustness of the FeFETs-CiM kNN distance calculator was ensured by simulating under different process corners and temperatures. The performance improvements owing to the proposed FeFETs-CiM CMOS circuits were evaluated by taking the kNN algorithm as an example, which can ensure the data access reduction by more than 300 times compared to von Neumann architecture. Full article

Against the backdrop of global climate change, remote subtropical mountainous power grids face severe operational challenges due to their fragile infrastructure and complex climatic conditions. However, existing research has insufficiently addressed load forecasting in data-sparse regions, particularly lacking systematic analysis of the “meteorology–load–failure” coupling mechanism. To address this gap, this study focused on 10 kV distribution lines in a typical subtropical monsoon region of southern China. Based on hourly load and meteorological data from 2016 to 2025, we propose a two-stage hybrid model combining “Random Forest (RF) feature selection + Long Short-Term Memory (LSTM) time series forecasting”. Through deep feature engineering, composite, lagged, and interactive features were constructed. Using the RF algorithm, we quantitatively identified the core drivers of load variation across different time scales: at the hourly scale, variations are dominated by historical inertia (with weights of 0.5915 and 0.3757 for 1-h and 24-h lagged loads, respectively); at the daily scale, the logic shifts to meteorological triggering and cumulative effects, where the composite feature load_lag1_hi_product emerged as the most critical driver (weight of 0.8044). Experimental results demonstrate that the hybrid model significantly improved forecasting accuracy compared to the full-feature LSTM benchmark: on a daily scale, RMSE decreased by 13.29% and MAE by 16.67%, with R² reaching 0.8654; on an hourly scale, R² reached 0.9687. Furthermore, correlation analysis with failure data revealed that most grid faults occurred during intervals of extremely low load variation (0–5%), suggesting that “chronic stress” from environmental exposure in hot and humid conditions is the primary cause, with lightning identified as the leading external threat (26.90%). The interpretable forecasting framework proposed in this study transcends regional limitations. It provides a strategic “low-cost, high-resilience” prototype applicable to power systems in humid-subtropical zones worldwide, particularly for developing regions facing the dual challenges of data sparsity and climate vulnerability. Full article

Traditional complementary metal-oxide-semiconductor (CMOS) logic gates serve as the fundamental building blocks of modern computing, operating through the electron charge manipulation wherein binary information is encoded as distinct high- and low-voltage states. However, as physical dimensions approach the quantum limit, conventional logic gates encounter fundamental bottlenecks, including power consumption barriers, memory limitations, and a significant increase in static power dissipation. Consequently, the pursuit of novel low-power computing methodologies has emerged as a research hotspot in the post-Moore era. Logic gates based on magnetic skyrmions constitute a highly promising candidate in this context. Magnetic skyrmions, nanoscale quasiparticles endowed with topological protection, offer ideal carriers for information transmission due to their exceptional stability and mobility. In this work, we provide a concise overview of the current development status and underlying operating principles of magnetic skyrmion logic gates across various magnetic materials, including ferromagnetic, synthetic antiferromagnetic, and antiferromagnetic systems. The introduction of magnetic skyrmion-based logical operations represents a paradigm shift from traditional Boolean logic to architectures integrating memory and computation, as well as brain-inspired neuromorphic computing. Although significant challenges remain in the synthesis of materials, fabrication, and detection, magnetic skyrmion-based logic computing holds considerable potential as a future ultra-low-power computing technology. Full article

Due to the Von Neumann bottleneck of traditional CMOS computing, there is an urgent need to develop in-memory logic devices with low power consumption. In this work, we demonstrate ferroelectric diode devices based on the TiN/Hf_0.5Zr_0.5O₂/HfO₂/TiN structure, implementing 16 Boolean logic operations through single-step or multi-step (2–3 steps) cascade and achieving attojoule-level one-bit full-adder computation. The TiN/Hf_0.5Zr_0.5O₂/HfO₂/TiN ferroelectric diode exhibits non-destructive readout and bidirectional rectification characteristics, with the conduction mechanism following Schottky emission behavior in the on-state. Based on its bidirectional rectification characteristics, we designed and simulated the circuit scheme of 16 Boolean logic and one-bit full-adder through cascaded operations. Both the input and output logic values are represented in the form of resistance, without the need for additional form conversion circuits. The state writing is performed by pulse-controlled polarization flipping, and the state reading is non-destructive. The logic circuits in this work demonstrate superior performance with ultralow computing power consumption in simulation. This breakthrough establishes a foundation for developing energy-efficient and scalable in-memory computing systems. Full article

Fuel cell commercial vehicles are widely used in commercial transport for their high efficiency and long range. However, in mixed operating scenarios, their energy economy and fuel cell operational stability cannot be fully balanced. Traditional strategies lack adaptability in mixed operating scenarios. Therefore, based on the equivalent factor regulation formula of the Adaptive Equivalent Hydrogen Consumption Minimization Strategy (A-ECMS) and the improved Sparrow Search Algorithm-Long Short-Term Memory (SSA-LSTM) hybrid model, short-term speed prediction and three-stage speed interval division are embedded into the equivalent factor regulation logic. A dynamic equivalent factor regulation strategy integrating SOC deviation is constructed, and an improved Predictive Equivalent Hydrogen Consumption Minimization Strategy (P-ECMS) is finally derived. The SSA-LSTM algorithm is optimized via constrained hyperparameter tuning for short-term speed prediction. A time-decay weighting mechanism enhances recent speed data weight, with weighted results as inputs to boost accuracy. Moving Average Residual Correction (MARC) is used to verify the speed prediction model accuracy and correct residuals. Multi-scenario tests show that the SSA-LSTM model outperforms the Gated Recurrent Unit (GRU) model in prediction accuracy and generalization ability, providing reliable data support for segmented regulation. With battery SOC deviation and the SSA-LSTM-predicted speed trend as core inputs, combined with three-stage speed interval division, A-ECMS’s equivalent factor regulation formula is improved. The model adopts a segmented dynamic regulation logic to integrate dual factors into equivalent factor adjustment, and it reasonably adjusts the energy output ratio of fuel cells and power batteries according to speed intervals and operating condition changes. In scenarios with significant speed fluctuations and frequent operating condition transitions, power shocks are mitigated by the power battery’s peak-shaving and valley-filling function. Simulation results for C-WTVC and NREL2VAIL show that, compared with traditional A-ECMS, the improved P-ECMS has notable energy benefits, with equivalent hydrogen consumption reduced by 3.41% and 5.48%, respectively. The fuel cell’s state is significantly improved, with its high-efficiency share reaching 63%. The output power curve is smoother, start–stop losses are reduced, and the fuel cell’s service life is extended, balancing the energy economy and component durability. Full article

This work aims to evaluate the feasibility of using a COTS-embedded computer as an on-board computer (OBC) for nanosatellites in academic projects. The prototype is based on the BeagleBone Black board, which runs the cFS flight-mission software on the RTEMS operating system. For evaluation purposes, 15.9 MeV proton-accelerated radiation tests were performed at the CNA facility to obtain the soft-error rate of the DDR3 SDRAM. Results show the presence of bit-flips in memory cells, leading to error propagation, and a burst of errors produced by SEEs, affecting the control logic of the SDRAM memory. Despite the errors and accumulated dose, the board continued to function normally, with a worst-case FIT indicating that one failure every two years is expected in the SDRAM memory. This study suggests the possibility of using BeagleBone Black as an OBC for LEO. In addition, the article provides clues on how redundancy-based fault tolerance can be implemented. Full article

This paper presents fine-grained Field Programmable Gate Arrays (FPGA) architectures for the Advanced Encryption Standard (AES) MixColumns and InvMixColumns transformations, targeting improved performance and resource utilization. The proposed method reformulates these operations as boolean functions directly mapped onto FPGA Lookup-Table (LuT) primitives, replacing conventional xor-based arithmetic with memory-level computation. A custom MATLAB-R2019a-based pre-synthesis optimization algorithm performs algebraic simplification and shared subexpression extraction at the polynomial level of Galois Field $GF(2^8)$, reducing redundant logic memory. This architecture, LuT-level optimization minimizes the delay of the complex InvMixColumns stage and narrows the delay gap between encryption (1.305 ns) and decryption (1.854 ns), resulting in a more balanced and power-efficient AES pipeline. Hardware implementation on a Xilinx Virtex-5 FPGA confirms the efficiency of the design, demonstrating competitive performance compared to state-of-the-art FPGA realizations. Its fast performance and minimal hardware requirements make it well suited for real-time secure communication systems and embedded platforms with limited resources that need reliable bidirectional data processing. Full article

A special class of complex adaptive systems—biological and social—thrive not by passively accumulating patterns, but by engineering coherence, i.e., the deliberate alignment of prior knowledge, real-time updates, and teleonomic purposes. By contrast, today’s AI stacks—Large Language Models (LLMs) wrapped in agentic toolchains—remain rooted in a Turing-paradigm architecture: statistical world models (opaque weights) bolted onto brittle, imperative workflows. They excel at pattern completion, but they externalize governance, memory, and purpose, thereby accumulating coherence debt—a structural fragility manifested as hallucinations, shallow and siloed memory, ad hoc guardrails, and costly human oversight. The shortcoming of current AI relative to human-like intelligence is therefore less about raw performance or scaling, and more about an architectural limitation: knowledge is treated as an after-the-fact annotation on computation, rather than as an organizing substrate that shapes computation. This paper introduces Mindful Machines, a computational paradigm that operationalizes coherence as an architectural property rather than an emergent afterthought. A Mindful Machine is specified by a Digital Genome (encoding purposes, constraints, and knowledge structures) and orchestrated by an Autopoietic and Meta-Cognitive Operating System (AMOS) that runs a continuous Discover–Reflect–Apply–Share (D-R-A-S) loop. Instead of a static model embedded in a one-shot ML pipeline or deep learning neural network, the architecture separates (1) a structural knowledge layer (Digital Genome and knowledge graphs), (2) an autopoietic control plane (health checks, rollback, and self-repair), and (3) meta-cognitive governance (critique-then-commit gates, audit trails, and policy enforcement). We validate this approach on the classic Credit Default Prediction problem by comparing a traditional, static Logistic Regression pipeline (monolithic training, fixed features, external scripting for deployment) with a distributed Mindful Machine implementation whose components can reconfigure logic, update rules, and migrate workloads at runtime. The Mindful Machine not only matches the predictive task, but also achieves autopoiesis (self-healing services and live schema evolution), explainability (causal, event-driven audit trails), and dynamic adaptation (real-time logic and threshold switching driven by knowledge constraints), thereby reducing the coherence debt that characterizes contemporary ML- and LLM-centric AI architectures. The case study demonstrates “a hybrid, runtime-switchable combination of machine learning and rule-based simulation, orchestrated by AMOS under knowledge and policy constraints”. Full article

Contemporary artificial intelligence is dominated by generative systems that excel at extracting patterns but fail to grasp meaning, sense, context, and experiential temporality. This limitation highlights the need for new computational wisdom that combines philosophical insights with advanced models to produce AI systems capable of authentic understanding. Sophimatics, as elaborated upon in this article, is introduced as a science of computational wisdom that rejects the purely syntactic manipulation of symbols characteristic of classical physical symbolic systems and addresses the shortcomings of generative statistical approaches. Building on philosophical foundations of dynamic ontology, intentionality and dialectical reasoning, Sophimatics integrates complex temporality, multidimensional semantic modeling, hybrid symbolic–connectionist logic, and layered memory structures to that the AI can perceive, remember, reason, and act in ethically grounded ways. This article, which is part of a set of papers, summarizes the theoretical framework underlying Sophimatics and outlines the conceptual results of the materials and methods, illustrating the potential of this approach to improve interpretability, contextual adaptation, and ethical deliberation compared to basic generative models. This is followed by a methodology and a complete formal model for translating philosophical categories into an operational model and specific architecture. This article represents Phase 1 of a six-phase research program, providing mathematical foundations for the architectural implementation and empirical validation presented in companion publications. Following this, several use cases are outlined, and then the Discussion Section anticipates the main results and perspectives for post-generative AI solutions within the Sophimatic paradigm. Full article

This work investigated machine-learning algorithms for remote-control and autonomous operation of the Very-Small, Long-Life, Modular (VSLLIM) microreactor. This walk-away safe reactor can continuously generate 1.0–10 MW of thermal power for 92 and 5.6 full power years, respectively, is cooled by natural circulation of in-vessel liquid sodium, does not require on-site storage of either fresh or spent nuclear fuel, and offers redundant means of control and passive decay heat removal. The two ML algorithms investigated are Supervised Learning with Long Short-Term Memory networks (SL-LSTM) and Soft-Actor Critic with Feedforward Neural Networks (SAC-FNN). They are trained to manage the movement of the control rods in the reactor core during various transients including startup, shutdown, and to change the reactor steady state power up to 10 MW. The trained algorithms are incorporated into a Programmable Logic Controller (PLC) coupled to a digital twin dynamic model of the VSLLIM microreactor. Although the SL-LSTM algorithms demonstrate high prediction accuracy of up to 99.95%, they demonstrate inferior performance when incorporated into the PLC. Conversely, the PLC with SAC-FNN algorithm accurately adjusts the control rods positions during the reactor startup transients to within ±1.6% of target values. Full article

Solid-State Drives (SSDs) have become the dominant storage medium in performance-sensitive systems due to their high throughput, reliability, and energy efficiency. However, inherent constraints in NAND flash memory—such as out-of-place writes, block-level erase operations, and data fragmentation—necessitate frequent garbage collection (GC), which can significantly degrade user I/O performance when not properly managed. This paper presents a channel-aware GC control mechanism for multi-channel SSD architectures that limits GC concurrency based on real-time storage utilization. Unlike conventional controllers that allow GC to proceed simultaneously across all channels—often leading to complete I/O stalls—our approach adaptively throttles the number of GC-active channels to preserve user responsiveness. The control logic uses a dynamic thresholding function that increases GC aggressiveness only as the SSD approaches full capacity, allowing the system to balance space reclamation with quality-of-service guarantees. We implement the proposed mechanism in an SSD simulator and evaluate its performance under a range of real-world workloads. Experimental results show that the proposed adaptive GC control significantly improves SSD responsiveness across various workloads. Across all workloads, the proposed adaptive GC control achieved an average latency improvement factor of 4.86×, demonstrating its effectiveness in mitigating GC-induced interference. Even when excluding extreme outlier cases, the method maintained an average improvement of 1.55×, with a standard deviation of 1.17, confirming its consistency and robustness across diverse workload patterns. Full article