Search Results (6)

Recent advances in artificial intelligence have made power efficiency a primary objective in system design. In this context, stochastic computing (SC), which processes probabilistic bitstreams using simple logic, and spiking neural networks (SNNs), a neuromorphic paradigm, have gained prominence as alternative approaches. This study proposes a Stochastic Computing Neural Network (SC-NN) framework that minimizes the intrinsic errors of stochastic computing and leverages the isomorphism between one-count operations on bitstreams and spike-rate computations in spiking neural networks, yielding improvements in accuracy and hardware efficiency. In contrast to earlier studies that utilized independent random number sequences of 10 bits or higher, our study employed a practically implementable 8-bit linear feedback shift Register (LFSR)-based pseudo-random bitstream. Using 4 taps and 255 seeds improves the realism of the hardware. Despite the inherent accuracy ceiling of pseudo-random sequences, the proposed method achieves higher accuracy. Applied to an 8-bit SC-based neural network accelerator, the proposed design improves accuracy by 35% over a conventional FSM baseline, while reducing power and area by 43.8% and 17.2%, respectively, and decreasing delay by 5.5%. These improvements translate to a 2.3× enhancement in the Figure of Merit (FoM), which was further verified through physical layout and FPGA results. Overall, this work introduces a new paradigm that enables simultaneous gains in accuracy and efficiency for low-power AI by suppressing the error sources and embedding the structural similarity between SNNs and SC into the design. Full article

Physical Unclonable Functions (PUFs) are hardware-based security primitives that can produce unique digital identifiers from electronic devices. They are particularly useful for Internet of Things (IoT) applications due to their low cost and ability to improve security on lightweight devices. In this paper, we propose a new lightweight delay-based Linear Feedback Shift Register (LFSR) PUF with configurable primitive feedback. Our configurable PUF offers various important benefits, such as a compact architecture, low hardware overhead, a large challenge-response space, conservative power requirements, and flexibility to operate in different modes. We implement our proposed PUF on an FPGA, and the experimental results demonstrate that our PUF exhibits nearly ideal performance metrics in terms of uniformity and uniqueness, with minimal hardware overhead and low power consumption. Moreover, our PUF also passes the National Institute of Standards and Technology (NIST) statistical test suite. We also show that our proposed PUF is resistant to Machine Learning (ML) attacks. Full article

This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity of generated patterns, as well as their power consumption, improves through circuit modifications. This work explores enhancements to LFSR structures to achieve broader range of patterns with reduced power consumption for BIST-based applications. The proposed circuit constructed on the LFSR platform can be programmed to generate patterns with varying degrees of different LFSR configurations. Diverse set of patterns of any circuit arrangement can be created using any characteristic polynomial and by utilizing the reseeding capacity of the circuit. The circuit combines a double-tier linear feedback circuit with zero forcing methods, resulting in more than 70% transition reduction, thus significantly lowering power dissipation. The behaviour of the proposed circuit is assessed for characteristic polynomials with degrees ranging from 4 to 128 using various Linear Feedback Shift Register (LFSR) topologies. For reconfigurable HDL and ASIC synthesis, the power-aware RP-PRPG can be used to generate an efficient set of stream ciphers as well as applications involving the scan-for-test protocol. Full article

Stochastic circuits are used in applications that require low area and power consumption. The computing performed using these circuits is referred to as Stochastic computing (SC). The arithmetic operations in this computing can be realized using minimum logic circuits. The SC system allows a tradeoff of computational accuracy and area; thereby, the challenge in SC is improving the accuracy. The accuracy depends on the SC system’s stochastic number generator (SNG) part. SNGs provide the appropriate stochastic input required for stochastic computation. Hence we explore the accuracy in SC for various arithmetic operations performed using stochastic computing with the help of logic circuits. The contributions in this paper are; first, we have performed stochastic computing for arithmetic components using two different SNGs. The SNGs considered are Linear Feed-back Shift Register (LFSR) -based traditional stochastic number generators and S-box-based stochastic number generators. Second, the arithmetic components are implemented in a combinational circuit for algebraic expression in the stochastic domain using two different SNGs. Third, computational analysis for stochastic arithmetic components and the stochastic algebraic equation has been conducted. Finally, accuracy analysis and measurement are performed between LFSR-based computation and S-box-based computation. The novel aspect of this work is the use of S-box-based SNG in the development of stochastic computing in arithmetic components. Also, the implementation of stochastic computing in the combinational circuit using the developed basic arithmetic components, and exploration of accuracy with respect to stochastic number generators used is presented. Full article

The importance of high resolution range profiles (HRRPs) for radar applications like tracking or classification is well known. In the scientific literature several approaches have been investigated to obtain HRRPs from wideband radar signals. Recent works show that noise radar waveforms can be exploited in this sense due to their high resolution and low peak to sidelobe ratio (PSLR) properties. However their use can cause some issues in applications where long time integrations are required, e.g., in the presence of a low effective radiated power (ERP) transmitter: recording the reference signal in this case would be difficult due to the big quantity of data. This work proposes a real time digital processing schematic based on linear feedback shift registers (LFSRs) which is very flexible and has a low computational burden: its internal state can be easily controlled and reproduced in reception, where a multichannel correlator is exploited as matched filter. The resulting signal, compared to typical “pulse compression” and noise radar waveforms, shows similar performances but a lower order of complexity in terms of real time generation and reception. Full article

Pseudorandom number generation (PRNG) is the main security tool in low-cost passive radio-frequency identification (RFID) technologies, such as EPC Gen2. We present a lightweight PRNG design for low-cost passive RFID tags, named J3Gen. J3Gen is based on a linear feedback shift register (LFSR) configured with multiple feedback polynomials. The polynomials are alternated during the generation of sequences via a physical source of randomness. J3Gen successfully handles the inherent linearity of LFSR based PRNGs and satisfies the statistical requirements imposed by the EPC Gen2 standard. A hardware implementation of J3Gen is presented and evaluated with regard to different design parameters, defining the key-equivalence security and nonlinearity of the design. The results of a SPICE simulation confirm the power-consumption suitability of the proposal. Full article