Search Results (16)

Fine-pitch redistribution layers (RDLs) are key enabling technologies for fan-out wafer-level packaging (FOWLP)-based interposers used in chiplet and high-bandwidth memory (HBM) integration. In this study, a CAR-based photolithography process optimized for fine-pitch RDL fabrication was evaluated to realize 2 μm/2 μm line/space (L/S) RDL structures in an FOWLP environment. Key lithographic parameters, including exposure energy, focus offset, and thermal processing conditions, were systematically optimized to establish a stable and reproducible process window. Cross-sectional analysis confirmed the structural integrity of the electroplated RDL features formed under the optimized conditions. To assess functional feasibility, channel-level electrical simulations were performed using JEDEC-defined HBM3 signal assignments. Simulated eye diagrams indicate that the fabricated fine-pitch RDL interconnects are capable of supporting HBM3-class signal transmission with a moderate level of signal integrity. The presence of jitter and noise suggests that further optimization of RDL transmission line impedance is required. Rather than presenting a fully optimized interposer solution, this work provides an engineering-level assessment of lithographic and process constraints associated with implementing 2 μm class RDLs in FOWLP-based interposers, offering practical insight into fine-pitch RDL process window definition for advanced packaging applications. This work uniquely combines systematic CAR-based lithography optimization with cross-sectional structural validation and HBM3-class channel-level simulations to define a practical process window for 2 μm/2 μm RDLs in an FOWLP environment. Full article

The increasing power density of 2.5D and 3D chiplets imposes severe thermal constraints that have a direct impact on the performance and long-term reliability of high-performance computing systems. Stacked and laterally integrated dies, which generate hundreds of watts per package, create localized hotspots and inconsistent temperature fields, major obstacles to scalable heterogeneous integration. Research efforts have addressed these challenges by finite element and compact heat modeling, thermal interface material optimization (TIM), and advanced cooling solutions such as micro-channel liquid cooling and cold racks. While these approaches provide valuable insights, most remain case-specific, focusing on isolated packages or single design variables, and lack a general methodology for assessing thermal feasibility at an early stage. This review consolidates and critically analyzes contributions to thermal modeling at the package level, interposer thermal spreading, thermal characterization of TIMs, and the development of cooling technologies. A comparative review of published studies indicates a consistent threshold: 2.5D stacks are viable under air cooling at approximately 300 W, whereas 3D stacks require liquid or hybrid cooling in conjunction with high-performance thermal interface materials at about 350 W. The investigations identify interposer conductivity, thermal interface material thickness, and hotspot power distribution as the primary sensitivity elements. This study explores Thermal Feasibility Maps (TFMs), defined as multidimensional charts parameterized by architecture, cooling regime, and material stack. TFMs provide a systematic framework for comparing design trade-offs and support architecture cooling co-design in advanced chiplet systems. Full article

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller, modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents ChipletQuake, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, ChipletQuake detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects hardware Trojans and interposer tampering. Full article

High-purity germanium (HPGe) detectors occupy a prominent position in fields such as radiation detection and aerospace because of their excellent energy resolution and wide detection range. To achieve a broader detection range, conventional HPGe detectors often need to be expanded to cubic-centimeter-scale volumes. However, this increase in volume leads to a large detector area, which in turn increases the detector capacitance, affecting the detector’s noise level and performance. To address this issue, this study proposes a novel high-purity germanium drift detector (HPGeDD). The design features a small-area central collecting cathode surrounded by concentric anode rings, with a resistive chain interposed between the anode rings to achieve self-dividing voltage. This design ensures that the detector’s capacitance is only related to the area of the central collecting cathode, independent of the overall active area, thus achieving a balance between a small capacitance and large active area. Electrical performance simulations of the novel detector were conducted using the semiconductor simulation software Sentaurus TCAD (P-2019.03). The results show a smooth electric potential distribution within the detector, forming a lateral electric field, as well as a lateral hole drift channel precisely directed toward the collecting cathode. Furthermore, simulations of heavy ion incidence were performed to investigate the detector’s carrier collection characteristics. The simulation results demonstrate that the HPGeDD exhibits advantages such as fast signal response and short collection time. The design proposal presented in this study offers a new solution to the problem of excessive capacitance in conventional HPGe detectors, expands their application scope, and provides theoretical guidance for subsequent improvements, optimizations, and practical manufacturing. Full article

In this article, electrical performance analysis of high-speed interconnection and power delivery network (PDN) in low-loss glass substrate-based interposers is conducted considering signal integrity (SI) and power integrity (PI). The low-loss glass substrate is a superior alternative to silicon substrate in terms of high-speed signaling and fabrication yield. However, the low-loss of the substrate is vulnerable to power/ground noise in the PDN since the low-loss property of the substrate cannot suppress the noise naturally. In this article, an in-depth electrical performance analysis is conducted based on various measurements and simulations to fully benefit the advantages of the low-loss glass substrate. First, the fabrication process and test vehicles for the analysis are explained. Using the test vehicles, the electrical performance of the glass interposer’s high-speed interconnection is compared with those of silicon and organic interposers. The insertion loss, eye-diagrams, and signal bandwidths of three interposer channels are compared and analyzed based on electromagnetic (EM) and circuit simulations. Also, the electrical performance of the through glass via (TGV) channel is measured and compared with through silicon via (TSV) channel. The high-speed interconnection of the glass interposer showed better performance for most of the parameters which is more suitable for maintaining the SI. Even though the low-loss of the glass substrate ensured the SI, power/ground noise issues in the PDN must be analyzed and solved. In this article, various cases inducing the power/ground noise in the PDN are considered, simulated, and measured. To solve the issues, ground TGV design and electromagnetic bandgap (EBG) design are proposed for an efficient broadband suppression of the noise generated in the glass interposer PDN. Full article

In this article, a novel statistical approach is proposed and applied to co-design signal and power integrity (SI/PI) in high-speed interconnects considering the non-linear power/ground noise generated by parallel buffers and bit-patterns. With increased data rates and decreased operating voltages, the allowed noise margin in high-speed interconnects is continuously reduced, and this trend requires SI/PI co-design. Specifically, non-linear power/ground noise associated with simultaneous switching circuits sharing a power delivery network (PDN) and bit-patterns must be carefully considered during the interconnects’ design and analysis phase. In many cases, conventional electromagnetic (EM) and transient circuit simulators require heavy computational resources or even fail to deliver an accurate result. The proposed statistical method estimates the statistical eye-diagram in the high-speed interconnect considering power/ground noise and bit-patterns such as data bus inversion (DBI) coding. The accuracy and computational efficiency of the proposed method are validated by comparing the result with HSPICE transient simulation result. The proposed method is also compared with conventional statistical methods, such as peak distortion analysis (PDA) and statistical channel simulation in the transient simulator. Lastly, the proposed method is applied to the SI/PI co-design and co-analysis in the high bandwidth memory (HBM) interposer channel. Impacts of decoupling capacitors on hierarchical PDN impedance, statistical eye-diagram of the HBM channel, and bit error rate (BER) Bathtub curves are summarized. Finally, the BER eye-diagram is derived from the estimated statistical eye-diagram for timing and voltage analysis. The impacts of hierarchical PDN design and bit-patterns on SI/PI are discussed. Full article

Following Moore’s law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 $\mathsf{\mu }$m long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks. Full article

In this paper, first, a broad overview of existing covert channel communication-based security attacks is provided. Such covert channels establish a communication link between two entities that are not authorized to share data. The secret data is encoded into different forms of signals, such as delay, temperature, or hard drive location. These signals and information are then decoded by the receiver to retrieve the secret data, thereby mitigating some of the existing security measures. The important steps of covert channel attacks are described, such as data encoding, communication protocol, data decoding, and models to estimate communication bandwidth and bit error rate. Countermeasures against covert channels and existing covert channel detection techniques are also summarized. In the second part of the paper, the implications of such attacks for emerging packaging technologies, such as 2.5D/3D integration are discussed. Several covert channel threat models for 2.5D/3D ICs are also proposed. Full article

This article proposes a three-dimensional heterogenous-integrated (3DHI) switchable bandpass filter bank with two independent wideband filter channels that cover 26–40 GHz and 32.5–40 GHz, respectively. An accurate wafer-level process with a high hollowed ratio of the applied 8-inch high-resistivity-silicon (HR-Si) interposer wafers is presented to form both compact filter channels. Above the interdigital filter patterns fabricated on the bottom interposer wafer, deep cavities are etched in the cap interposer wafer to improve the quality factor of the filter bank. Besides the cavities, the cap interposer wafer is 35% hollow inside, which two bare dies of GaAs single-pole double-throw (SPDT) switches and two thin film resistors are attached to the bottom interposer after the wafer-to-wafer (W2W) bonding. To ensure good out-of-band performance, a 3D EM co-simulation of the switch layout at the chip level and filter patterns at the package level is applied. Measurement results show that the switchable filter bank achieves a high isolation of 50 dB and a competitive shape factor (BW_30dB/BW_3dB) of about 1.3. In addition, the size of the switchable filter bank is only 7.0 mm × 3.5 mm × 0.6 mm, and the weight is only 0.1 g. Full article

In this study, power/ground noise suppression structures were designed based on a proposed dispersion analysis for packages and interposers with low-loss substrates. Low-loss substrates are suitable for maintaining signal integrity (SI) of high-speed channels operating at high data rates. However, when the power/ground noise is generated in the power delivery network (PDN), low-loss substrates cannot suppress the power/ground noise, thereby causing PDN-induced crosstalk and various power integrity (PI) issues. To solve these issues, noise suppression structures generating electromagnetic bandgap were proposed and designed. The mechanism of the proposed structures was examined based on a proposed dispersion analysis. The proposed structures were designed and fabricated in glass interposer test vehicles, and the effectiveness of the structures on power/ground noise suppression was experimentally validated by measuring the noise suppression band. The proposed dispersion analysis was also verified by comparing the derived noise stopband edges ($f_{\mathrm{L}}$ and $f_{\mathrm{U}}$) with electromagnetic (EM) simulation and experimental results, and they all showed good agreement. Compared to EM simulation, the proposed method required smaller computational resources but showed good accuracy. Using the proposed dispersion analysis, various power/ground noise suppression bands were designed considering the applications and design rules of packages and interposers. With measurements and EM/circuit simulations, the effectiveness of the designed structure in maintaining SI/PI was verified. By adopting the designed structures, the noise transfer properties in the PDN were suppressed in the target suppression frequency band, which is key for PI design. Finally, it was verified that the proposed structures were capable of suppressing power/ground noise propagation in the PDN by analyzing PDN-induced crosstalk in the high-speed channel. Full article

In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel. Full article

With the advantage of faster data access than traditional disks, in-memory database systems, such as Redis and Memcached, have been widely applied in data centers and embedded systems. The performance of in-memory database greatly depends on the access speed of memory. With the requirement of high bandwidth and low energy, die-stacked memory (e.g., High Bandwidth Memory (HBM)) has been developed to extend the channel number and width. However, the capacity of die-stacked memory is limited due to the interposer challenge. Thus, hybrid memory system with traditional Dynamic Random Access Memory (DRAM) and die-stacked memory emerges. Existing works have proposed to place and manage data on hybrid memory architecture in the view of hardware. This paper considers to manage in-memory database data in hybrid memory in the view of application. We first perform a preliminary study on the hotness distribution of client requests on Redis. From the results, we observe that most requests happen on a small portion of data objects in in-memory database. Then, we propose the Application-oriented Data Migration called ADM to accelerate in-memory database on hybrid memory. We design a hotness management method and two migration policies to migrate data into or out of HBM. We take Redis under comprehensive benchmarks as a case study for the proposed method. Through the experimental results, it is verified that our proposed method can effectively gain performance improvement and reduce energy consumption compared with existing Redis database. Full article

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient. Full article

Sprint interval training (SIT) has emerged as a time-efficient training regimen for young individuals. Here, we studied whether SIT is effective also in elderly individuals and whether the training response was affected by treatment with the antioxidants vitamin C and E. Recreationally active elderly (mean age 65) men received either vitamin C (1 g/day) and vitamin E (235 mg/day) or placebo. Training consisted of nine SIT sessions (three sessions/week for three weeks of 4-6 repetitions of 30-s all-out cycling sprints) interposed by 4 min rest. Vastus lateralis muscle biopsies were taken before, 1 h after, and 24 h after the first and last SIT sessions. At the end of the three weeks of training, SIT-induced changes in relative mRNA expression of reactive oxygen/nitrogen species (ROS)- and mitochondria-related proteins, inflammatory mediators, and the sarcoplasmic reticulum Ca²⁺ channel, the ryanodine receptor 1 (RyR1), were blunted in the vitamin treated group. Western blots frequently showed a major (>50%) decrease in the full-length expression of RyR1 24 h after SIT sessions; in the trained state, vitamin treatment seemed to provide protection against this severe RyR1 modification. Power at exhaustion during an incremental cycling test was increased by ~5% at the end of the training period, whereas maximal oxygen uptake remained unchanged; vitamin treatment did not affect these measures. In conclusion, treatment with the antioxidants vitamin C and E blunts SIT-induced cellular signaling in skeletal muscle of elderly individuals, while the present training regimen was too short or too intense for the changes in signaling to be translated into a clear-cut change in physical performance. Full article

The functional activity of channel-forming peptides and proteins is most directly verified by monitoring the flow of physiologically relevant inorganic ions, such as Na⁺, K⁺ and Cl⁻, along the ion channels. Electrical current measurements across bilayer lipid membranes (BLMs) interposed between two aqueous solutions have been widely employed to this end and are still extensively used. However, a major drawback of BLMs is their fragility, high sensitivity toward vibrations and mechanical shocks, and low resistance to electric fields. To overcome this problem, metal-supported tethered BLMs (tBLMs) have been devised, where the BLM is anchored to the metal via a hydrophilic spacer that replaces and mimics the water phase on the metal side. However, only mercury-supported tBLMs can measure and regulate the flow of the above inorganic ions, thanks to mercury liquid state and high hydrogen overpotential. This review summarizes the main results achieved by BLMs incorporating voltage-gated channel-forming peptides, interpreting them on the basis of a kinetic mechanism of nucleation and growth. Hg-supported tBLMs are then described, and their potential for the investigation of voltage-gated and ohmic channels is illustrated by the use of different electrochemical techniques. Full article