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16 pages, 7086 KB

Open AccessArticle

4.11 A/1650 V Sapphire-Substrate GaN MIS-HEMTs with Thin Buffer for Medium-Voltage Power Applications

by Changhao Chen, Yang Liu, Xiaowei Zhou, Peixian Li, Yongfeng Zhang, Bo Yang, Zili Yang and Junchun Bai

Micromachines 2026, 17(2), 233; https://doi.org/10.3390/mi17020233 - 11 Feb 2026

Viewed by 916

Abstract

The substantially lower breakdown electric field of Si compared to GaN necessitates thick buffer layers in Si-based GaN power devices for medium-voltage applications, significantly increasing cost. Recently, sapphire substrates, offering high electrical insulation and excellent mechanical strength, have emerged as a promising alternative. In this work, we demonstrate a CMOS-compatible process for sapphire-based GaN MIS-HEMTs utilizing a thin buffer layer. The fabricated devices with a W_G of 20.4 mm and an L_GD of 24 μm achieve a high off-state breakdown voltage >1650 V and a maximum on-state current > 4.1 A, with tight statistical distributions of V_TH and R_ON across the wafer. Furthermore, statistical characterization results of dynamic R_ON and leakage current under electrical stress conditions at both room temperature and 150 °C, confirm operational viability at high temperatures. Finally, long-term reliability for 650 V operation is validated by high-temperature reverse bias (HTRB) accelerated aging tests. Full article

(This article belongs to the Special Issue III-V Optoelectronics and Semiconductor Process Technology, Second Edition)

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9 pages, 2943 KB

Open AccessArticle

Improve Intermetal Dielectric Process for HTRB Stability in Power GaN High Electron Mobility Transistor (HEMT) by unbiased-Highly Accelerated Stress Testing (uHAST)

by Yu-Ting Chuang, Niall Tumilty and Tian-Li Wu

Micromachines 2025, 16(11), 1233; https://doi.org/10.3390/mi16111233 - 30 Oct 2025

Cited by 1 | Viewed by 1402

Abstract

This study investigates a severe high-temperature reverse bias (HTRB) failure observed in GaN HEMTs, with devices failing in under 24 h. We conducted an in-depth analysis of the electrical and physical failure mechanisms, revealing that unbiased-highly accelerated stress testing (uHAST) can effectively induce dielectric delamination. The electrical and physical characteristics of devices post-delamination demonstrated a strong correlation between delamination at the nitride–polyimide interface and an increase in off-state drain leakage current (I_DSS). Our findings led to the removal of a suspected process step involving the use of the reactive chemical, N-methyl-2-pyrrolidone (NMP), before and after polyimide deposition. This critical process change yielded a significant improvement in reliability; while the initial failure rate was 25% at 24 h, three lots of 260 parts subsequently survived 1000 h of HTRB stress with no failure. In conclusion, uHAST is a valuable reliability testing tool for assessing package and film adhesion, leveraging high pressure and moisture to quickly identify and troubleshoot delamination-related reliability issues. Full article

(This article belongs to the Special Issue GaN-Based Materials and Devices: Research and Applications, 2nd Edition)

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11 pages, 2795 KB

Open AccessArticle

Experiment and Analysis of Termination Robustness Design for 1200 V 4H-SiC MOSFET

by Mengyuan Yu, Yi Shen, Hongping Ma and Qingchun Zhang

Nanomaterials 2025, 15(11), 805; https://doi.org/10.3390/nano15110805 - 27 May 2025

Cited by 4 | Viewed by 2665

Abstract

This study investigates the degradation mechanisms of 1200 V SiC MOSFETs during High-temperature Reverse Bias (HTRB) reliability testing, focusing on breakdown voltage (BV) reduction. Experimental results reveal that trapped charges at the SiC/SiO₂ interface in the termination region alter electric field distribution, leading to premature breakdown. To address this issue, an optimized termination structure is proposed, incorporating reduced spacing between adjacent field rings and additional outer rings. TCAD simulations and experimental validation demonstrate that the improved design stabilizes BV within 2% deviation during 1000 h HTRB testing, which significantly enhances termination robustness. Full article

(This article belongs to the Section Nanoelectronics, Nanosensors and Devices)

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12 pages, 4150 KB

Open AccessArticle

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses

by Laura Anoldo, Edoardo Zanetti, Walter Coco, Alfio Russo, Patrick Fiorenza and Fabrizio Roccaforte

Materials 2024, 17(8), 1908; https://doi.org/10.3390/ma17081908 - 20 Apr 2024

Cited by 9 | Viewed by 4570

Abstract

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO₂ interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler–Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔV_th and ΔV_FN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔV_th and ΔV_FN, while HTRB showed only a 4% variation in both ΔV_th and ΔV_FN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration. Full article

(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)

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8 pages, 1714 KB

Open AccessArticle

Optimization of the Field Plate Design of a 1200 V p-GaN Power High-Electron-Mobility Transistor

by Chia-Hao Liu, Chong-Rong Huang, Hsiang-Chun Wang, Yi-Jie Kang, Hsien-Chin Chiu, Hsuan-Ling Kao, Kuo-Hsiung Chu, Hao-Chung Kuo, Chih-Tien Chen and Kuo-Jen Chang

Micromachines 2022, 13(9), 1554; https://doi.org/10.3390/mi13091554 - 19 Sep 2022

Cited by 6 | Viewed by 5122

Abstract

This study optimized the field plate (FP) design (i.e., the number and positions of FP layers) of p-GaN power high-electron-mobility transistors (HEMTs) on the basic of simulations conducted using the technology computer-aided design software of Silvaco. Devices with zero, two, and three FP layers were designed. The FP layers of the HEMTs dispersed the electric field between the gate and drain regions. The device with two FP layers exhibited a high off-state breakdown voltage of 1549 V because of the long distance between its first FP layer and the channel. The devices were subjected to high-temperature reverse bias and high-temperature gate bias measurements to examine their characteristics, which satisfied the reliability specifications of JEDEC. Full article

(This article belongs to the Special Issue Novel Electronics Devices Integrated with 2D Quantum Materials)

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13 pages, 339 KB

Open AccessArticle

Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs Lifetime by Reliability Tests

by Fabio Principato, Giuseppe Allegra, Corrado Cappello, Olivier Crepel, Nicola Nicosia, Salvatore D′Arrigo, Vincenzo Cantarella, Alessandro Di Mauro, Leonardo Abbene, Marcello Mirabello and Francesco Pintacuda

Sensors 2021, 21(16), 5627; https://doi.org/10.3390/s21165627 - 20 Aug 2021

Cited by 11 | Viewed by 4538

Abstract

High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to

2 \times

^{11}

(n/cm

^{2}

). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device. Full article

(This article belongs to the Section Physical Sensors)

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