Search Results (424)

This study presents an innovative wedge-shaped inlet weir-type microfluidic chip designed to address common issues of clogging and inefficiency in microfiltration processes. Driven solely by centrifugal force, the chip integrates a crossflow separation mechanism and enables selective droplet sorting based on size, without the need for external pumps. Fabricated from PMMA, the device features a central elliptical chamber, a wedge-shaped inlet, and spiral microchannels. These structures leverage shear stress and Dean vortices under centrifugal fields to achieve high-throughput separation of droplets with different diameters. Using water-in-oil emulsions as a model system, we systematically investigated the effects of geometric parameters and rotational speed on separation performance. A theoretical model was developed to derive the critical droplet size based on force balance, accounting for centrifugal force, viscous drag, pressure differentials, and surface tension. Experimental results demonstrate that the chip can effectively separate droplets ranging from 0 to 400 μm in diameter at 200 rpm, achieving a sorting efficiency of up to 72% and a separation threshold (cutoff accuracy) of 98.2%. Fluorescence analysis confirmed the absence of cross-contamination during single-chip operation. This work offers a structure-guided, efficient, and contamination-free droplet sorting strategy with broad potential applications in biomedical diagnostics and drug screening. Full article

Turbo Codes (TCs) are a family of convolutional codes that provide powerful Forward Error Correction (FEC) and operate near the Shannon limit for channel capacity. In the context of modern communication systems, such as those conforming to the DVB-RCS2 standard, Turbo Encoders (TEs) play a crucial role in ensuring robust data transmission over noisy satellite links. A key computational bottleneck in the Turbo Encoder is the non-uniform interleaving stage, where input bits are rearranged according to a dynamically generated permutation pattern. This stage often requires the intermediate storage of data, resulting in increased latency and reduced throughput, especially in embedded or real-time systems. This paper introduces a vector processing algorithm designed to accelerate the interleaving stage of the Turbo Encoder. The proposed algorithm is tailored for vector DSP architectures (e.g., CEVA-XC4500), and leverages the hardware’s SIMD capabilities to perform the permutation operation in a structured, phase-wise manner. Our method adopts a modular Load–Execute–Store design, facilitating efficient memory alignment, deterministic latency, and hardware portability. We present a detailed breakdown of the algorithm’s implementation, compare it with a conventional scalar (serial) model, and analyze its compatibility with the DVB-RCS2 specification. Experimental results demonstrate significant performance improvements, achieving a speed-up factor of up to 3.4× in total cycles, 4.8× in write operations, and 7.3× in read operations, relative to the baseline scalar implementation. The findings highlight the effectiveness of vectorized permutation in FEC pipelines and its relevance for high-throughput, low-power communication systems. Full article

This study addresses the parallel operation of multiple compressor units in the gas injection process of gas storage facilities. A multi-objective optimization model based on the NSGA-II algorithm is proposed to maximize gas injection volume while minimizing energy consumption. Thermodynamic models of compressors and flow–heat transfer models of air coolers are established. The influence of key factors, including inlet and outlet pressures, temperatures, and natural gas composition, on compressor performance is analyzed using the control variable method. The results indicate that the first-stage inlet pressure has the most significant impact on gas throughput, and higher compression ratios lead to increased specific energy consumption. The NSGA-II algorithm is applied to optimize compressor start–stop strategies and air cooler speed matching under high, medium, and low compression ratio conditions. This study reveals that reducing the compression ratio significantly enhances the energy-saving potential. Under the investigated conditions, adjusting air cooler speed can achieve approximately 2% energy savings at high compression ratios, whereas at low compression ratios, the energy-saving potential reaches up to 8%. This research provides theoretical guidance and technical support for the efficient operation of gas storage compressor units. Full article

Convolutional neural networks (CNNs) are widely used in geotechnical engineering. Real-time detection in complex geological environments, combined with the strict power constraints of embedded devices, makes Field-Programmable Gate Array (FPGA) platforms ideal for accelerating CNNs. Conventional parallelization strategies in FPGA-based accelerators often result in imbalanced resource utilization and computational inefficiency due to varying kernel sizes. To address this issue, we propose a customized heterogeneous hybrid parallel strategy and refine the bit-splitting approach for Digital Signal Processor (DSP) resources, improving timing performance and reducing Look-Up Table (LUT) consumption. Using this strategy, we deploy the lightweight YOLOv5n network on an FPGA platform, creating a high-speed, low-power subsurface geotechnical defect-detection system. A layer-wise quantization strategy reduces the model size with negligible mean average precision (mAP) loss. Operating at 300 MHz, the system reduces LUT usage by 33%, achieves a peak throughput of 328.25 GOPs in convolutional layers, and an overall throughput of 157.04 GOPs, with a power consumption of 9.4 W and energy efficiency of 16.7 GOPs/W. This implementation demonstrates more balanced performance improvements than existing solutions. Full article

In axial-flow combine harvesters, guide vanes direct crop material through the threshing and separation unit. The research object has the standard configuration of guide vane assembly; the six rear vanes are adjustable, while the two front vanes—located in the threshing zone—are fixed, which limits material flow control. In European conditions, where crop biomass is typically higher, improved control in the threshing area is essential to reduce losses and maintain grain quality. This study introduces a guide vane angle evaluation to combine performance and a modified guide vane system that enables all eight vanes to be adjusted simultaneously between 10–35°. Field tests were conducted using two identical combines (A and B) in the same winter wheat field, under identical operating conditions. Combine A was equipped with the modified system, while Combine B retained the original manufacturer configuration. Both machines operated at a rotor speed of 980 rpm and a concave clearance of 15 mm. Results showed that Combine A achieved higher throughput (23.78 kg s⁻¹), lower broken grain (0.18%), and lower fuel consumption (0.84 L t⁻¹) compared to Combine B (20.6 kg s⁻¹, 0.61%, 0.99 L t⁻¹, respectively); the separation and sieve losses were also reduced in Combine A. Analysis of the results demonstrated that full-range guide vane adjustability—including in the threshing zone—can improve crop flow, grain separation, and harvesting efficiency in high-yield conditions. Full article

The development of beyond 5G (B5G) future wireless communication networks (FWCN) needs novel solutions to support high-speed, reliable, and low-latency communication. Unmanned aerial vehicles (UAVs) and reconfigurable intelligent surfaces (RISs) are promising techniques that can enhance wireless connectivity in urban environments where tall buildings block line-of-sight (LoS) links. However, existing UAV-assisted communication strategies do not fully address key challenges like mobility management, handover failures (HOFs), and path disorders in dense urban environments. This paper introduces a deep deterministic policy gradient (DDPG)-based UAV-RIS framework to overcome these limitations. The proposed framework jointly optimizes UAV trajectories and RIS phase shifts to improve throughput, energy efficiency (EE), and LoS probability while reducing outage probability (OP) and HOF. A modified K-means clustering algorithm is used to efficiently partition the ground users (GUs) considering the newly added GUs as well. The DDPG algorithm, based on reinforcement learning (RL), adapts UAV positioning and RIS configurations in a continuous action space. Simulation results show that the proposed approach significantly reduces HOF and OP, increases EE, enhances network throughput, and improves LoS probability compared to UAV-only, RIS-only, and without UAV-RIS deployments. Additionally, by dynamically adjusting UAV locations and RIS phase shifts based on GU mobility patterns, the framework further enhances connectivity and reliability. The findings highlight its potential to transform urban wireless communication by mitigating LoS blockages and ensuring uninterrupted connectivity in dense environments. Full article

This study presents a novel artificial intelligence-driven architecture for real-time sensor fusion in autonomous vehicles (AVs), leveraging Apache Kafka and MongoDB for synchronous and asynchronous data processing to enhance resilience against sensor failures and dynamic conditions. We introduce Chaotic AdaBoost (CAB), an advanced variant of AdaBoost that integrates a logistic chaotic map into its weight update process, overcoming the limitations of deterministic ensemble methods. CAB is evaluated alongside k-Nearest Neighbors (kNNs), Artificial Neural Networks (ANNs), standard AdaBoost (AB), Gradient Boosting (GBa), and Random Forest (RF) for speed and acceleration prediction using CARLA simulator data. CAB achieves a superior 99.3% accuracy (MSE: 0.018 for acceleration, 0.010 for speed; MAE: 0.020 for acceleration, 0.012 for speed; R²: 0.993 for acceleration, 0.997 for speed), a mean Time-To-Collision (TTC) of 3.2 s, and jerk of 0.15 m/s³, outperforming AB (98.5%, MSE: 0.15, TTC: 2.8 s, jerk: 0.22 m/s³), GB (99.1%), ANN (98.2%), RF (97.5%), and kNN (87.0%). This logistic map-enhanced adaptability, reducing MSE by 88% over AB, ensures robust anomaly detection and data fusion under uncertainty, critical for AV safety and comfort. Despite a 20% increase in training time (72 s vs. 60 s for AB), CAB’s integration with Kafka’s high-throughput streaming maintains real-time efficacy, offering a scalable framework that advances operational reliability and passenger experience in autonomous driving. Full article

This work presents a novel dual-polarized antenna array tailored for Internet of Things (IoT) applications, specifically designed to operate in the millimeter-wave (mm-wave) spectrum within the frequency range of 30–60 GHz. Leveraging printed ridge gap waveguide (PRGW) technology, the antenna ensures robust performance by eliminating parasitic radiation from the feed network, thus significantly enhancing the reliability and efficiency required by IoT communication systems, particularly for smart cities, autonomous vehicles, and high-speed sensor networks. The proposed antenna achieves superior radiation characteristics through a cross-shaped magneto-electric (ME) dipole backed by an artificial magnetic conductor (AMC) cavity and electromagnetic bandgap (EBG) structures. These features suppress surface waves, reduce edge diffraction, and minimize back-lobe emissions, enabling stable, high-quality IoT connectivity. The antenna demonstrates a wide impedance bandwidth of 24% centered at 30 GHz and exceptional isolation exceeding 40 dB, ensuring interference-free dual-polarized operation crucial for densely populated IoT environments. Fabrication and testing validate the design, consistently achieving a gain of approximately 13.88 dBi across the operational bandwidth. The antenna’s performance effectively addresses the critical requirements of emerging IoT systems, including ultra-high data throughput, reduced latency, and robust wireless connectivity, essential for real-time applications such as healthcare monitoring, vehicular communication, and smart infrastructure. Full article

Saffron is a high-cost spice due to the specific conditions for optimal growth and because of being harvested by hand. The massive income from commercializing saffron substituted with other plant parts or low-cost spices makes this spice the main target of fraudsters. Background: Different methods have been developed for detecting saffron adulteration. Most of them are time consuming and complex, and in some types of analysis, the whole untargeted dataset is combined with advanced chemometric tools to differentiate authentic from non-authentic saffron. The official method, combining UV–vis spectroscopy and LC to determine the colour strength and the crocin content, is unable to detect saffron adulterants (safflower, marigold, or turmeric) added at a level lower than 20% (w/w). As a result, innovative approaches based on rapid, high-throughput methods for the identification of adulterated saffron samples are urgently demanded to counteract food frauds. Methods: This paper describes, for the first time, the development of a method combining Direct Analysis in Real Time (DART) with the triple quadrupole MS EVOQ based on the detection of specific MS/MS transitions, promoting a rapid, robust and chromatography-free method capable of monitoring safflower and turmeric adulteration in saffron. Results: The method proved to reach low LODs, allowing the determination of tiny amounts of turmeric and safflower powder in saffron as low as 3% and 5%, respectively, speeding up the whole analytical workflow and enabling us to perform 20 analyses in 10 min. Finally, the greenness of the method was also assessed according to the 0.88 score achieved by submitting it to the greenness calculator AGREE. Conclusions: Given its speed, simplicity, and robustness, this method stands out as a strong candidate for routine implementation in testing laboratories as a rapid screening tool to detect saffron adulteration with safflower or turmeric. Full article

Lossless image compression plays a vital role in improving data storage and transmission efficiency without compromising data integrity. However, the throughput of current lossless compression and decompression systems remains limited and is unable to meet the growing demands of high-speed data transfer. To address this challenge, a previously proposed hybrid lossless compression and decompression algorithm has been implemented on an FPGA platform. This implementation significantly improves processing speed and efficiency. A multi-core system architecture is introduced, utilizing the processing system (PS) and programmable logic (PL) of a Xilinx Zynq-706 evaluation board. The PS handles coordination. The PL performs compression and decompression using multiple cores. Each core can process up to eight image tiles at the same time. The compression process is designed with a four-stage pipeline, and decompression is managed by a dynamic state machine to ensure optimized control. The parallel architecture and innovative algorithm design enable high-throughput operation, achieving compression and decompression rates of 480 Msubpixels/s and 372 Msubpixels/s, respectively. Through this work, a practical and high-performance solution for real-time lossless image compression is demonstrated. Full article

Modern power systems, particularly those integrating smart grid and microgrid functionalities, demand efficient high-speed data processing to manage increasingly complex operational requirements. In response to these challenges, this paper proposes a high-speed Sampled Measured Values (SMVs) subscriber design that leverages the programmability of Multi-Processor System-on-Chip (MPSoC) technology and the parallel processing capabilities of Field-Programmable Gate Arrays (FPGAs). By offloading SMVs data decoding to dedicated FPGA hardware, the approach significantly reduces processing latency and delivers deterministic performance, thereby surpassing traditional software-based implementations. This hardware acceleration is achieved without sacrificing flexibility, ensuring compatibility with emerging standards in IEC 61850 and offering scalability for expanding substation and grid communication networks. Experimental validations demonstrate lower end-to-end delays and improved throughput, highlighting the potential of the proposed system to meet stringent real-time requirements for monitoring and control in evolving smart grids. Full article

The Number Theoretic Transform (NTT) is a cornerstone for efficient polynomial multiplication, which is fundamental to lattice-based cryptographic algorithms such as CRYSTALS-Kyber—a leading candidate in post-quantum cryptography (PQC). However, existing NTT accelerators often rely on integer multiplier-based modular reduction techniques, such as Barrett or Montgomery reduction, which introduce significant computational overhead and hardware resource consumption. These accelerators also lack optimization in unified architectures for forward (FNTT) and inverse (INTT) transformations. Addressing these research gaps, this paper introduces a novel, high-speed NTT accelerator tailored specifically for CRYSTALS-Kyber. The proposed design employs an innovative shift-add modular reduction mechanism, eliminating the need for integer multipliers, thereby reducing critical path delay and enhancing circuit frequency. A unified pipelined butterfly unit, capable of performing FNTT and INTT operations through Cooley–Tukey and Gentleman–Sande configurations, is integrated into the architecture. Additionally, a highly efficient data handling mechanism based on Register banks supports seamless memory access, ensuring continuous and parallel processing. The complete architecture, implemented in Verilog HDL, has been evaluated on FPGA platforms (Virtex-5, Virtex-6, and Virtex-7). Post place-and-route results demonstrate a maximum operating frequency of 261 MHz on Virtex-7, achieving a throughput of 290.69 Kbps—1.45× and 1.24× higher than its performance on Virtex-5 and Virtex-6, respectively. Furthermore, the design boasts an impressive throughput-per-slice metric of 111.63, underscoring its resource efficiency. With a 1.27× reduction in computation time compared to state-of-the-art single butterfly unit-based NTT accelerators, this work establishes a new benchmark in advancing secure and scalable cryptographic hardware solutions. Full article

Maize is a vital staple crop significantly affected by climate change, necessitating urgent efforts to enhance its resilience. This review analyzes advanced methodologies for maize improvement, focusing on the identification of genetic determinants through QTL mapping, candidate gene mining, and GWAS. We highlight the transformative potential of CRISPR gene editing for identifying key regulators in maize development and the utility of virus-induced gene silencing (VIGS) for functional genomics. Additionally, we discuss breeding strategies leveraging the genetic diversity of maize wild relatives and innovations such as speed breeding and genomic selection (GS), which accelerate breeding cycles. Marker-assisted selection (MAS) plays a critical role in developing superior maize varieties. The review also encompasses agronomic practices and technological innovations, including GS, aimed at climate mitigation. High-throughput phenotyping and omics-based approaches, including transcriptomics and metabolomics, are essential tools for developing climate-resilient maize. Climate changes have a significant impact on maize production and pose unprecedented challenges to its cultivation. Full article

To address the current limitations of spaceborne solid-state storage systems that cannot effectively support the parallel storage of multiple high-speed data streams, the throughput bottleneck of NAND FLASH-based solid-state storage systems was analyzed in relation to the high-speed data input requirements of payloads. A four-stage pipeline operation and bus parallel expansion scheme was proposed to enhance the throughput. Additionally, to support the parallel storage of multichannel data and continuity of pipeline loading, the shortcomings of existing caching schemes were analyzed, leading to the design of a storage system based on Synchronous Dynamic Random Access Memory (SDRAM). Model simulations indicate that, under extreme conditions, the proposed scheme could continuously receive and cache multiple high-speed file data streams into the SDRAM. File data were dynamically written into FLASH based on the priority and status of each partition cache autonomously, without overflow during caching. The system eventually entered a regular dynamic balance scheduling state to achieve parallel reception, caching, and autonomous scheduling of storage for multiple high-speed payload data streams. The data throughput rate of the storage system can reach 4 Gbps, thus satisfying future requirements for multichannel high-speed payload data storage in spaceborne solid-state storage systems. Full article

Blockchain technology uses a consensus mechanism to create and finalize blocks. The consensus mechanism affects the total performance parameters of the blockchain network, such as throughput. In this paper, we present “Nazfast”, a simplified proof of stake—Byzantine fault tolerance based consensus mechanism to create and finalize blocks. The presented consensus is completed in multiple folds. For block producer and validation committee selection, we used a secure and speeded-up election mechanism, S&Sem, in Nazfast. The consensus is designed for fast block finalization in a malicious environment. The simulation result shows that we approximately achieved three block finalizations in 1 s with almost similar latency. We reduced and fixed the number of validators in the consensus to improve the throughput. We achieved a higher throughput among other consensus of the same family. Because we reduced the number of validators, the safety parameters of the consensus are at risk, so we used Sea Shield to improve the overall consensus safety. This is another blockchain to save nodes’ details when they join/unjoin the network as validators. By using all three parts together, our system is protected from 28-plus different attacks, and we maintain a high decentralization by using S&Sem. Finally, we also enhance the incentive mechanism of consensus to improve the liveness of the network. Full article