Search Results (29)

The earth pressure balance shield machine (EPB) is an important piece of engineering equipment used in tunnel excavation and plays an important role in large underground tunnel projects. This article takes the sand and gravel formation as the research object, while discrete element simulation is utilized to study the correlation between cutterhead torque and thrust and other parameters. The EPB tunneling experiment was carried out by setting up formations with different sand and gravel contents. The reliability of the simulation model was verified by the experimental data, which provided the data samples for the training of the excavation formation identification network. Finally, a GTNet (gated Transformer network) based on the formation identification method was proposed. The reliability of the network model was verified by contrasting the model used with other network models and by analyzing the results of experiment and visualization. The effects of different parameters were weighted using the ablation study for tunneling parameters. The proposed method has a high accuracy of 0.99, and the cutterhead torque and thrust have a great recognition feature, the weight of which is over 0.95. This paper can provide significant guidance for the torque and thrust analysis of cutterheads in tunnel construction. Full article

This paper investigates 6.5 kV SiC trench gate p-channel IGBTs using Sentaurus TCAD simulations. The proposed superjunction structure is compared to conventional designs to highlight its advantages. The p-IGBT, fabricated on an n-type substrate, offers notable commercial advantages over n-IGBTs on p-type substrates. The n-shield can effectively protect the trench gate oxide in the corners of SiC. The n-shield and n-pillar can be either floating or grounded, with the floating shield condition significantly enhancing injection and improving forward conduction performance. The superjunction floating shield p-IGBT (SJFS-p-IGBT) improves forward conduction voltage (V_F) by 47% and 15% compared to conventional planar gate p-IGBT (CP-p-IGBT) and grounded shield p-IGBT (CGS-p-IGBT), respectively. For switching characteristics, the superjunction grounded shield p-IGBT (SJGS-p-IGBT) improves turn-off time (t_off) by 15% compared to the conventional floating shield p-IGBT (CFS-p-IGBT). The trade-off between V_F and turn-off energy (E_off) is analyzed, showing that the SJFS-p-IGBT offers a better trade-off. A negative temperature coefficient is observed at high buffer layer doping concentration and elevated temperatures, leading to an increase in V_F. This provides design guidance for devices operating in parallel at high temperatures. These results demonstrate the SJ’s potential to enhance efficiency and performance for ultra-high voltage applications. Full article

This study systematically investigates the mechanism by which total ionizing dose (TID) affects the lifetime degradation of NMOS devices induced by hot-carrier injection (HCI). Experiments involved Cobalt-60 (Co-60) gamma-ray irradiation to a cumulative dose of 500 krad (Si), followed by 168 h annealing at 100 °C to simulate long-term stability. However, under HCI stress conditions (V_D = 2.7 V, V_G = 1.8 V), irradiated devices show a 6.93% increase in threshold voltage shift (ΔV_th) compared to non-irradiated counterparts. According to the IEC 62416 standard, the lifetime degradation of irradiated devices induced by HCI stress is only 65% of that of non-irradiated devices. Conversely, when the saturation drain current (I_Dsat) degrades by 10%, the lifetime doubles compared to non-irradiated counterparts. Mechanistic analysis demonstrates that partial neutralization of E’ center positive charges at the gate oxide interface by hot electrons weakens the electric field shielding effect, accelerating ΔV_th drift, while interface trap charges contribute minimally to degradation due to annealing-induced self-healing. The saturation drain current shift degradation primarily correlates with electron mobility variations. This work elucidates the multi-physics mechanisms through which TID impacts device reliability and provides critical insights for radiation-hardened design optimization. Full article

Background/Objectives: Lutetium-177 is a widely used radioisotope in targeted radionuclide therapy, particularly for treating certain types of cancers relying on beta and low-energy gamma emissions, making it suitable for both therapeutic and post-therapy monitoring purposes. The purpose of this study was to evaluate the technical parameters for developing a prototype portable gamma camera dedicated to ¹⁷⁷Lu imaging applications. Methods: The well-validated GATE Monte Carlo toolkit was used to study the characteristics of the system and evaluate its performance in terms of spatial resolution, sensitivity, and image quality. For this purpose, a series of Monte Carlo simulations were executed, modeling a channel-edge aperture pinhole collimator incorporating a variety of computational phantoms. The final configuration of the prototype was standardized, incorporating the crystal size, collimator design, shielding, and the optimal FOV. After the development of the actual prototype camera, the system was also validated experimentally on the same setups as the simulations. Results: The final configuration of the prototype imaging system was standardized based on simulation results and then experimentally validated using physical phantoms under equivalent conditions. A minification of 1:5, spatial resolution of 1.0 cm, and sensitivity of 5.2 Cps/MBq at 10 cm distance source-to-collimator distance were assessed and confirmed. The experimental results agreed within 5% of simulated values. Conclusions: This study establishes the technical feasibility and foundational performance of a portable pinhole imaging system for potential clinical use in ¹⁷⁷Lu imaging workflows and thereby improving therapeutic effectiveness. Full article

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article

In this study, we propose an optimized shield gate trench 4H-SiC structure with effective gate oxide protection. The proposed device has a split trench with a P+ shield region, and the P+ shield is grounded by the middle deep trench. Our simulation results show that the peak electric field near the gate oxide is almost completely suppressed. Compared with a conventional P+ shield device, our proposed structure achieves a 78% reduction in the Q_gd and a 108% increase in the FoM (figure of merit) simultaneously. Additionally, it is estimated that the device cell pitch can be reduced to 1.8 μm with a R_on below 0.94 mΩ·cm², in theory. These demonstrated device performance metrics, as well as its simple structure and good compatibility, make our proposed SiC MOSFET highly attractive for future high-performance applications. Full article

A 4H-silicon carbide (SiC) trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) with dual integrated Schottky barrier diodes (SBDs) was characterized using numerical simulations. The advantage of three-dimensional stacked integration is that it allows the proposed structure to obtain an electric field of below 0.6 MV/cm in the gate oxide and SBD contacts and achieve ~10% lower forward voltage of SBDs than the planar gate SBD-integrated MOSFET (PSI-MOS) and the trench gate structure with three p-type-protecting layers (TPL-MOS). The dual-SBD-integrated MOSFET (DSI-MOS) also highlights the better influences of the more than 70% reduction in the miller charge, as well as the over 50% reduction in switching loss compared to the others. Furthermore, the short-circuit (SC) robustness of the three devices was identified. The DSI-MOS attains the critical energy and the aluminum melting point in a longer SC time interval than the TPL-MOS. The p-shield layers in the DSI-MOS are demonstrated to yield the huge benefit of improving the reliability of the contacts when SC reliability is considered. Full article

This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters’ degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability. Full article

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆V_th) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (C_rss), while maintaining a similar low ON-resistance. Full article

Silicon nanowire field effect (SiNW-FET) biosensors have been successfully used in the detection of nucleic acids, proteins and other molecules owing to their advantages of ultra-high sensitivity, high specificity, and label-free and immediate response. However, the presence of the Debye shielding effect in semiconductor devices severely reduces their detection sensitivity. In this paper, a three-dimensional stacked silicon nanosheet FET (3D-SiNS-FET) biosensor was studied for the high-sensitivity detection of nucleic acids. Based on the mainstream Gate-All-Around (GAA) fenestration process, a three-dimensional stacked structure with an 8 nm cavity spacing was designed and prepared, allowing modification of probe molecules within the stacked cavities. Furthermore, the advantage of the three-dimensional space can realize the upper and lower complementary detection, which can overcome the Debye shielding effect and realize high-sensitivity Point of Care Testing (POCT) at high ionic strength. The experimental results show that the minimum detection limit for 12-base DNA (4 nM) at 1 × PBS is less than 10 zM, and at a high concentration of 1 µM DNA, the sensitivity of the 3D-SiNS-FET is approximately 10 times higher than that of the planar devices. This indicates that our device provides distinct advantages for detection, showing promise for future biosensor applications in clinical settings. Full article

A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (TMOS) with depletion-mode pMOS (D-pMOS) is proposed and investigated via TCAD simulation. It has an auxiliary gate electrode that controls the electrical connections of P-shield layers under the trench bottom through the D-pMOS. In linear operation, the D-pMOS is turned off and then the potential of the P-shield layers is raised with the auxiliary gate, which shrinks the width of the depletion region of the P-shield/N-drift junction to reduce the resistance of the JFET region. In the saturation operation, the saturation current density of the proposed TMOS is reduced, benefiting from its relatively large cell pitch. The design concept eases the tension between specific on-resistance and short circuit capabilities. Numerical simulation results show that the proposed TMOS exhibits a short circuit withstand time that is 1.92 times longer than that of the conventional TMOS. In addition, a drive tactic is introduced and optimized for the proposed TMOS, which requires only one set of gate drivers. Compared with the conventional TMOS, the switching performance is improved and the switching loss is reduced by 40%. Full article

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t_sc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (R_on,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Q_gd) and gate-drain capacitance (C_gd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process. Full article

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug‘s N-type doping scheme is proposed to avoid the current dropping anomaly. Full article

In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons appears because of the LBD; thus, a path that makes it easier for electrons to transfer from the N+ source to the drift region is provided, finally eliminating the bipolar degradation of the body diode. At the same time, the LBD integrated in the P-well region weakens the scattering effect of interface states on electrons. Compared with the gate p-shield trench 4H-SiC MOSFET (GPMOS), the reverse on-voltage (V_F) is reduced from 2.46 V to 1.54 V; the reverse recovery charge (Q_rr) and the gate-to-drain capacitance (C_gd) are 28% and 76% lower than those of the GPMOS, respectively. The turn-on and turn-off losses of the DT-LBDMOS are reduced by 52% and 35%. The specific on-resistance (R_ON,sp) of the DT-LBDMOS is reduced by 34% due to the weaker scattering effect of interface states on electrons. The HF-FOM (HF-FOM = R_ON,sp × C_gd) and the P-FOM (P-FOM = BV²/R_ON,sp) of the DT-LBDMOS are both improved. Using the unclamped inductive switching (UIS) test, we evaluate the avalanche energy of devices and the avalanche stability. The improved performances suggest that DT-LBDMOS can be harnessed in practical applications. Full article

A novel Performance Optimized Carrier Stored Trench Gate Bipolar Transistor (CSTBT) with Low Switching Loss has been proposed. By applying a positive DC voltage to the shield gate, the carrier storage effect is enhanced, the hole blocking capability is improved and the conduction loss is reduced. The DC biased shield gate naturally forms inverse conduction channel to speed up turn-on period. Excess holes are conducted away from the device through the hole path to reduce turn-off loss (E_off). In addition, other parameters including ON-state voltage (V_on), blocking characteristic and short circuit performance are also improved. Simulation results demonstrate that our device exhibits a 35.1% and 35.9% decrease in E_off and turn-on loss (E_on), respectively, in comparison with the conventional shield CSTBT (C_on-SGCSTBT). Additionally, our device achieves a short-circuit duration time that is 2.48 times longer. In high-frequency switching applications, device power loss can be reduced by 35%. It should be noted that the additional DC voltage bias is equivalent to the output voltage of the driving circuit, enabling an effective and feasible approach towards high-performance power electronics applications. Full article