Search Results (1,238)

Detecting rotated parabolic shapes in digital images remains a significant challenge in computer vision, especially in embedded environments constrained by computational and memory resources. This study introduces a novel field-programmable gate array (FPGA)-based genetic algorithm (GA) architecture specifically tailored for rotated parabola detection, implemented as an intellectual property (IP) core on a PYNQ-Z1 system-on-chip (SoC) platform. The architecture encodes four parabola parameters into fixed-length chromosomes, assesses their geometric consistency with a 640 × 480 binary edge image using a hardware fitness function, and executes the entire evolutionary process in programmable logic. Image pre-processing is executed on an external CPU, using Canny edge detection for synthetic images and Holistically Nested Edge Detection (HED). For real images, post-processing and result visualization are conducted on the ARM processor using the PYNQ framework. Experimental results on synthetic images demonstrate mean accuracies of 98.47% and 95.23%, with detection success rates of up to 96%. For real images, since manually annotated ground truth is not available, results are presented as qualitative observations of convergence consistency across 100 independent runs. These findings demonstrate the feasibility of detecting rotated parabolas on resource-constrained embedded platforms and indicate promising applications in domains where parabolic patterns are prevalent, such as structural inspection, biomedical imaging, and perception modules for autonomous vehicles and driver-assistance systems. Full article

With the development of space-based cloud computing and on-orbit intelligent processing, higher requirements have been imposed on standardized network interconnection for spaceborne platforms. However, constrained by size, power consumption, thermal design, and structural layout, some spaceborne platforms lack physical Ethernet interfaces and therefore cannot directly support standard Internet Protocol version 6 (IPv6) communications. In addition, harsh spaceborne operating conditions, including thermal-vacuum stress and potential radiation-induced disturbances, increase the risk of link anomalies, state inconsistency, and service interruption. To address these issues, this paper proposes a reliability-enhanced IPv6 access and transmission method for spaceborne platforms without physical Ethernet interfaces. On the processor side, a network TAP interface is established to reconstruct the semantics of a standard Layer-2 network device. Combined with a cooperative central processing unit–field-programmable gate array (CPU–FPGA) link-carrying mechanism, the proposed method enables transparent IPv6 access without modifying the native Linux protocol stack. To satisfy both standard spacecraft onboard network services and high-throughput engineering data transmission, a dual-channel architecture is designed, in which the service network channel is separated from the engineering data channel. In addition, a hierarchical reliability-oriented mechanism is constructed, consisting of hardware-level fault-tolerance design, reliable link interaction, status monitoring, and redundancy takeover. Experimental validation is conducted on a CPU-FPGA prototype platform under a thermal-vacuum environment and representative abnormal operating scenarios. The results show that the proposed method can stably support IPv6 address configuration, neighbor discovery, and end-to-end communication. Under zero-packet-loss conditions, the service network channel achieves an average stable throughput of 173.8 Mb/s, while the engineering data channel achieves a stable throughput of approximately 3.4 Gb/s. The system also demonstrates good service continuity during long-duration operation and under typical abnormal scenarios. The proposed method provides a verifiable system-level solution for realizing standardized IPv6 network access and reliability-enhanced data transmission on interface-constrained spaceborne platforms. Full article

Floating-point arithmetic provides the dynamic range that fixed-point lacks for digital signal processing (DSP) algorithms with widely varying operand magnitudes. This work presents a parameterizable floating-point unit set for field programmable gate array (FPGA)-based DSP. The set consists of five units: adder/subtractor, multiplier, multiply–accumulate (MAC), fixed-to-float and float-to-fixed converters. Two architectural choices distinguish the proposed format from IEEE-754: configurable exponent and mantissa widths during synthesis and a $0.f$ significand encoding that reduces corner-case logic at the cost of one additional mantissa bit. The format is therefore IEEE-754-inspired rather than fully compliant: special values (NaN, ±∞) are not implemented, and overflow and underflow are handled through saturation to predefined constants. The design is implemented in standard VHDL-2008 without relying on high-level synthesis (HLS) tools or vendor-specific primitives, ensuring portability across different FPGA families and application-specific integrated circuits (ASICs). The multiplier and MAC are evaluated in two configurations: inferring DSP blocks or look-up table (LUT)-only, both close timing at 300MHz on Artix-7 and Kintex Ultrascale devices. The proposed blocks outperform vendor IP Cores and recent academic designs in terms of area-throughput-power (ATP), achieving improvements from 10% to 108%, except for the adder/subtractor, which does not outperform two optimized Xilinx IP cores (HS-R and HS-P) and is therefore included for design coherence rather than as a strict resource improvement over all vendor IPs. All these blocks meet the theoretical error bound, and a representative 200-tap finite impulse response (FIR) filter built from them closes timing at 300MHz with 76% LUT utilization. Full article

Field-Programmable Gate Array (FPGA) technology allows for the creation of unique hardware implementations based on mass-produced chips. The process of project prototyping for such systems using Hardware Description Languages (HDLs) remains complex, even with modern tools. The comparison of HDL coding styles, for example, a behavioral case statement against a structural binary-tree decomposition, shows that the choice is capable of affecting post-implementation timing and area. The performed study, using the open-source yosys/nextpnr toolchain, shows that the validity of such a comparison is decided by the fabric domain. Logic that falls through to generic Look-Up Table (LUT) mapping is governed by the mapper’s heuristic fixed point rather than by source intent: on the crossbar, the behavioral and structural netlists become identical in cell composition; on the priority encoder, the verdict reverses; and on the barrel shifter, the LUT area collapses, so the comparison does not isolate the coding-style variable. It was measured that the keep_hierarchy attribute restores a meaningful comparison at ~17% LUT cost (N = 8) and provides a structural invariant to the ABC mapper variant, but the behavioral result is mapper-sensitive and the N = 4 verdict reverses under the legacy -noabc9 mapper (Cohen’s d from +2.4 to −1.6). By contrast, logic that involves a dedicated primitive before LUT mapping—an adder bound to the carry chain or a multiplier bound to a DSP block—yields source-meaningful verdicts that do not reverse with a mapper. Replication on a second fabric (Lattice iCE40) confirms that this behavior is fabric- rather than vendor-specific. The main contribution of this work is the proposed first fabric-domain characterization of synthesis canonicalization as a methodological hazard for cross-HDL FPGA studies on open-source toolchains, which identifies the two-phase synthesis mechanism that delimits it and supplies a decision rule (inspect post-synthesis composition) to identify whether a given comparison is susceptible. Full article

Field-programmable gate array (FPGA)-based reconfigurable system-on-chip (SoC) platforms are increasingly deployed in safety-critical domains such as autonomous driving and industrial automation, yet the existing literature lacks a systematic assessment of how these designs address functional safety requirements. This paper presents a systematic review of 36 peer-reviewed studies (core period 2010–2024, with historical context from 1998) on FPGA-based reconfigurable parallel processing SoCs, analyzed through three frameworks: a convergence–divergence analysis (CDA) that provides a structured exploratory lens for identifying research trajectory trends and informing hypothesis generation; a safety-critical gap analysis benchmarked against a three-layer standard framework comprising ISO 26262 (functional safety), ISO 21448/SOTIF (safety of the intended functionality), and ISO/PAS 8800 (AI safety properties); and a four-dimensional design space taxonomy spanning reconfigurability granularity, parallelism exploitation, design automation level, and safety criticality. The analysis reveals that 33 of the 36 surveyed studies (92%) ignore safety certification entirely. While recent work has begun establishing worst-case execution time (WCET) bounds for FPGA SoC platforms, none of the surveyed FPGA-based AI accelerator studies provide WCET bounds, although recent analytical models for multi-DPU architectures demonstrate the feasibility of such analysis. FPGA CNN accelerators achieve energy efficiencies of up to 60 GOPS/W, and dynamic partial reconfiguration (DPR) yields 2–5× throughput improvements, yet these gains remain unsupported by the formal verification or uncertainty quantification mandated for safety certification. The CDA framework reveals strong convergence between DPR, network-on-chip (NoC), and high-level synthesis research threads (scores 0.72–0.91), indicating maturation toward integrated design flows. We identify conformal prediction as a distribution-free hardware-compatible framework for uncertainty quantification on resource-constrained FPGAs, motivated by requirements from ISO 21448 (triggering event identification) and ISO/PAS 8800 (runtime confidence monitoring), and propose a prioritized research agenda to bridge the gap between FPGA performance optimization and safety-certified deployment in transportation systems. Full article

This paper presents a system-on-chip field-programmable gate array (SoC FPGA) acceleration architecture for graph-neural-network- and deep-reinforcement-learning (GNN–DRL)-based routing inference in low-Earth-orbit (LEO) satellite networks. Because LEO satellites move at high orbital speeds, the network topology changes continuously, and routing decisions must track the current link state rather than rely only on static rules. GNN-based DRL routing can represent the graph structure of the network when selecting paths, but its message-passing and readout stages are computationally expensive for resource-constrained onboard platforms. To address this limitation, the trained GNN routing model is ported to an SoC FPGA and implemented with a collaborative processing-system (PS) and programmable-logic (PL) architecture. The PS handles candidate-path generation, environment setup, path selection, and network-state updates, whereas the PL executes the computationally dominant message-passing neural network (MPNN) and readout layers. Post-training INT8 quantization, nonlinear-function approximation, vector-level parallelization, and a parallel multiply–accumulate structure are applied to reduce memory pressure and execution time. Experiments on a ZCU104 board using a PYNQ-controlled PS–PL implementation and an NSFNET-based routing environment show that the proposed PS–PL structure reduces the evaluation time from 94.08 s to 12.63 s compared with the PS-only implementation while maintaining an evaluation score close to that of the original model. Full article

The rapid growth of artificial intelligence (AI) workloads is reshaping semiconductor design across architecture, interconnect, memory hierarchy, packaging, timing, and design automation. Rather than converging on a single hardware solution, the field is expanding into a heterogeneous ecosystem that includes data-center graphics processing units (GPUs), edge neural processing units (NPUs), and application-specific integrated circuits (ASICs), field-programmable gate array (FPGA)-based and hybrid AI system-on-chip (SoC) platforms, chiplet-enabled systems, and emerging beyond-conventional-silicon approaches such as photonic, neuromorphic, and analog in-memory processors. This paper presents a comprehensive review of AI-on-chip systems from a cross-layer perspective. It examines AI chip architectures and hardware platforms, network-on-chip (NoC) designs for AI communication patterns, and algorithm–hardware co-design methods for model acceleration, including compression, quantization, and sparsity-aware optimization. It also reviews clocking, synchronization, and clock-domain-crossing (CDC) challenges in large heterogeneous systems and chiplets, as well as manufacturing, advanced packaging, and reliability issues, including two-and-a-half-dimensional (2.5D) and three-dimensional (3D) integration, thermal and mechanical constraints, assembly quality, and long-term yield considerations. In parallel, the paper surveys the growing role of AI in chip design itself, covering machine-learning-assisted analysis, Bayesian and reinforcement-learning-based optimization, and the emerging use of large language models (LLMs) and AI agents for register-transfer level (RTL) generation, design-space exploration, and autonomous electronic design automation (EDA) workflows. Finally, it discusses beyond-silicon AI chip directions and the broader economic and industry context shaping cloud, on-premises, and edge deployment. By integrating these topics into a unified framework, this review highlights the key technological drivers, system-level tradeoffs, and future research directions that will define next-generation scalable, reliable, and energy-efficient AI-on-chip systems. Full article

Image sensors produce high-dimensional visual data for classification algorithms. Deep Neural Networks (DNNs) achieve high accuracy but require large labeled datasets and computational and energy resources, limiting their use in embedded systems. Active Learning (ALrn) can reduce labeling effort by selecting samples based on informativeness scores, but it remains computationally expensive, especially for high-dimensional images. This work presents a hardware-accelerated approach for the instance selection stage based on a query strategy in uncertainty-based ALrn for image classification using a novel in-line top-k selection algorithm that avoids conventional sorting and reduces memory and computational requirements. The algorithm is implemented on an Xilinx ZYNQ-7000 System on Chip (SoC) using a Field Programmable Gate Array (FPGA)-based accelerator operating at 110 MHz, interfacing with an embedded Advanced RISC Machine (ARM) processor for data acquisition and communication via the Python Productivity for Zynq (PYNQ) framework. Experiments on diverse multiclass datasets demonstrate correctness within an ALrn setting, showing negligible performance deviation in the learning curves compared to software baselines. The accelerator achieves speedup of 231.7× and 22.9× over software baseline and optimized software implementation of the proposed algorithm, respectively, in query-strategy computation while consuming only 0.473 W, substantially lower than conventional Central Processing Unit (CPU)- and Graphics Processing Unit (GPU)-based platforms. These results demonstrate the efficiency and extensibility of the proposed accelerator across alternative ALrn designs and hardware platforms, where the computational cost of instance selection scales with the size of the unlabeled pool. Full article

We implemented a power grid fault detection scheme based on adaptive frequency tracking and an iterative discrete Fourier transform. We designed and verified the scheme on a Field-Programmable Gate Array (FPGA) development board, leveraging the inherent advantages of hardware parallel processing to overcome the speed and real-time limitations of traditional general-purpose processor-based solutions. The simulation results demonstrate that the FPGA implementation validates the effectiveness of the algorithm, achieving excellent performance in terms of resource utilization and power consumption. These findings provide a solid technical foundation for the development of specialized and miniaturized power grid protection devices. Full article

Alpha/beta (α/β) pulse shape discrimination (PSD) in liquid scintillation counting (LSC) is fundamentally limited by the charge comparison method (CCM) at low energies, where the entire tritium (³H) beta spectrum resides (0–18.6 keVee). The CCM figure-of-merit drops below 0.6 in this region, rendering it inadequate for simultaneous tritium and natural uranium alpha monitoring in nuclear power plant (NPP) liquid effluents. We present a one-dimensional convolutional neural network (1D-CNN) trained on an 80,000-waveform physics-based simulation dataset using established scintillation parameters for Ultima Gold AB. The proposed network achieves 97.4% overall classification accuracy and an area under the receiver operating characteristic curve (AUC) of 0.9981 on the held-out test set, representing improvements of 13.8 percentage points and 0.046 AUC over CCM. In the critical 0–18.6 keVee region, CNN accuracy exceeds 95% compared to below 60% for CCM—a greater than 35 percentage point improvement. Pulse amplitude discrimination (PAD), evaluated as a preliminary screening method, exhibits a 6.3% alpha spillover rate into the beta window, exceeding the regulatory limit of 3%. Gradient-weighted class activation maps (Grad-CAM) confirm that the network exploits physically meaningful pulse features rather than simulation artefacts. A comprehensive background suppression strategy combining dual-SiPM coincidence (24× reduction), anti-coincidence guard detector (5.8× reduction), composite passive shielding (10× reduction), and CNN-assisted discrimination reduces the system equivalent background to 1.83 ± 0.12 cpm, yielding a tritium minimum detectable activity (MDA) of 0.21 Bq/mL (10 mL sample, 30 min count), which satisfies the GB 14587 reference limit of 0.5 Bq/mL. After 8-bit post-training quantisation, the model achieves sub-microsecond inference latency on an embedded Xilinx Artix-7 Field-programmable gate array(FPGA), enabling real-time deployment in portable online monitoring systems. Full article

With the standardization of the Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM) in NIST FIPS 203 (2024), efficient hardware support for polynomial ring operations has become critical for practical post-quantum cryptography deployment. The dominant computational workload of ML-KEM arises from matrix–vector multiplications over polynomial rings, which involve repeated Number Theoretic Transform (NTT), pointwise multiplication, and modular addition operations. This work proposes an ML-KEM polynomial ring accelerator leveraging Open Intellectual Property (Open IP) and integrates it into an open hardware Chipyard RISC-V System on Chip (SoC) via a Memory-Mapped I/O (MMIO) interface. The design incorporates an NTT-based datapath with multiplier and adder arrays, and employs a scratchpad memory to enable intermediate data reuse and reduce memory access overhead. The proposed architecture is implemented on a Genesys 2 FPGA development board featuring a Kintex-7 XC7K325T Field Programmable Gate Array (FPGA) (Digilent Inc., Pullman, WA, USA) and evaluated at both kernel and system levels. Experimental results show that the accelerator reduces matrix–vector multiplication latency to 7372 cycles, achieving up to 40× speedup over a software baseline. At the SoC level, the complete ML-KEM implementation achieves performance improvements of 1.6× to 2.1× across different parameter sets. These results demonstrate that integrating Open IP within an open hardware SoC provides an effective and reproducible approach for accelerating ML-KEM. Full article

Convolutional Neural Network (CNN) accelerators are widely deployed in edge Artificial Intelligence (AI), embedded vision, and object detection systems, but their hardware designs often incur significant power consumption due to intensive multiply–accumulate (MAC) operations, frequent register toggling, memory transactions, and persistent signal switching. This study examines Register Transfer Level (RTL)-level power optimization of a CNN accelerator on a Field-Programmable Gate Array (FPGA) using three design approaches: a baseline, a Local Explicit Clock Gating (LECG) + Memory Split scheme, and a sparsity-aware scheme. The LECG + Memory Split approach reduces redundant sequential and memory-switching operations, while the sparsity-aware scheme further minimizes arithmetic operations on zero-valued operands. FPGA power measurements on a Xilinx ZCU102 platform reveal a total power decrease from 3.644 W in the baseline to 2.775 W with LECG + Memory Split and 2.442 W with sparsity-aware optimization. This achieves up to a 32.99% reduction in total power without increasing Digital Signal Processing (DSP) block or Block Random Access Memory (BRAM) usage. The findings confirm that integrating control-based, memory-aware, and data-aware RTL methods enhances the power efficiency of CNN accelerators while maintaining the main compute and memory architectures. Full article

Many machine learning and deep learning algorithms based on Artificial Neural Networks (ANNs) have been implemented on software platforms for handwritten digit and character recognition. However, an ANN is difficult to deploy on an embedded platform based on a Central Processing Unit (CPU) because of its large computation, complex structure, and frequent memory access. However, Field Programmable Gate Array (FPGA) devices facilitate this task and offer the capability to design fully customizable hardware architectures. Additionally, they provide high flexibility and high parallel computations based on parallel processing techniques, and they contain sufficient on-chip Digital Signal Processing (DSP) blocks useful for complicated multiplications. In this paper, we present a detailed FPGA-based implementation of a handwritten digit recognition system based on a Multi-Layer Perceptron (MLP) model. The internal modules of the network are designed using the VHSIC Hardware Description Language (VHDL) to achieve a high-level optimization on the hardware platform, and the functionality is simulated and tested using Vivado ISIM Tools. The system has been characterized to reach acceptable performance compared to previous approaches. After implementing the whole neural network on a Xilinx Pynq-Z2 board, it occupies in the device 20758 LUTs, 4426 FFs, 3.50 blocks of random-access memory (BRAM), and 42 DSPs. It reaches an execution time of 2.192 µs to recognize a handwritten number, while consuming only 0.36 Watts, and it achieves a classification accuracy of 97%. Additionally, the proposed architecture can be easily scaled on different FPGA devices thanks to its regularity. Therefore, it offers more portability of the architecture and can be used on different real embedded applications. Full article

This paper presents the design and implementation of a field-programmable gate array (FPGA)-based System-on-Programmable-Chip (SoPC) architecture for sensorless speed control of permanent magnet synchronous motor (PMSM) drives. To enable real-time execution of the computationally intensive estimation stage, a parallelized Unscented Kalman Filter (UKF) is proposed for the joint estimation of rotor speed, position, and load torque. Unlike traditional sequential processor-based UKF implementations, the proposed parallel architecture simplifies the iterative process and significantly reduces computational latency and hardware resource utilization while preserving high estimation fidelity. This transformation reduces the number of sequential dependency stages within one estimation cycle and enables simultaneous execution of matrix operations using dedicated FPGA resources, thereby decreasing effective iteration latency. The complete control system comprises current regulators, a coordinate transformation module, a proportional–integral (PI) speed controller, and auxiliary functional blocks—all fully integrated within a single SoPC. The UKF estimator and control components are described using a hardware description language (HDL), enabling efficient hardware-level parallelism and real-time execution. The proposed system is validated through co-simulation and experimental verification on a Xilinx ZCU102 platform driving an inverter-fed PMSM. The results confirm correct real-time operation of the proposed architecture and demonstrate its feasibility for FPGA-based sensorless motor drive implementation. A detailed quantitative comparison with a fully sequential FPGA-based UKF implementation is identified as future work to further substantiate the reported latency reduction. Full article

The accuracy of transit-time ultrasonic flow measurement depends strongly on stable time-of-flight (TOF) extraction. However, threshold-based TOF methods are susceptible to emission transients, structural ringing, and repeated threshold crossings, which may cause false triggering and timing fluctuations. This paper proposes a time-of-flight extraction method based on time-sequenced pulses for ultrasonic flow measurement using an FPGA-based time-to-digital converter (TDC). The method equalizes signal input paths, combines peripheral path switching with FPGA gating to achieve windowed valid-edge extraction, and exploits the temporal correspondence among consecutive excitation pulses to construct multiple TOF observations from matched pulse pairs, thereby improving extraction stability and timing efficiency. A complete FPGA-TDC ultrasonic flow measurement platform based on a Zynq UltraScale+ device was developed, and TDC linearity, timing precision, and flow calibration experiments were conducted. After code-density calibration, the four channels achieved RMS values of about 20 ps, and within a flow range of 0.7–3.6 m³/h, the relative error with respect to the reference flowmeter remained within ±0.6%, with repeatability errors below 0.3%. The platform operated stably under the present experimental conditions. These results demonstrate improved TOF extraction stability and overall flow measurement performance without complex full-waveform processing. Full article