Search Results (12)

Artificial intelligence (AI) has become ubiquitous in modern computing systems, from high-performance data centers to resource-constrained edge devices. As AI applications continue to expand into mobile and IoT domains, the need for energy-efficient neural network implementations has become increasingly critical. To meet this requirement of energy-efficient computing, this work presents a BWNN (binary-weighted neural network) architecture implemented using FeRAM (Ferroelectric RAM)-based synaptic arrays. By leveraging the non-volatile nature and low-power computing of FeRAM-based CIM (computing in memory), the proposed CIM architecture indicates significant reductions in both dynamic and standby power consumption. Simulation results in this paper demonstrate that scaling the ferroelectric capacitor size can reduce dynamic power by up to 6.5%, while eliminating DRAM-like refresh cycles allows standby power to drop by over 258× under typical conditions. Furthermore, the combination of binary weight quantization and in-memory computing enables energy-efficient inference without significant loss in recognition accuracy, as validated using MNIST datasets. Compared to prior CIM architectures of SRAM-CIM, DRAM-CIM, and STT-MRAM-CIM, the proposed FeRAM-CIM exhibits superior energy efficiency, achieving 230–580 TOPS/W in a 45 nm process. These results highlight the potential of FeRAM-based BWNNs as a compelling solution for edge-AI and IoT applications where energy constraints are critical. Full article

An overview of the steps employed to advance non-volatile Pb(Zr_xTi_1−x)O₃-based materials from parallel capacitor array test structures to embedded 130 nm (1.5 V operation) memory product release is presented. Specific development stages include parallel capacitor array evaluation, capacitor characterization array development, memory macro creation and measurement, and initial product design and qualification. Representative data, learning goals, and critical outputs will be presented for each development phase. We note that the cost and complexity of the development effort increase dramatically as the new technology approaches high-volume manufacturing. We hope that the documentation of our experiences in this manuscript may be of assistance to those teams striving to create the next generations of non-volatile embedded memory technology. Full article

In this work, we analyze the thermodynamic principles underlying modern data storage systems, including Random Access Memory (RAM), hard disk drive (HDD), flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and phase-change RAM (PCRAM), as well as other less well-known data storage mechanisms. The analysis is conducted in the context of data storage and processing in relation to Landauer’s principle, with special emphasis on hysteresis. Analogous to how heat engines are characterized by thermodynamic cycles, data storage systems are examined in terms of the hysteresis loop of their fundamental data unit. We explore the role of heat in data storage systems. Afterward, we introduce the concept of temperature gradient memory (TeGraM) along with a detailed layout of a realizable device. Experimental results demonstrating this technology are also presented. Full article

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string. Full article

To be CMOS-compatible, a low preparation temperature (<500 °C) for ferroelectric films is required. In this study, BiFeO₃ films were successfully fabricated at a low annealing temperature (<450 °C) on aluminum foils by a metal–organic decomposition process. The effect of the annealing atmosphere on the performance of BiFeO₃ films was assessed at 440 ± 5 °C. By using a N₂-rich atmosphere, a large remnant polarization (P_r~78.1 μC/cm² @ 1165.2 kV/cm), and a high rectangularity (~91.3% @ 1165.2 kV/cm) of the P-E loop, excellent charge-retaining ability of up to 1.0 × 10³ s and outstanding fatigue resistance after 1.0 × 10⁹ switching cycles could be observed. By adopting a N₂-rich atmosphere and aluminum foil substrates, acceptable electrical properties (P_r~70 μC/cm² @ 1118.1 kV/cm) of the BiFeO₃ films were achieved at the very low annealing temperature of 365 ± 5 °C. These results offer a new approach for lowering the annealing temperature for integrated ferroelectrics in high-density FeRAM applications. Full article

In this work, 10 nm scandium-doped aluminum nitride (AlScN) capacitors are demonstrated for the construction of the selector-free memory array application. The 10 nm Al_0.7Sc_0.3N film deposited on an 8-inch silicon wafer with sputtering technology exhibits a large remnant polarization exceeding 100 µC/cm² and a tight distribution of the coercive field, which is characterized by the positive-up-negative-down (PUND) method. As a result, the devices with lateral dimension of only 1.5 μm show a large memory window of over 250% and a low power consumption of ~40 pJ while maintaining a low disturbance rate of <2%. Additionally, the devices demonstrate stable multistate memory characteristics with a dedicated operation scheme. The back-end-of-line (BEOL)-compatible fabrication process, along with all these device performances, shows the potential of AlScN-based capacitors for the implementation of the high-density selector-free memory array. Full article

Ferroelectric scandium-doped aluminum nitride (Al_1-xSc_xN) is of considerable research interest because of its superior ferroelectricity. Studies indicate that Al_1-xSc_xN may suffer from a high leakage current, which can hinder further thickness scaling and long-term reliability. In this work, we systematically investigate the origin of the leakage current in Al_0.7Sc_0.3N films via experiments and theoretical calculations. The results reveal that the leakage may originate from the nitrogen vacancies with positively charged states and fits well with the trap-assisted Poole-Frenkel (P-F) emission. Moreover, we examine the cycling behavior of ferroelectric Al_0.7Sc_0.3N-based FeRAM devices. We observe that the leakage current substantially increases when the device undergoes bipolar cycling with a pulse amplitude larger than the coercive electric field. Our analysis shows that the increased leakage current in bipolar cycling is caused by the monotonously reduced trap energy level by monitoring the direct current (DC) leakage under different temperatures and the P-F emission fitting. Full article

Hafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Access Memory) still faces challenges related to endurance and retention susceptibility to process variations. Hence, testing and obtaining the core parameters of ferroelectric capacitors continuously is essential to investigate these phenomena and explore the potential solution. The traditional method for measuring ferroelectric capacitors has limitations in timing generation capability, introduces parasitic capacitance, and lacks accuracy for small-area capacitors. In this study, we analyzed the working principle of ferroelectric capacitors and designed a method to detect the remnant polarization, saturation polarization, and imprint offset of ferroelectric capacitors. Further, we further proposed a circuit implementation method. The proposed test circuit conquers these limitations and enables high-precision testing of ferroelectric capacitors, contributing to developing hafnium-based ferroelectric memories. The circuit includes a flip-readout circuit, a capacitance calibration circuit, and a voltage-to-time converter and time-to-digital converter (VTC&TDC) readout circuit. According to simulation results, the capacitance calibration circuit reduces the deviation of the capacitance by 84%, and the accuracy of the readout circuit is 5.91 bits, with a readout time of 150 ns and a power consumption of 1 mW. This circuit enables low-cost acquisition of array-level small-area ferroelectric capacitance data, which can guide subsequent device optimization and circuit design. Full article

Hf_0.5Zr_0.5O₂-based multi-level cell (MLC) ferroelectric random-access memory (FeRAM) has great potential for high-density storage applications. However, it is usually limited by the issues of a small operation margin and a large input offset. The study of circuit design and optimization for MLC FeRAM is necessary to solve these problems. In this work, we propose and simulate a configuration for a Hf_0.5Zr_0.5O₂-based 3TnC MLC FeRAM macro circuit, which also presents a high area efficiency of 12F² for each bit. Eight polarization states can be distinguished in a single fabricated Hf_0.5Zr_0.5O₂-based memory device for potential MLC application, which is also simulated by a SPICE model for the subsequent circuit design. Therein, a nondestructive readout approach is adopted to expand the reading margin to 450 mV between adjacent storage levels, while a capacitorless offset-canceled sense amplifier (SA) is designed to reduce the offset voltage to 20 mV, which improves the readout reliability of multi-level states. Finally, a 4 Mb MLC FeRAM macro is simulated and verified using a GSMC 130 nm CMOS process. This study provides the foundation of circuit design for the practical fabrication of a Hf_0.5Zr_0.5O₂-based MLC FeRAM chip in the future, which also suggests its potential for high-density storage applications. Full article

The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash memory systems, the large voltage required to erase the charge of nonvolatile memory cells, and the limitations of scaled-down systems. Ferroelectric materials are one exciting means of breaking away from this structure, as Hf-based ferroelectric materials have a low operating voltage, excellent data retention qualities, and show fast switching speed, and can be used as non-volatile memory (NVM) if polarization characteristics are utilized. Moreover, adjusting their conductance enables diverse computing architectures, such as neuromorphic computing with analog characteristics or ‘logic-in-memory’ computing with digital characteristics, through high integration. Several types of ferroelectric memories, including two-terminal-based FTJs, three-terminal-based FeFETs using electric field effect, and FeRAMs using ferroelectric materials as capacitors, are currently being studied. In this review paper, we include these devices, as well as a Fe-diode with high on/off ratio properties, which has a similar structure to the FTJs but operate with the Schottky barrier modulation. After reviewing the operating principles and features of each structure, we conclude with a summary of recent applications that have incorporated them. Full article

The discovery of ferroelectricity in HfO₂ thin film, which is compatible with the CMOS process, has revived interest in ferroelectric memory devices. HfO₂ has been found to exhibit high ferroelectricity at a few nanometers thickness, and studies have rapidly progressed in the past decade. Ferroelectricity can be induced in HfO₂ by various deposition methods and heat treatment processes. By combining ferroelectric materials with field-effect transistors, devices that combine logic and memory functions can be implemented. Ferroelectric HfO₂-based devices show high potential, but there are some challenges to overcome in endurance and characterization. In this paper, we discuss the fabrication and characteristics of ferroelectric HfO₂ film and various applications, including negative capacitance (NC)), Ferroelectric random-access memory (FeRAM), Ferroelectric tunnel junction (FTJ), and Ferroelectric Field-effect Transistor (FeFET). Full article

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues. Full article